Datasheet SP6132H Datasheet (Sipex)

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Page 1

SP6132H

High Voltage, 300KHz Synchronous PWM Controller

FEATURES

■ 3V to 28V Step Down Achieved Using Dual Input

■ 2A to 15A Ouput Capability

■ Highly Integrated Design, Minimal Components

■ UVLO Detects Both VCC and V

■ Short Circuit Protection with Auto-Restart

■ On-Board 1.5Ω sink (2Ω source) NFET Drivers

GND

COMP

SP6132H

10 Pin MSOP

BST

SWN

UVIN

Now Available in Lead Free Packaging

■ Wide BW Amp Allows Type II or III Compensation

■ Programmable Soft Start

■ Fast Transient Response

■ High Efficiency: Greater than 95% Possible

■ A Synchronous Start-Up into a Pre-Charged Output

■ Small 10-Pin MSOP Package

APPLICATIONS

■ Wireless Base Station

■ Automotive

■ Industrial

■ Power Supply

DESCRIPTION

The SP6132H is a synchronous step-down switching regulator controller optimized for high efficiency. The part is designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower V voltage minimizes power dissipation in the part. The SP6132H is designed to drive a pair of external NFETs using a fixed 300kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown and

output short circuit protection. The SP6132H is available in the cost and space saving 10-pin MSOP.

TYPICAL APPLICATION CIRCUIT

VIN

3.0 - 28V

22µF

FDS7088N3

2.7µH @ 12A

100pF

SP6132H

GND

VFB

COMP

1500pF

22pF

BST

SWN

UVIN

27.4k, 1%

5.11, 1%

1µF

47nF

FDS7088N3

47µF

220pF

4.64k, 1%

47µF

MBR0530

221k, 1%

100k, 1%

10µF

0.1µF

GND

2.5V 10 A

OUT

68.1k, 1%

31.6k, 1%

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These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC.................................................................................................. 7V

BST ............................................................................................... 33V

BST-SWN ......................................................................... -0.3V to 7V

SWN ................................................................................... -1V to 30V

GH ......................................................................... -0.3V to BST+0.3V

GH-SWN ......................................................................................... 7V

All other pins .......................................................... -0.3V to VCC+0.3V

ABSOLUTE MAXIMUM RATINGS

Peak Output Current < 10us

GH,GL ............................................................................................. 2A

Storage Temperature .................................................. -65°C to 150°C

Power Dissipation .......................................................................... 1W

Lead Temperature (Soldering, 10 sec) ...................................... 300°C

ESD Rating .......................................................................... 2kV HBM

Thermal Resistance ............................................................. 41.9°C/W

Unless otherwise specified: 0°C < T C

= 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF, Typical measured at VCC=5V. The ♦ denotes the specifications which

COMP

apply over the -40°C to 85°C temperature range, unless otherwise specified.

PARAMETER MIN TYP MAX UNITS CONDITIONS QUIESCENT CURRENT

VCC Supply Current 1.5 3 mA BST Supply Current 0.2 0.4 mA

PROTECTION: UVLO

VCC UVLO Start Threshold 4.00 4.25 4.5 V VCC UVLO Hysteresis 100 200 300 mV

UVIN Start Threshold 2.3 2.5 2.65 V

UVIN Hysteresis 200 300 400 mV UVIN Input Current 1 µA UVIN =3.0V

ERROR AMPLIFIER REFERENCE

Error Amplifier Reference 0.792 0.800 0.808 V 2X Gain Config., Measure VFB Error Amplifier Reference 0.788 0.800 0.812 V

Over Line and Temperature Error Amplifier Transconductance 6 ms Error Amplifier Gain 60 dB No Load COMP Sink Current 150 µAV COMP Source Current 150 µAV VFB Input Bias Current 50 200 nA Internal Pole 4 MHz COMP Clamp 2.5 V VFB=0.7V, TA = 25°C COMP Clamp Temp. Coefficient -2 mV/°C

CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH

Ramp Amplitude 0.92 1.1 1.28 V RAMP Offset 1.1 V TA = 25°C, RAMP COMP

RAMP Offset Temp. Coefficient -2 mV/°C GH Minimum Pulse Width 90 180 ns Maximum Controllable Duty Ratio 92 97 %

Maximum Duty Ratio 100 % Valid for 20 Cycles Internal Oscillator Frequency 255 300 345 kHz

< 70°C, 4.5V < V

AMB

240 300 360

< 5.5V, BST=VCC,SWN = GND = 0V, UVIN = 3.0V, CVCC = 10µF,

♦

=0.9V (No switching)

♦

=0.9V (No switching)

♦

= 0.9V, COMP = 0.9V

= 0.7V, COMP = 2.2V

♦

VFB = 0.8V

♦

until GH starts switching

♦

Maximum Duty Ratio Measured just before pulse skipping begins

♦

ELECTRICAL SPECIFICATIONS

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Unless otherwise specified: 0°C < T C

= 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF, Typical measured at VCC=5V. The ♦ denotes the specifications which

COMP

apply over the full operating temperature range, unless otherwise specified.

PARAMETER MIN TYP MAX UNITS CONDITIONS TIMERS: SOFTSTART

SS Charge Current: 10 µA SS Discharge Current: 1 mA

PROTECTION: SHORT CIRCUIT & THERMAL

Short Circuit Threshold Voltage 0.2 0.25 0.3 V Measured V Hiccup Timeout 200 ms VFB = 0.5V Number of Allowable Clock Cycles 20 Cycles VFB = 0.7V

at 100% Duty Cycle Minimum GL Pulse After 20 Cycles 0.5 Cycles VFB = 0.7V Thermal Shutdown Temperature 145 °C Thermal Recovery Temperature 135 °C Thermal Hysteresis 10 °C

OUTPUT: NFET GATE DRIVERS

GH & GL Rise Times 35 50 ns GH & GL Fall Times 30 40 ns GL to GH Non Overlap Time 45 70 ns SWN to GL Non Overlap Time 25 40 ns GH & GL Pull Down Resistance 15 50 85 KΩ

< 70°C, 4.5V < V

AMB

< 5.5V, BST=VCC,SWN = GND = 0V, UVIN = 3.0V, CVCC = 10µF,

♦

Fault Present, SS = 0.2V

(0.8V) - V

REF

♦

Measured 10% to 90%

♦

Measured 90% to 10%

♦

GH & GL Measured at 2.0V

♦

Measured SWN = 100mV to GL = 2.0V

♦

ELECTRICAL SPECIFICATIONS: Continued

PIN DESCRIPTION

PIN # PIN NAME DESCRIPTION

1VCCBias Supply Input. Connect to external 5V supply. Used to power internal circuits and

2GLHigh current driver output for the low side NFET switch. It is always low if GH is high or

3 GND Ground Pin. The control circuitry of the IC and lower power driver are referenced to this

4VFBFeedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error

5 COMP Output of the Error Amplifier. It is internally connected to the non-inverting input of the

6 UVIN UVLO input for VIN voltage. Connect a resistor divider between VIN and UVIN to set

7SSSoft Start. Connect an external capacitor between SS and GND to set the soft start rate

8 SWN Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node

9GHHigh current driver output for the high side NFET switch. It is always low if GL is high or

10 BST High side driver supply pin. Connect BST to the external boost diode and capacitor as

low side gate driver.

during a fault. Resistor pull down ensure low state at low voltage.

pin. Return separately from other ground traces to the (-) terminal of C

OUT

Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode.

PWM comparator. An optimal filter combination is chosen and connected to this pin and either ground or VFB to stabilize the voltage mode loop.

minimum operating voltage.

based on the 10µA source current. The SS pin is held low via a 1mA (min) current during all fault conditions.

at the junction between the two external power MOSFET transistors.

during a fault. Resistor pull down ensure low state at low voltage.

shown in the Typical Application Circuit on page 1. High side driver is connected between BST pin and SWN pin.

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10 µA

THERMAL

SHUTDOWN 145 ˚C ON 135 ˚C OFF

SHORT CIRCUIT

0.25 V DETECTION

+ -

VPOS

VFBINT

THERMAL AND SHORT CIRCUIT PROTECTION

CLK

COUNTER

200ms Delay

CLR

REF OK

FAULT

SOFTSTART INPUT

VFBINT

REFERENCE

CORE

SET DOMINANT

Gm ERROR AMPLIFIER

VPOS

FAULT

POS REF

0.8V

REF OK

FUNCTIONAL DIAGRAM

COMP

PWM LOOP

1.7 V

VCC

4.25 V ON

4.05 V OFF

2.50 VON

2.20 V OFF

UVIN

RAMP = 1.1V

0.4 V

HICCUP FAULT

REF OK

VCC UVLO

VIN UVLO

UVLO COMPARATORS

100% Protection Logic

CLR

PULSES

COUNT 20

CLOCK

CLK

FAULT

300 kHZ

CLOCK PULSE GENERATOR

RESET DOMINANT

CLK

1.7 V

ASYNC. STARTUP

COMPARATOR

POWER FAULT

QPWM

FAULT

GL HOLD OFF

SYNCHRONOUS

DRIVER

FAULT

BST

SWN

GND

THEORY OF OPERATION

General Overview

The SP6132H is a fixed frequency, voltage mode, synchronous PWM controller optimized for high efficiency. The part has been designed to be especially attractive for split plane applications utilizing 5V to power the controller and 3V to 12V for step down conversion.

The SP6132H contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is enabled during start up to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on. Second, a 100% duty cycle timeout ensures that the

The heart of the SP6132H is a wide bandwidth transconductance amplifier designed to accommodate Type II and Type III compensation schemes. A precision 0.8V reference present on

low side NFET is periodically enhanced during extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty ratios.

the positive terminal of the error amplifier permits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a 1.1V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to

The SP6132H also contains a number of valuable protection features. A programmable input (VIN) UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal V

UVLO ensures that the controller itself has enough voltage to properly operate. Other pro-

300kHz.

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THEORY OF OPERATION: Continued

tection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP6132H is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted.

Soft Start

“Soft Start” is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. In a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor.

IVIN = C

OUT

* DV

/ DTSoft-start

OUT

The SP6132H provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 10uA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, the excess source can be redefined as:

IVIN = C

Under Voltage Lock Out (UVLO)

OUT

* DV

*10µA / (CSS * 0.8V)

OUT

The SP6132H contains two separate UVLO comparators to monitor the bias (VCC) and conversion (VIN) voltages independently. The V

UVLO threshold is internally set to 4.25V, whereas the VIN UVLO threshold is programmable through the UVIN pin. When the UVIN pin is greater than 2.5V, the SP6132H is permitted to start up pending the removal of all other faults. Both the VCC and V

UVLO compara-

tors have been designed with hysteresis to prevent noise from resetting a fault.

Thermal and Short-Circuit Protection

Because the SP6132H is designed to drive large NFETs running at high current, there is a chance that either the controller or power converter will become too hot. Therefore, an internal thermal shutdown (145°C) has been included to prevent the IC from malfunctioning at extreme temperatures.

A short-circuit detection comparator has also been included in the SP6132H to protect against the accidental short or sever build up of current at the output of the power converter. This comparator constantly monitors the positive and negative terminals of the error amplifier, and if the VFB pin ever falls more than 250mV (typical) below the positive reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP6132H is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation.

Handling of Faults:

Upon the detection of power (UVLO), thermal, or short-circuit faults, the SP6132H is forced into an idle state where the SS and COMP pins are pulled low and the gate drivers are held off. In the event of UVLO fault, the SP6132H remains in this idle state until after the UVLO fault is removed. Upon the detection of thermal or shor-circuit faults, an internal 200ms (typical) timer is activated. In the event of a short-circuit fault, a re-start is attempted immediately after the 200ms timeout expires. Whereas, when a thermal fault is detected the 200ms delay continuously recycles and a re-start cannot be attempted until the thermal fault is removed and the timer expires.

Error Amplifier and Voltage Loop

As stated before, the heart of the SP6132H voltage error loop is a high performance, wide bandwidth transconductance amplifier. Because of the amplifier’s current limited (+/-150µA)

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transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. If a simple, single pole, single zero response is required, then compensation can be a simple as an RC to ground. If a more complex compensation is required, then the amplifier has enough bandwidth (45° at 4 MHz) and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase margins at cross over frequencies greater than 50kHz.

The common mode output of the error amplifier is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between 1.1V and 2.2V to ensure proper 0% to 100% duty cycle capability. The voltage loop also includes two other very important features. One is an asynchronous start up mode. Basically, the GL driver can not turn on unless the GH driver has attempted to turn on or the SS pin has exceeded 1.7V. This feature prevents the controller from “dragging down” the output voltage during startup or in fault modes. The second feature is a 100% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 21st cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor.

THEORY OF OPERATION: Continued

GATE DRIVER TEST CONDITIONS

90%

FALL TIME

NON-OVERLAP

90%

RISE TIME

TIME

10%

GH(GL)

10%

GL(GH)

V(BST)

GH Voltage

V(SWN)

V(VCC)

GL Voltage

V(VIN)

SWN Voltage

-0V

-V(Diode) V

V(VIN)+V(VCC)

BST Voltage

V(VCC)

Gate Drivers

The SP6132H contains a pair of powerful 2Ω SOURCE and 1.5Ω SINK drivers. These state of the art drivers are designed to drive external NFETs capable of handling up to 30A. Rise, fall, and non-overlap times have all been minized to achieve maximum efficiency. All drive pins GH, GL & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time.

Page 7

APPLICATIONS INFORMATION

Inductor Selection

There are many factors to consider in selecting the inductor including cost, efficiency, size and EMI. In a typical SP6132H circuit, the inductor is chosen primarily for value, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. The inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current.

The switching frequency and the inductor operating point determine the inductor value as follows:

L−=

(max)

OUTINOUT

IKFV

(max)(max)

OUTrSIN

)(

VVV

where: Fs = switching frequency Kr = ratio of the ac inductor ripple current to the

maximum output current

II +=

(max)

OUTPEAK

and provide low core loss at the high switching frequency. Low cost powdered iron cores have a gradual saturation characteristic but can introduce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. In general, ferrite or molypermalloy materials are better choice for all but the most cost sensitive applications.

The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetic vendor.

The peak to peak inductor ripple current is:

The copper loss in the inductor can be calculated using the following equation:

)( −

VVV

(max)

OUTINOUT

LFV

SIN

where I

L(RMS)

is the RMS inductor current that

RIP

)()(

WINDINGRMSLCuL

can be calculated as follows:

) 2

OUT(max)

Once the required inductor value is selected, the proper selection of core material is based on

L(RMS)

= I

OUT(max)

1 +

1 ( IPP

3 I

peak inductor current and efficiency requirements. The core must be large enough not to saturate at the peak inductor current

Page 8

APPLICATIONS INFORMATION: Continued

Output Capacitor Selection

The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP6132HHVCU adjusts the inductor current to the new value.

Therefore the capacitance must be large enough so that the output voltage is help up while the inductor current ramps up or down to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the current. Because of the fast transient response and inherent 100% and 0% duty cycle capability provided by the SP6132HHVCU when exposed to output load transient, the output capacitor is typically chosen for ESR, not for capacitance value.

The output capacitor’s ESR, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by:

RESR ≤ ∆V

PK-PK

OUT

where: ∆V

= Peak to Peak Output Voltage Ripple

OUT

= Peak to Peak Inductor Ripple Current

PK-PK

FS = Switching Frequency D = Duty Cycle C

= Output Capacitance Value

OUT

Input Capacitor Selection

The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle V

OUT/VIN

. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak

to peak inductor ripple current is low, it is given by:

CIN(rms)

= I

OUT(max)

√

D(1 - D)

The worse case occurs when the duty cycle D is 50% and gives an RMS current value equal to I

/2.

OUT

Select input capacitors with adequate ripple current rating to ensure reliable operation.

The power dissipated in the input capacitor is:

RIP =

)( CINESRrmsCINCIN

)(

This can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. The input voltage ripple primarily depends on the input capacitor ESR and capacitance. Ignoring the inductor ripple current, the input voltage ripple can be determined by:

The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows:

∆

OUT

where:

IPP (1 – D)

(

OUTFS

)

+ (IPPR

ESR

)

RIV

+=∆

)((max)

CINESRoutIN

)(

VVVI

−

OUTINOUTMAXOUT

VCF

ININS

)(

Page 9

APPLICATIONS INFORMATION: Continued

The capacitor type suitable for the output capacitors can also be used for the input capacitors.

However, exercise extra caution when tantalum capacitors are considered. Tantalum capacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are connected “live” to low impedance power sources.

MOSFET Selection

The losses associated with MOSFETs can be divided into conduction and switching losses. Conduction losses are related to the on resistance of MOSFETs, and increase with the load current. Switching losses occur on each on/off transition when the MOSFETs experience both high current and voltage. Since the bottom MOSFET switches current from/to a paralleled diode (either its own body diode or a Schottky diode), the voltage across the MOSFET is no more than 1V during switching transition. As a result, its switching losses are negligible. The switching losses are difficult to quantify due to all the variables affecting turn on/ off time. However, the following equation provides an approximation on the switching losses associated with the top MOSFET driven by SP6132H.

12=

FIVCP

SOUTINrssSH

(max)(max)(max)

where

= reverse transfer capacitance of the top

rss

MOSFET

Switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. The conduction losses associated with top and bottom MOSFETs are determined by:

OUTONDSCH

(max))((max)

OUTONDSCL

DIRP

(max))((max)

)1(

DIRP

−=

where

= conduction losses of the high side

CH(max)

MOSFET

= conduction losses of the low side

CL(max)

MOSFET

= drain to source on resistance.

DS(ON)

The total power losses of the top MOSFET are the sum of switching and conduction losses. For synchronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side MOSFETs. For input voltages of 3.3V and 5V, conduction losses often dominate switching losses. Therefore, lowering the R

DS(ON)

of the MOSFETs always improves efficiency even though it gives rise to higher switching losses due to increased C

rss

Top and bottom MOSFETs experience unequal conduction losses if their on time is unequal. For applications running at large or small duty cycle, it makes sense to use different top and bottom MOSFETs. Alternatively, parallel multiple MOSFETs to conduct large duty factor.

varies greatly with the gate driver voltage.

DS(ON)

The MOSFET vendors often specify R

DS(ON)

on multiple gate to source voltages (VGS), as well as provide typical curve of R 5V input, use the R

DS(ON)

specified at 4.5V VGS. At

versus VGS. For

DS(ON)

the time of this publication, vendors, such as Fairchild, Siliconix and International Rectifier, have started to specify R

at VGS less than 3V.

DS(ON)

This has provided necessary data for designs in which these MOSFETs are driven with 3.3V and made it possible to use SP6132H in 3.3V only applications.

Thermal calculation must be conducted to ensure the MOSFET can handle the maximum load current. The junction temperature of the MOSFET, determined as follows, must stay below the maximum rating.

(max)( max)

MOSFET

(max)

where

= maximum ambient temperature

A(max)

PMOSFET(max) = maximum power dissipation of the MOSFET

= junction to ambient thermal resistance.

of the device depends greatly on the board

Page 10

APPLICATIONS INFORMATION: Continued

layout, as well as device package. Significant thermal improvement can be achieved in the maximum power dissipation through the proper design of copper mounting pads on the circuit board. For example, in a SO-8 package, placing two 0.04 square inches copper pad directly under the package, without occupying additional board space, can increase the maximum power from approximately 1 to 1.2W. For DPAK package, enlarging the tap mounting pad to 1 square inches reduces the RΘJA from 96°C/W to 40°C/W.

Schottky Diode Selection

When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noises. Without this Schottky diode, the body diode of the bottom MOSFET conducts the current during the non-overlap time when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage and reverse recovery problem. The reverse recovery of the body diode causes additional switching noises when the diode turns off. The Schottky diode alleviates these noises and additionally improves efficiency thanks to its low forward voltage. The reverse voltage across the

diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current.

The power dissipation of the Schottky diode is determined by

= 2VFI

DIODE

OUTTNOLFS

where

= non-overlap time between GH and GL.

NOL

VF = forward voltage of the Schottky diode.

Loop Compensation Design

The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter output stage, and feedback resistor divider. In order to crossover at the selected frequency FCO, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency.

REF

(Volts)

Type III Voltage Loop

Compensation

(s) Gain Block

AMP

+ _

Notes: R

Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> R

(SRz2Cz2+1)(SR1Cz3+1) (SR

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

= Output Capacitor Equivalent Series Resistance.

ESR

= Output Inductor DC Resistance.

= SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

RAMP_PP

& R

ESR

FBK

(Volts)

PWM Stage

Gain

PWM

Block

RAMP_PP

Voltage Feedback

Gain Block

FBK

)

Output Stage G

(s) Gain

OUT

Block

+ 1)

ESRCOUT

+S(R

[S^2LC

OUT

REF

OUT

ESR+RDC

) C

+1]

OUT

(Volts)

SP6132H Voltage Mode Control Loop with Loop Dynamic

Page 11

APPLICATIONS INFORMATION: Continued

The goal of loop compensation is to manipulate loop frequency response such that its gain crosses

over 0db at a slope of -20db/dec. The first step of compensation design is to pick the loop crossover frequency. High crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by:

Z(ESR)

2π C

OUT RESR

The next step is to calculated the complex conjugate poles contributed by the LC output filter,

P(LC)

2π L C

OUT

When the output capacitors are of a Ceramic Type, the SP6132HHVCU Evaluation Board requires a Type III compensation circuit to give a phase boost of 180° in order to counteract the effects of an under damped resonance of the output filter at the double pole frequency.

Gain

(dB)

Error Amplify Gain

Condition: C22 >> CP1, R1 >> RZ3

20 Log (RZ2/R1)

1/6.28 (R1) (CZ3)

1/6.28 (R1) (CZ2)

1/6.28(R22) (CZ2)

Bode Plot of Type III Error Amplify Compensation.

Bandwidth Product

1/6.28 (RZ2) (CP1)

1/6.28 (RZ3) (CZ3)

Frequency

(Hz)

INDUCTORS - SURFACE MOUNT

Inductor Specification

Inductance Manufacturer/Part No. Series R I

(uH) mΩ (a) LxW(mm) Ht.(mm) Website

2.7 Easy Magnet SC5018-2R7M 4.30 12.0 12.6x12.6 4.5 Shielded Ferrite Core inter-technical.com

2.7 TDK RLF 12560T-2R7N110 4.50 12.2 12.5x12.8 6.0 Shielded Ferrite Core tdk.com

3.3 Coilcraft DO5010P-332HC 8.60 17.0 14.7x15.2 8.0 Unshielded Ferrite Core coilcraft.com

1.2 Easy Magnet SC5018-1R2M 1.96 20.0 12.6x12.6 4.5 Shielded Ferrite Core inter-technical.com

1.2 Inter-Technical SC4015-1R2M 4.37 17.0 10.0x10.0 3.8 Shielded Ferrite Core inter-technical.com

1.5 Coilcraft DO5010P-152HC 4.00 25.0 14.7x15.2 8.0 Unshielded Ferrite Core coilcraft.com

1.9 TDK RLF 12560T-1R9N120 3.60 13.2 12.5x12.8 6.0 Shielded Ferrite Core tdk.com

CAPACITORS -SURFACE MOUNT

Capacitance Manufacturer/Part No. ESR Ripple Current Size Voltage Capacitor Manufaturer

(uF) Ω (max) (A)@45°C LxW(mm) Ht.(mm) (V) Type Website

22 TDK C3225X5R1C226M 0.002 4.00 3.2x2.5 2.0 16.0 X5R Ceramic tdk.com 47 TDK C3225X5ROJ476M 0.002 4.00 3.2x2.5 2.5 6.3 X5R Ceramic tdk.com

MOSFET Manufacturer/Part No. RDS (on) ID Current Qg Qg Voltage Foot Print Manufaturer

Ω (max) (A) nC(Typ) nC(Max) (V) Website

N-Channel Fairchild Semi FDS6676S 0.006 14.50 43 60.0 30.0 SO-8 fairchildsemi.com

N-Channel Fairchild Semi FD7088N3 0.005 21.10 37 48.0 30.0 SO-8 fairchildsemi.com N-Channel Vishay Si4336DY 0.004 25.0 32 50.0 30.0 SO-8 vishay.com

Note: Components highlighted in Bold are those used on the SP6132H Evaluation Board.

SAT

MOSFET - Surface Mount

Size Inductor Type Manufaturer

Table 1. Input and Output Stage Components Selection Charts.

Page 12

APPLICATIONS INFORMATION: Continued

SP6132HCUEB Component Placement

SP6132HCUEB PC Layout Top Side

SP6132HCUEB PC Layout Bottom Side

Page 13

PACKAGE: 10 PIN MSOP

D e1

Ø1

E/2

Seating Plane

Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)

10 Pin MSOP JEDEC MO-187 (BA) Variation

SYMBOL

MIN NOM MAX

A--1.1 A1 0 - 0.15 A2 0.75 0.85 0.95

b0.17-0.27

c0.08-0.23

3.00 BSC

4.90 BSC

3.00 BSC

0.50 BSC

2.00 BSC

L0.40.60.8

L1 L2

0.95 REF

0.25 BSC N-10R0.07- -

R1 0.07 - -

ø0º-8º

ø1 0º - 15º

Note: Dimensions in (mm)

Ø1

WITH PLATING

Gauge Plane

BASE METAL

Section B-B

Page 14

ORDERING INFORMATION

Part Number Top Mark Temperature Package

SP6132HCU......................... SP6132HCU..................-0°C to +70°C ...................... 10 Pin MSOP

SP6132HCU/TR ................... SP6132HCU..................-0°C to +70°C ...................... 10 Pin MSOP

SP6132HEU ........................ SP6132HEU..................-40°C to +85°C ..................... 10 Pin MSOP

SP6132HEU/TR .................. SP6132HEU..................-40°C to +85°C .................... 10 Pin MSOP

Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6132HEU/TR = standard; SP6132HEU-L/TR = lead free

/TR = Tape and Reel Pack quantity is 2500 for MSOP.

CLICK HERE TO ORDER SAMPLES

Corporation

ANALOG EXCELLENCE

Sipex Corporation

Headquarters and Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP6132H Datasheet (Sipex)

Specifications and Main Features

Frequently Asked Questions

User Manual