Datasheet SP5848, SP5848KG, SP5848QP1S, SP5848QP1T Datasheet (MITEL)

1

Preliminary Information SP5848

SP5848

2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL

Preliminary Information

Features

● Dual independent PLL frequency synthesisers in a

single package, optimised for double conversion
cable tuners, offering improved application

● 2.2GHz up-synthesiser optimised for low phase

noise up to comparison frequencies of 4MHz

Ordering Information

SP5848/KG/QP1S

SP5848/KG/QP1T

Applications

● TV, VCR, and cable tuning systems

The SP5848 is a dual PLL frequency synthesizer
controlled by a 3-wire bus optimised for application in
double conversion tuners.

Each synthesiser loop within the SP5848 is
independently addressable and contains an RF
programmable divider, phase/frequency detector and
charge pump/loop amplifier section; a common
reference frequency oscillator and divider chain is
provided, whose ratios for each loop are independently
programmable.

Both synthesisers are optimised for low phase noise
performance and in addition synthesiser 2 is capable of
operation with a low comparison frequency.

● 1.3GHz down-synthesiser optimised for low phase

noise AND small step size

● Common reference oscillator and divider with

independently selectable ratios for each
synthesiser

● 10:1 programmable charge pump current ratio in up

synthesiser

● 3-Wire bus programmable, each synthesiser

indepently addressable

● Low power consumption, typ 100mW at 5V

● ESD protection, (Normal ESD handling procedures

should be observed)

DS5076 Issue 1.6 October 1999

Description

RF1 INPUT

16/17

4 BIT

COUNT

11 BIT

COUNT

15 BIT LATCH

2 BIT

LATCH

PORT P0

PUMP 1

DRIVE 1

16 BIT LATCH

DATA

CLOCK

ENABLE

2

DATA

INTERFACE

RF 2 INPUT

16/17

4 BIT

COUNT

12 BIT

COUNT

1 BIT

LATCH

2 BIT

LATCH

5 BIT

LATCH

9

DIVIDE

PORT P1

PUMP 2

DRIVE 2

Figure 1 Block Diagram

2

SP5848 Preliminary Information

Figure 2 Pin Connections

QP20

PORT P1

CHARGE PUMP 2

DRIVE 2

Vee 2

RF2 INPUT

RF2 INPUT

Vcc2

CRYSTAL

CRYSTAL CAP

Vee

PORT P0

CHARGE PUMP 1

DRIVE 1

Vee 1

RF1 INPUT

RF1 INPUT

Vcc1

ENABLE

DATA

CLOCK

Electrical Characteristics

T

amb

= -40oC to +80oC, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or design.

They apply within the specified ambient temperature and supply voltage unless otherwise stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Supply voltage 7, 14 4.5 5.5 V
Supply current 18 22 mA

Synthesiser 1 (UP)

RF1 input voltage 15,16 40 300 mV

rms

80 -2200MHz
RF1 input impedance 15,16 See Figure 4
RF1 division ratio 240 32767
Reference division 1 See Table 1
ratio
Comparison frequency 1 4 MHz
Equivalent phase noise -148 dBc/Hz SSB, within loop bandwidth, all
at phase detector 1 comparison frequencies
Charge pump 1 output 19 See Table 3
current Vpin 19=2V
Charge pump 1 output 19 ±3 ±10 nA Vpin19 = 2V
leakage
Charge pump 1 drive 18 0.5 mA Vpin 18 = 0.7V
output current

3

Preliminary Information SP5848

Electrical Characteristics (continued)

T

amb

= -40oC to +80oC, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or design.

They apply within the specified ambient temperature and supply voltage unless otherwise stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Synthesiser 2 (DOWN)

RF2 input voltage 5,6 30 300 mV

rms

80 -1300MHz
RF2 input impedance 5,6 See Figure 5
RF2 division ratio 240 65535
Reference division 2 See Table 2
ratio
Comparison frequency 2 16.25 4000 KHz Phase noise degrades above

250KHz
Equivalent phase noise -144 dBc/Hz SSB, within loop bandwidth, all
at phase detector 2 comparison frequencie up to

250KHz
Charge pump 2 output 2 See Table 4
current Vpin 2=2V
Charge pump 2 output 2 ±3 ±10 nA Vpin2 = 2V
leakage
Charge pump 2 drive 3 0.5 mA Vpin 3 = 0.7V
output curent
Data, clock and enable 12,11,13
Input high voltage 3 Vcc V
Input low voltage 0 0.7 V
Input current -10 10 µA All input conditions
hysterysis 0.8 Vpp
Clock rate 11 500 KHz

Bus timing ­ Data set up 300 ns
Data hold 600 ns
Enable setup 300 ns
Enable hold 600 ns
Clock to enable 300 ns

Reference Oscillator

Crystal frequency 8, 9 2 16 MHz See Figure 6 for application
External reference input 8 2 20 MHz Sinewave coupled through
frequency 10nF blocking capacitor
External reference drive 8 0.2 0.5 Vpp Sinewave coupled through 10nF

blocking capacitor
Outputs ports P0 - P1 1, 20 See note 1
sink current 2 mA Vport = 0.7V
leakage current 10 µA Vport = Vcc

Note 1 Output ports high impedance on power up, with data, clock and enable at logic 0

4

SP5848 Preliminary Information

Absolute maximum Ratings

All voltages referred to Vee at 0V

Characteristic Value Conditions

Min Max Units

Supply voltages -0.3 7 V
RF1 input voltage 2.5 Vp-p Differential
RF2 input voltage 2.5 Vp-p Differential
All I/O ports DC offset -0.3 Vcc+0.3 V
Storage temperature -55 +125 °C
Junction temperature 150 °C
Package thermal resistance
chip to ambient 100 °C/W
chip to case 30 °C/W
Power consumption with all 121 mW All ports off
Vcc =5.5V
ESD protection 2 kV Mil std 883 latest revision methood 3015

class 1

Functional Description

The SP5848 contains two PLL frequency synthesiser
loops, each independently programmable from a 3-wire
bus. The device is optimised for application in double
conversion tuners where synthesiser 1 would form part
of the upconverter and synthesiser 2 part of the down
converter. Both loops are optimised for application in low
phase noise loops and furtherly synthesiser 2 offers low
comparison frequencies. A block diagram is contained in
Figure 1.

The device is programmed via a 3-wire bus where data
is fed on serial data and clock lines and is gated by an
enable line. Figure 3 indicates the format of the data.
The sequence and timing of data load is described below
in ‘programming mode’ description. Each synthesiser is
independently addressable and is defined by the LSB bit
within the data transmission.

A common reference frequency source and reference
divider is used to derive the comparison frequency for
both PLL loops. The reference division ratio is
programmable via the data bus as defined in Tables1
and 2.

The charge pump current for each loop is also
programmable via the data bus as defined in Tables 3
and 4

Two switching ports are provided to control switching
functions within the tuner. These ports also access test
signals within the PLL as defined in Figure 7. Ports
power up in high impedance state.

Programming Mode

The SP5848 is designed to be programmed from a
standard 3-wire bus consisting of clock, data and enable,
where the serial clock and data lines can be shared with
other devices and the enable line is a unique line for
individual device selection. To simplify programming
each synthesiser is independently addressed, with the
required loop being selected by the LSB bit , which
functions as the address, therefore to fully program the
device two complete data transmissions must be sent.

The data format for each transmission is contained in
Figure 3.

Test modes as described in Figure 7, can be invoked by
setting bit T0 in synthesiser 2 data word to a ‘1’ and
sending control data for bits T1-T2. In normal operation
where T0 is set to a ‘0’ bits T1 and T2 do not need to be
transmitted

5

Preliminary Information SP5848

2

22

2

21

2

20

2

19

2

18

2

17

2

16

2

15

2

1

2

0

CLOCK

ENABLE

DATA

P1 P0 CU1 CU0RU2 RU1 RU0 MSB LSB ‘0’

Frequency data (15 bits)

Synthesiser 1 control data

CLOCK

ENABLE

DATA

2

24

2

23

2

22

2

20

2

19

2

18

2

17

2

16

2

1

2

0

T2 T1 T0 CD RD2 RD1 RD0 MSB LSB ‘1’

Frequency data (16 bits)

Synthesiser 2 control data

CU0 - CU1 : Synthesiser 1 charge pump
RU0 - RU2 : Synthesiser 1 reference division ration

CD : Synthesiser 2 charge pump

RD0 - RD2 : Synthesiser 2 reference division ratio

T0 - T2 : Test modes

P0 - P1 : Switching ports P0 - P1

Figure 3 Control data

6

SP5848 Preliminary Information

Figure 4 Synthesiser 1 RF input impedance

j2

j1

j0.5

j0.2

0

2j0.2

2j0.5

2j1

2j2

1

0.5

0.2

j5

2j5

2

5

80MHz

1GHz

2·2GHz

1·7GHz

Figure 5 Synthesiser 2 RF input impedance

j2

j1

j0.5

j0.2

0

2j0.2

2j0.5

2j1

2j2

1

0.5

0.2

j5

2j5

2

5

80MHz

1·3GHz

0·5GHz

0·9GHz

7

Preliminary Information SP5848

RU2 RU1 RU0 Ratio

000 4

001 8

01016

01132

10064

1 0 1 128

1 1 0 256

1 1 1 512

Table 2 Synthesiser 2 reference division ratio

CU1 CU0 Current (typical in mA)

0 0 0.12

0 1 0.26

1 0 0.55

1 1 1.2

Table 3 Synthesiser 1 charge pump current

RU2 RU1 RU0 Ratio

000 2

001 4

010 8

01116

10032

10164

1 1 0 128

1 1 1 256

Table 1 Synthesiser 1 reference division ratio

8

SP5848 Preliminary Information

T2 T1 T0 Functional Description

X X 0 Normal operation

0 0 1 Both charge pumps in sink mode

0 1 1 Both charge pumps in source mode

1 0 1 Port P1 = Fcomp1, P0 = Fcomp2 and charge pumps disabled

1 1 1 Port P1 = (Fpd1)/2, P0 = (Fpd2)/2

X = dont care

Figure 7 Test modes

CD Current (typical in mA)

00.05

1 0.2

Table 4 Synthesiser 2 charge pump current

Figure 6 Crystal oscillator application

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Mitel Semiconductor is an ISO 9001 Registered Company
Copyright 1999 MITEL Corporation
All Rights Reserved
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