Datasheet SI2302DDS Specification

PRODUCT SUMMARY

Ordering Information: Si2302DDS-T1-GE3 (Lead (Pb)-free and Halogen-free)

* Marking Code

Si2302DDS (O2)*

G

S

D

Top View

2

3

TO-236

(SOT-23)

1

VDS (V) R

20

0.057 at V

0.075 at V

(Ω) Max. ID (A) Qg (Typ.)

DS(on)

= 4.5 V

GS

= 2.5 V

GS

N-Channel 20 V (D-S) MOSFET

FEATURES

• Halogen-free According to IEC 61249-2-21

2.9

2.6

3.5

Definition

• TrenchFET

• 100 % R

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Load Switching for Portable Devices

• DC/DC Converter

®

Power MOSFET

Tested

g

Si2302DDS

Vishay Siliconix

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol 5 s Steady State Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

J

Pulsed Drain Current (t = 300 µs)

Continuous Source Current (Diode Conduction)

Power Dissipation

a

a

b

a

Operating Junction and Storage Temperature Range

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

Maximum Junction-to-Foot Steady State

Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Pulse width limited by maximum junction temperature.

Document Number: 63653
S11-2528-Rev. A, 26-Dec-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

a

This document is subject to change without notice.

V

DS

V

GS

TA = 25 °C

= 70 °C

T

A

TA = 25 °C

= 70 °C

T

A

t ≤ 5 s

Steady State 140 175

I

D

I

DM

I

S

P

D

T

, T

J

stg

R

thJA

R

thJF

2.9 2.6

2.3 2.1

0.72 0.6

0.86 0.71

0.55 0.46

120 145

62 78

20

± 8

10

- 55 to 150 °C

V

A

W

°C/W

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1

Si2302DDS

0

2

4

6

8

10

0.0 0.4 0.8 1.2 1.6 2.0

VGS- Gate-to-Source Voltage (V)

- Drain Current (A)I

D

TC= 25 °C

TC= 125 °C

TC= - 55 °C

Vishay Siliconix

SPECIFICATIONS (TA = 25 °C, unless otherwise noted)

Limits

Parameter Symbol Test Conditions

Min. Typ. Max.

Static

Drain-Source Breakdown Voltage

Gate-Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-Resistance

Forward Transconductance

a

a

a

Diode Forward Voltage

Dynamic

b

Total Gate Charge

Gate-Drain Charge

Gate Resistance

V

DS

V

GS(th)

I

GSS

I

DSS

I

V

D(on)

R

DS(on)

g

fs

V

SD

Q

g

Q

gs

Q

gd

R

g

VGS = 0 V, ID = 250 µA

V

= VGS, ID = 250 µA

DS

VDS = 0 V, VGS = ± 8 V

V

= 20 V, V

DS

V

= 20 V, V

DS

GS

≥ 10 V, V

DS

V

= 4.5 V, ID = 3.6 A

GS

V

= 2.5 V, ID = 3.1 A

GS

VDS = 5 V, ID = 3.6 A

IS = 0.95 A, V

V

= 10 V, V

DS

GS

f = 1 MHz 2 4 8 Ω

= 0 V

GS

= 0 V, TJ = 70 °C

= 4.5 V

GS

= 0 V

GS

= 4.5 V, ID = 3.6 A

20

0.40 0.85

± 100 nA

1

75

6A

0.045 0.057

0.056 0.075

13 S

0.7 1.2 V

3.5 5.5

0.6

0.45

Switching

Tur n -O n De l a y T i m e

Rise Time

Turn-Off Delay Time

Fall Time

Source-Drain Reverse Recovery Time

Body Diode Reverse Recovery Charge

t

d(on)

t

d(off)

Q

t

r

t

f

t

rr

rr

V

= 10 V, RL = 2.78 Ω

DD

≅ 3.6 A, V

I

D

= 4.5 V, Rg = 1 Ω

GEN

IF = 3.6 A, dI/dt = 100 A/µs

815

715

30 45

715

8.5 15

24nC

Notes:
a. Pulse test: Pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

Unit

V

µA

Ω

nCGate-Source Charge

ns

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10

VGS=5V thru 2 V

8

6

4

- Drain Current (A)I

D

2

0

0.0 0.5 1.0 1.5 2.0

VDS- Drain-to-Source Voltage (V)

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2

Output Characteristics

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

VGS=1.5V

VGS=1V

Transfer Characteristics

Document Number: 63653

S11-2528-Rev. A, 26-Dec-11

This document is subject to change without notice.

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0

80

160

240

320

400

0 5 10 15 20

C

iss

VDS- Drain-to-Source Voltage (V)

C - Capacitance (pF)

C

oss

C

rss

0.6

0.8

1.0

1.2

1.4

1.6

- 50 - 25 0 25 50 75 100 125 150

TJ-Junction Temperature (°C)

(Normalized)

- On-Resistance

R

DS(on)

VGS=2.5V,ID=3.1A

VGS=4.5V,ID=3.6A

0.03

0.04

0.05

0.06

0.07

02468 10

- On-Resistance (Ω)R

DS(on)

ID- Drain Current (A)

VGS=2.5V

VGS=4.5V

2.0

1.6

1.2

0.8

- Drain Current (A)I

D

0.4

TC= 125 °C

0.0

0.0 0.3 0.6 0.9 1.2 1.5

TC= 25 °C

TC= - 55 °C

VGS- Gate-to-Source Voltage (V)

Si2302DDS

Vishay Siliconix

Transfer Characteristics

Capacitance

On-Resistance vs. Drain Current

5

ID=3.6A

4

3

2

- Gate-to-Source Voltage (V)

GS

1

V

0

01234

Qg- Total Gate Charge (nC)

VDS=10V

VDS= 5 V

VDS= 15 V

Gate Charge

100

10

TJ= 150 °C

1

Document Number: 63653
S11-2528-Rev. A, 26-Dec-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

On-Resistance vs. Junction Temperature

0.1

- Source Current (A)I

S

0.01

0.001

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Source-Drain Diode Forward Voltage

This document is subject to change without notice.

TJ= 25 °C

TJ= - 55 °C

VSD-Source-to-Drain Voltage (V)

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3

Si2302DDS

0.04

0.06

0.08

0.10

0.12

012345

- On-Resistance (Ω)R

DS(on)

VGS- Gate-to-Source Voltage (V)

TJ= 25 °C

TJ= 125 °C

0

2

4

6

8

10

0.01 0.1 1 10 100 1000
Time (s)

Power (W)

TA= 25 °C

- 0.3

- 0.2

- 0.1

0.0

0.1

0.2

- 50 - 25 0 25 50 75 100 125 150

ID= 250 µA

Variance (V)V

GS(th)

TJ- Temperature (°C)

ID=1mA

VDS- Drain-to-Source Voltage (V)

* V

GS

> minimum VGSat which R

DS(on)

is specified

- Drain Current (A)I

D

10

0.1

0.1 1 10

1

TA= 25 °C

Single Pulse

1ms

10 ms

100 ms

0.01

100 s, DC

BVDSS Limited

100

100 µs

Limited byR

DS(on)*

1s
10 s

10

-3

10

-2

1

10

100010

-1

10

-4

100

0.2

0.1

0.05

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

Single Pulse

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

= 70 °C/W

3. T

JM-TA=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

Duty Cycle = 0.5

0.02

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

On-Resistance vs. Gate-to-Source Voltage

Single Pulse Power

Threshold Voltage

Safe Operating Area, Junction-to-Ambient

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63653

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Normalized Thermal Transient Impedance, Junction-to-Ambient

.

This document is subject to change without notice.

Document Number: 63653

S11-2528-Rev. A, 26-Dec-11

SOT-23 (TO-236): 3-LEAD

b

3

1

Package Information

Vishay Siliconix

E

E

1

2

S

A

A

2

A

1

Dim

A 0.89 1.12 0.035 0.044

A

1

A

2

b 0.35 0.50 0.014 0.020

c 0.085 0.18 0.003 0.007

D 2.80 3.04 0.110 0.120

E 2.10 2.64 0.083 0.104

E

1

e 0.95 BSC 0.0374 Ref

e

1

L 0.40 0.60 0.016 0.024

L

1

S 0.50 Ref 0.020 Ref

q 3°8°3°8°

ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479

e

e

1

D

0.10 mm

Seating Plane

C

0.004"

C

C

q

L

L

1

MILLIMETERS INCHES

Min Max Min Max

0.01 0.10 0.0004 0.004

0.88 1.02 0.0346 0.040

1.20 1.40 0.047 0.055

1.90 BSC 0.0748 Ref

0.64 Ref 0.025 Ref

0.25 mm

Gauge Plane

Seating Plane

Document Number: 71196
09-Jul-01

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1

Mounting LITTLE FOOTR SOT-23 Power MOSFETs

Wharton McDaniel

AN807

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.

The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.

ambient air. This pattern uses all the available area underneath the
body for this purpose.

0.114

2.9

0.081

2.05

0.150

3.8

0.059

1.5

0.0394

FIGURE 1. Footprint With Copper Spreading

1.0

0.037

0.95

Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the

Document Number: 70739
26-Nov-03

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.

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RECOMMENDED MINIMUM PADS FOR SOT-23

Application Note 826

Vishay Siliconix

0.106
(2.692)

0.037

(0.950)

0.053

(1.341)

0.097

(2.459)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.022

(0.559)

0.049

0.029

(1.245)

(0.724)

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Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25

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Revision: 08-Feb-17

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Document Number: 91000