Page 1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
CMOS/EEPROM/EPROM Technologies on a
Single Device
– Mask-ROM Devices for High-Volume
Production
– One-Time-Programmable (OTP) EPROM
Devices for Low-Volume Production
– Reprogrammable EPROM Devices for
Prototyping Purposes
D
Internal System Memory Configurations
– On-Chip Program Memory Versions
– ROM: 4K Bytes
– EPROM: 8K Bytes
– Data EEPROM: 256 Bytes
– Static RAM: 128 Bytes Usable as
Registers
D
Flexible Operating Features
– Low-Power Modes: STANDBY and HALT
– Commercial, Industrial, and Automotive
T emperature Ranges
– Clock Options:
– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)
– Divide-by-1 (2 MHz – 5 MHz SYSCLK)
PLL
– Supply Voltage (V
CC
): 5 V ± 10%
D
15-Channel 8-Bit A/D Converter 3
D
16-Bit General-Purpose Timer
– Software Configurable as
a 16-Bit Event Counter, or
a 16-Bit Pulse Accumulator, or
a 16-Bit Input Capture Function, or
T wo Compare Registers, or
a Self-Contained
Pulse-Width-Modulation (PWM) Function
– 8-Bit Prescaler, Providing a 24-Bit
Real-Time Timer
D
On-Chip 24-Bit Watchdog Timer
– EPROM/OTP Devices: Standard
Watchdog
– Mask ROM Devices: Hard Watchdog,
Simple Counter, or Standard Watchdog
D
TMS370 Series Compatibility
– Instructions Upwardly Compatible With
All TMS370 Devices
– Register-to-Register Architecture
– 128 or 256 General-Purpose Registers
– 14 Powerful Addressing Modes
D
Flexible Interrupt Handling
D
CMOS/Package/TTL-Compatible I/O Pins
– 40- and 44-Pin Plastic and Ceramic
Shrink Dual-In-Line and Leaded Chip
Carrier Packages /16 Bidirectional;
9 Input Pins
– All Peripheral Function Pins Are
Software Configurable for Digital I/O
D
Workstation/PC-Based Software
Development System
– C Compiler and C Source Debugger
– Real-Time In-Circuit Emulation
– Extensive Breakpoint/Trace Capability
– Software Performance Analysis
– Multi-Window User Interface
– Microcontroller Programmer
AN11
AN12
AN13
AN14
AN5
AN6
AN7
AN8
AN9
NC
AN10
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A3
A4
A5
A6
A7
RESET
INT1
V
CC
V
CC3
V
SS3
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
A2
A1
A0
T1EVT
T1PWM
MC
T1IC/CR
XTAL2/CLKIN
XTAL1
V
SS
D7
D5
D4
D6
D3
AN14
AN13
AN12
AN11
AN10
JC AND NJ PACKAGES
(TOP VIEW)
MC
T1IC/CR
XTAL2/CLKIN
NC
XTAL1
V
SS
D7
D5
D4
D6
D3
39
38
37
36
35
34
33
32
31
30
29
18 19
7
8
9
10
11
12
13
14
15
16
17
RESET
INT1
V
CC
V
CC3
V
SS3
AN0
AN1
AN2
AN3
AN4
NC
20 2122 23
FN AND FZ PACKAGES
(TOP VIEW)
A1A0T1EVT
T1PWM
54 321644
A7A6A5A4A3NCA2
42 4043
24 25 26 27 28
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
Page 2
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Pin Descriptions
PIN
NAME
SDIP
(40)
LCC
(44)
I/O
†
DESCRIPTION
‡
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
A0
A1
A2
A3
A4
A5
A6
A7
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
38
39
40
01
02
03
04
05
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
42
43
44
02
03
04
05
06
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
I/O
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
Port A is a general-purpose bidirectional I/O port.
ÁÁÁ
Á
ÁÁÁ
Á
D3/SYSCLK
D4
D5
D6
D7
Á
Á
Á
Á
26
28
29
27
30
Á
Á
Á
Á
29
31
32
30
33
Á
Á
Á
Á
I/O
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
AN0/E0
AN1/E1
AN2/E2
AN3/E3
AN4/E4
AN5/E5
AN6/E6
AN7/E7
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
11
12
13
14
15
16
17
18
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
12
13
14
15
16
18
19
20
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
I
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ADC3 analog input (AN0–AN7) or positive reference pins (AN6–AN7)
Port E can be individually programmed as general-purpose input pins if not used as ADC3 analog input. Only AN6 and AN7 can be software-configured as positive reference input.
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
AN8
AN9
AN10
AN11
AN12
AN13
AN14
Á
Á
Á
Á
Á
Á
Á
Á
19
20
21
22
23
24
25
Á
Á
Á
Á
Á
Á
Á
Á
21
22
24
25
26
27
28
Á
Á
Á
Á
Á
Á
Á
Á
I
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ББББББББББББББББББББББ
Á
ADC3 analog input pins
INT1
7
8
I
External (nonmaskable or maskable) interrupt/general-purpose input pin
ÁÁÁ
Á
T1IC/CR
T1PWM
T1EVT
Á
Á
34
36
37
Á
Á
38
40
41
Á
Á
I/O
ББББББББББББББББББББББ
Á
Timer1 input capture/counter reset input pin/general-purpose bidirectional pin
Timer1 PWM output pin/general-purpose bidirectional pin
Timer1 external event input pin/general-purpose bidirectional pin
ÁÁÁ
Á
RESET
Á
Á
6
Á
Á
7
Á
Á
I/O
ББББББББББББББББББББББ
Á
System-reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain
output, RESET
indicates an internal failure was detected by the watchdog or oscillator fault circuit.
ÁÁÁ
Á
MC
Á
Á
35
Á
Á
39
Á
Á
I
ББББББББББББББББББББББ
Á
Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM
VPP.
XTAL2/CLKIN
XTAL1
33
32
37
35IO
Internal oscillator crystal input/external clock source input
Internal oscillator output for crystal
V
CC
8
9
Positive supply voltage for digital logic
V
SS
31
34
Ground reference for digital logic
V
CC3
9
10
Positive supply voltage for ADC3
V
SS3
10
11
Ground reference for ADC3
NC
—
1, 17,
23, 36
These pins have no connection to the internal die.
†
I = input, O = output
‡
Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.
Page 3
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
Program Memory
ROM: 4K Bytes
EPROM: 8K Bytes
V
SS
V
CC
RESETMCXTAL2/
CLKIN
XTAL1INT1
E0–E7
or
AN0–AN7
Data EEPROM
256 Bytes
RAM
128 Bytes
CPU
Watchdog
Timer 1
A-to-D Converter 3
System Control
Clock Options:
Divide-by-4 or
Divide-by-1(PLL)
T1PWM
T1EVT
T1IC/CR
V
SS3
V
CC3
Port A
Interrupts
8
Port D
5
AN8–AN14
description
The TMS370C090A, TMS370C792, and SE370C792 devices are members of the TMS370 family of single-chip
8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx9x refers to these devices. The TMS370
family provides cost-effective real-time system control through integration of advanced peripheral function
modules and various on-chip memory configurations.
The TMS370Cx9x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM
technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS
technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx9x devices attractive in system designs for automotive electronics, industrial motor control,
computer peripheral control, telecommunications, and consumer application.
All TMS370Cx9x devices contain the following on-chip peripheral modules:
D
Fifteen-channel, 8-bit analog-to-digital converter 3 (ADC3)
D
One 24-bit general-purpose watchdog timer
D
One 16-bit general-purpose timer with an 8-bit prescaler
Page 4
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
Table 1 provides a memory configuration overview of the TMS370Cx9x devices.
Table 1. Memory Configurations
DEVICE
PROGRAM
MEMORY
(BYTES)
DATA MEMORY
(BYTES)
PACKAGES
44 PIN PLCC/CLCC, OR
ROM EPROM RAM EEPROM
40 PIN PSDIP/CSDIP
TMS370C090A
4K
—
128
256
FN – PLCC / NJ‡ –PSDIP
TMS370C792
—
8K
128
256
FN – PLCC / NJ‡ –PSDIP
SE370C792
†
—
8K
128
256
FZ – CLCC / JC –CSDIP
†
System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
‡
The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The mechanical drawing of the NJ is identical to the N2
package and did not need to be requalified.
The suffix letter A appended to the device names shown in the device column of Table 1 indicates the
configuration of the device. ROM and EPROM devices have a different configuration as indicated in Table 2.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
Table 2. Suffix Letter Configuration
DEVICE
§
WATCHDOG TIMER CLOCK LOW-POWER MODE
EPROM without A
Standard
Divide-by-4 (Standard oscillator)
Enabled
Standard
ROM A
Hard
Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled
Simple
§
Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.
The 4K bytes of mask-programmable ROM in the associated TMS370Cx9x device are replaced with 8K bytes
of EPROM in the TMS370C792 while all other available memory and on-chip peripherals are identical. A
one-time-programmable device (OTP) (TMS370C792) and a reprogrammable device (SE370C792) are
available.
The TMS370C792 OTP device is available in a plastic package. This microcontroller is effective for use as an
immediate production update for the TMS370Cx9x ROM device or for low-volume production runs when the
mask charge or cycle time for the low-cost mask-ROM device is not practical.
The SE370C792 has a windowed ceramic package that allows reprogramming of the program EPROM memory
during the development/prototyping design phase. The SE370C792 device allows quick updates to
breadboards and prototype systems while iterating initial designs.
The TMS370Cx9x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In
the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode,
all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both
low-power modes.
The TMS370Cx9x features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370Cx9x family is fully
instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller
family.
Page 5
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
The TMS370Cx9x family provides the system designer with very economical, efficient solutions to real-time
control applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently
developing the software and hardware required to design the TMS370Cx9x into an ever-increasing number of
complex applications. The application source code can be written in assembly and C-language, and the output
code can be generated by the linker. The TMS370 family CDT development tool can communicate through a
standard RS-232-C interface with a personal computer. This allows the use of personal-computer editors and
software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use through
extensive use of menus and screen windowing so that a system designer with minimal training can begin
developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools
ensure efficient software and hardware implementation as well as reduced time-to-market cycle.
The TMS370Cx9x family together with the TMS370 family CDT370 PACT, software tools, the SE370C792
reprogrammable device, comprehensive product documentation, and customer support provide a complete
solution to the needs of the system designer.
CPU
The CPU used on TMS370Cx9x devices is the high-performance 8-bit TMS370 CPU module. The ’x9x
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’x9x instruction set is summarized in Table 21. Figure 1 illustrates the CPU registers
and memory blocks.
CDT is a trademark of Texas Instruments Incorporated.
Page 6
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (continued)
0000h
0080h
1000h
107Fh
1EFFh
1F00h
Interrupts and Reset Vectors; Trap Vectors
FFFFh
0
RAM (Includes 128-Byte Registers File)
015
Program Counter
7
Legend:
Z=Zero
IE1=Level1 interrupts Enable
C=Carry
V=Overflow
N=Negative
IE2=Level2 interrupts Enable
IE1IE2ZNC
01234567
V
Status Register (ST)
Stack Pointer (SP)
R0(A)
R1(B)
R3
R63
0000h
0001h
0002h
003Fh
R127
0003h
R2
007Fh
Reserved
†
8K-Byte EPROM (6000h–7FFFh)
1FFFh
7FC0h
8000h
Peripheral File
256-Byte Data EEPROM
Reserved
†
Not Available
‡
007Fh
128-Byte RAM (0000h – 007Fh)
0FFFh
1080h
Not Available
‡
4K-Byte ROM (7000h–7FFFh)
2000h
5FFFh
6000h
6FFFh
7000h
7FBFh
7FFFh
†
Reserved means that the address space is reserved for future expansion.
‡
Not available means that the address space is not accessible.
Figure 1. Programmer’s Model
Page 7
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (continued)
The ’x9x CPU architecture provides the following components:
D
CPU registers:
– A stack pointer that points to the last entry in the memory stack
– A status register that monitors the operation of the instructions and contains the global-interrupt-enable
bits
– A program counter (PC) that points to the memory location of the next instruction to be executed
D
A memory map that includes :
– 128 bytes of general-purpose RAM that can be data memory storage, program instructions,
general-purpose register, or the stack (can be located only in the first 128 bytes)
– A peripheral file that provides access to all internal peripheral modules, system-wide control functions,
and EEPROM/EPROM programming control
– A 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off
conditions
– 4K bytes of ROM or 8K bytes of EPROM program memory
stack pointer (SP)
The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. The stack is used
typically to store the return address on subroutine calls as well as the status register contents during interrupt
sequences.
The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed
onto the stack and decrements after data is popped from the stack. The stack can be located only in the first
128 bytes of the on-chip RAM memory.
status register (ST)
The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes
four status bits (condition flags) and two interrupt-enable bits:
D
The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional jump instructions) use these status bits to determine program flow.
D
The two interrupt-enable bits control the two interrupt levels.
The ST register and status bit notation are shown in Table 3.
Table 3. Status Register
7
6
5
4
3
2
1
0
C
N
Z
V
IE2
IE1
Reserved
Reserved
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = read, W = write, 0 = value after reset
Page 8
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (continued)
program counter (PC)
The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.
The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH
(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is
loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of
6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).
Memory
Program Counter (PC)
60 00
PCH PCL
60
00
0000h
7FFEh
7FFFh
Figure 2. Program Counter After Reset
memory map
The TMS370Cx9x architecture is based on the Von Neuman architecture, where the program memory and data
memory share a common address space. All peripheral input/output is memory mapped in this same common
address space. As shown in Figure 3, the TMS370Cx9x provides a memory-mapped RAM, ROM, data
EEPROM, EPROM, input/output pins, peripheral functions, and system-interrupt vectors.
The peripheral file contains all input/output port control, peripheral status and control, EPROM, EEPROM
programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses
located from 1000h to 107Fh and logically divided into seven peripheral file frames of 16 bytes each. Each
on-chip peripheral is assigned to a separate frame through which peripheral control and data information is
passed. The TMS370Cx9x has its on-chip peripherals and system control assigned to peripheral file frames 1
through 7, addresses 1010h through 107Fh.
Page 9
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (continued)
Peripheral File Control Registers
1000h–100Fh
Reserved
1010h–101Fh
System Control
1020h–102Fh
Digital Port Control
1030h–103Fh
Reserved
1040h–104Fh
Timer 1 Peripheral Control
1050h–106Fh
Reserved
1070h–107Fh
ADC3 Peripheral Control
Vectors
7FC0h–7FDFh
Trap 0–15
7FE0h–7FEBh
Reserved
7FECh–7FEDh
Analog-to-Digital Converter 3
7FEEh–7FF3h
Reserved
Reserved
7FF4h–7FF5h
Timer 1
7FF6h–7FF7h
Reserved
7FF8h–7FF9h
Interrupt 1
7FFAh–7FFBh
7FFCh–7FFDh
7FFEh–7FFFhReset
0000h
0080h
1000h
107Fh
1EFFh
1F00h
Interrupts and Reset Vectors; Trap Vectors
FFFFh
Reserved
†
8K-Byte EPROM (6000h–7FFFh)
1FFFh
7FC0h
8000h
Peripheral File
256-Byte Data EEPROM
Reserved
†
Not Available
‡
007Fh
128-Byte RAM (0000h – 007Fh)
(Register File/Stack)
0FFFh
1080h
Not Available
‡
4K-Byte ROM (7000h–7FFFh)
2000h
5FFFh
6000h
6FFFh
7000h
7FBFh
7FFFh
Reserved
†
Reserved = the address space is reserved for future expansion.
‡
Not available = address space is unavailable in the mode illustrated.
Figure 3. TMS370Cx9x Memory Map
RAM/register file (RF)
Locations within RAM address space can serve as the register file, general-purpose read/write memory,
program memory, or stack instructions. The TMS370Cx9x device contains 128 bytes of internal RAM mapped
beginning at location 0000h (R0) and continuing through location 007Fh (R127) which is shown in Figure 3.
The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the
stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.
peripheral file (PF)
The TMS370Cx9x control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the peripheral file (PF)
directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0
for a hexadecimal designator or by P for a decimal designator. For example, the system control register 0
(SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal
designator is P16. Table 4 shows the TMS370Cx9x peripheral files address map.
Page 10
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
peripheral file (PF) (continued)
Table 4. TMS370Cx9x Peripheral File Address Map
БББББ
Á
ADDRESS RANGE
БББББ
Á
PERIPHERAL FILE
DESIGNAT OR
ББББББББББББББББББББ
Á
DESCRIPTION
1000h–100Fh
P000–P00F
Reserved
1010h–101Fh
P010–P01F
System and EEPROM/EPROM control registers
1020h–103Fh
P020–P03F
Digital I/O port control registers
1030h–103Fh
P030–P03F
Reserved
1040h–104Fh
P040–P04F
Timer 1 registers
1050h–106Fh
P050–P06F
Reserved
1070h–107Fh
P070–P07F
Analog-to-digital converter 3 registers
1080h–10FFh
P080–P0FF
Reserved
data EEPROM
The TMS370Cx9x devices contain 256 bytes of data EEPROM and have a memory map beginning at location
1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data
EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm
examples are available in the
TMS370 Family User’s Guide
(literature number SPNU127), or the
TMS370
Family Data Manual
(literature number SPNS014B). The data EEPROM features include the following:
D
Programming:
– Bit, byte, and block write/erase modes
– Internal charge pump circuitry: No external EEPROM programming voltage supply is needed.
– Control register: Data EEPROM programming is controlled by the data EEPROM control register
(DEECTL) located in the PF frame beginning at location P01A.
– In-circuit programming capability: There is no need to remove the device to program.
D
Write-protection: Writes to the data EEPROM are disabled during the following conditions:
– Reset: All programming of the data EEPROM module is halted.
– Write protection active: there is one write-protect bit per 32-byte EEPROM block.
– Low-power mode operation
D
Write protection can be overridden by applying 12 V to the MC pin.
Table 5 shows the memory map of the control registers.
T able 5. Data EEPROM and Program EPROM Control Registers Memory Map
ADDRESS
SYMBOL
БББББББББББББББББББ
NAME
101Ah (P01A)
DEECTL
БББББББББББББББББББ
Data EEPROM control register
101Bh (P01B)
—
БББББББББББББББББББ
Reserved
101Ch (P01C)
EPCTL
БББББББББББББББББББ
Program EPROM control register
Page 11
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
program EPROM
The TMS370C792 contains 8K bytes of program EPROM memory mapped beginning at location 6000h and
continuing through location 7FFFh as shown in Figure 3. Memory addresses 7FE0h through 7FEBh are
reserved for T exas Instruments (TI) and addresses 7FECh through 7FFFh are reserved for interrupt and reset
vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h
and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During
programming, the EPROM is controlled by the program EPROM control register (EPCTL). The program
EPROM modules’ features include:
D
Programming
– In-circuit programming capability if V
PP
is applied to the MC pin
– Control register: Program EPROM programming is controlled by the program EPROM control registers
EPCTL located at the addresses in PF frame 1 as shown in Table 5.
D
Write protection: Writes to the program EPROM are disabled under the following conditions:
– Reset: All programming to the EPROM module is halted.
– Low-power modes
– 13 V not applied to MC
program ROM
The program ROM consists of 4K bytes of mask-programmable ROM. The program ROM is used for permanent
storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication.
Memory addresses 7FE0h through 7FEBh are reserved for TI and addresses 7FECh through 7FFFh are
reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are
located between addresses 7FC0h and 7FDFh.
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx9x CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
internally generated, while one (RESET) is controlled externally. These actions are as follows:
D
External RESET pin. A low level signal can trigger an external reset. To assure a reset, the external signal
should be held low for one SYSCLK cycle (it is possible, however, that a signal of less than one SYSCLK
could cause a reset). See the
TMS370 User’s Guide
(literature number SPNU127) or the
TMS370 Family
Data Manual
(SPNS014B) for more information.
D
Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register or if the re-initialization does not occur before the watchdog timer timeout . See the
TMS370 User’s
Guide
(literature number SPNU127) or the
TMS370 Family Data Manual
(SPNS014B) for more information.
D
Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.
See the
TMS370 User’s Guide
(literature number SPNU127) or the
TMS370 Family Data Manual
(SPNS014B) for more information.
Once a reset source is activated, the external RESET
pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x9x device to reset external system components. Additionally, if a cold start condition
(V
CC
is off for several hundred milliseconds), oscillator failure occurs, or RESET pin is held low , then the reset
logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag
(COLD ST ART , SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 6 depicts the reset sources.
TI is a trademark of Texas Instruments Incorporated.
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TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
system reset (continued)
Table 6. Reset Sources
REGISTER
ADDRESS
PF
BIT NO.
CONTROL BIT NAME
SOURCE OF RESET
SCCR0
1010h
P010
7
COLD START
Cold (power-up)
SCCR0
1010h
P010
4
OSC FLT FLAG
Oscillator out of range
T1CTL2
104Ah
P04A
5
WD OVRFL INT FLAG
Watchdog timer timeout
Once a reset is activated, the following sequence of events occurs:
1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
2. Registers A and B are initialized to 00h (no other RAM is changed).
3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5. Program execution begins with an opcode fetch from the address pointed to by the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.
interrupts
The TMS370 family software programmable interrupt structure permits flexible on-chip and external-interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of
the status register.
Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
Page 13
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupts (continued)
TIMER 1
CPU
NMI
Logic
Enable
IE1
IE2
Level 1 INT
Level 2 INT
T1 PRI
Priority
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
STATUS REG
EXT INT1
INT1 PRI
INT1
Watchdog
AD INT
AD PRI
A/D
Figure 4. Interrupt Control
The TMS370Cx9x has three hardware system interrupts (plus RESET) as shown in Table 7. Each system
interrupt has a dedicated vector located in program memory through which control is passed to the interrupt
service routines. A system interrupt can have multiple interrupt sources. All of the interrupt sources are
individually maskable by local interrupt-enable control bits in the associated PF. Each interrupt source FLAG
bit is individually readable for software polling or for determining which interrupt source generated the
associated system interrupt.
Two of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is
supported. Software configuration of the external interrupt is performed through the INT1 control registers in
peripheral file frame 1. The external is software-configurable for input polarity (rising or falling edge) for ease
of system interface. External interrupt INT1 is software-configurable as either a maskable or non-maskable
interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual or global enable
mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured
during the initialization sequence following reset. To maximize pin flexibility, external interrupt INT1 can be
software-configured as a general-purpose input pin if the interrupt function is not required.
Page 14
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupts (continued)
T able 7. Hardware System Interrupts
БББББББББ
Á
INTERRUPT SOURCE
БББББББ
Á
INTERRUPT FLAG
ÁÁÁÁ
Á
SYSTEM
INTERRUPT
ÁÁÁÁ
Á
VECTOR
ADDRESS
ÁÁÁÁ
Á
PRIORITY
†
БББББББББ
Á
External RESET
Watchdog overflow
Oscillator fault detect
БББББББ
Á
COLD START
WD OVRFL INT FLAG
OSC FLT FLAG
ÁÁÁÁ
Á
RESET
‡
ÁÁÁÁ
Á
7FFEh, 7FFFh
ÁÁÁÁ
Á
1
External INT1
INT1 FLAG
INT1
‡
7FFCh, 7FFDh
2
БББББББББ
Á
БББББББББ
Á
БББББББББ
Á
Timer 1 overflow
Timer 1 compare 1
Timer 1 compare 2
Timer 1 external edge
Timer 1 input capture 1
Watchdog overflow
БББББББ
Á
БББББББ
Á
БББББББ
Á
T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC1 INT FLAG
WD OVRFL INT FLAG
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
T1INT
§
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
7FF4h, 7FF5h
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
3
A/D conversion complete
AD INT FLAG
ADINT
7FECh, 7FEDh
4
†
Relative priority within an interrupt level.
‡
Releases microcontroller from STANDBY and HALT low-power modes.
§
Releases microcontroller from STANDBY low-power mode.
privileged operation and EEPROM write-protection override
The TMS370Cx9x family has significant flexibility to enable the designer to software-configure the system and
peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation
ensures the integrity of the system configuration, once it is defined for an application. Following a hardware
reset, the TMS370Cx9x operates in the privileged mode, where all peripheral file registers have unrestricted
read/write access, and the application program configures the system during the initialization sequence
following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set
to one to enter the nonprivileged mode; disabling write operations to specific configuration control bits within
the peripheral file. Table 8 displays the system configuration bits that are write-protected during the
nonprivileged mode and must be configured by software prior to exiting the privileged mode.
Table 8. Privilege Bits
REGISTER
¶
NAME
LOCATION
CONTROL BIT
ÁÁÁÁ
Á
SCCRO
ÁÁÁ
Á
P010.6
P010.6
БББББББББ
Á
PF AUTO WAIT
OSC POWER
SCCR1
P011.2
P011.4
MEMORY DISABLE
AUTOWAIT DISABLE
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
SCCR2
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
P012.0
P012.1
P012.3
P012.4
P012.6
P012.7
БББББББББ
Á
БББББББББ
Á
БББББББББ
Á
PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY
ÁÁÁÁ
Á
T1PRI
ÁÁÁ
Á
P04F.6
P04F.7
БББББББББ
Á
T1 PRIORITY
T1 STEST
ÁÁÁÁ
Á
ADPRI
ÁÁÁ
Á
P07F.5
P07F.6
P07F.7
БББББББББ
Á
AD ESPEN
AD PRIORITY
AD STEST
¶
The privilege bits are shown in a bold typeface in the system configuration
registers section.
Page 15
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
privileged operation and EEPROM write-protection override (continued)
The write-protect override (WPO) mode provides an external hardware method of overriding the
write-protection registers of data EEPROM on the TMS370Cx9x. Applying a 12-V input to the MC pin after the
RESET input goes high (logic 1) enters the WPO mode. The high voltage on MC during the WPO mode is not
the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware system level capability to modify the content of the data
EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes
The TMS370Cx9x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.
The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the idle instruction when the PWRDWN/IDLE bit in register SCCR2 has been set to one.
The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.
In the ST ANDBY mode (HAL T/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, and timer 1 remain active. System processing is suspended until a
qualified interrupt (hardware RESET
, external interrupt on INT1, or timer 1 interrupt) is detected.
In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx9x is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET or an external interrupt on INT1) is detected. The
low-power mode selection bits are summarized in Table 9.
Table 9. Low-Power/Idle Control Bits
POWER-DOWN CONTROL BITS
ÁÁÁ
Á
PWRDWN/IDLE
(SCCR2.6)
ÁÁÁÁ
Á
HALT/STANDBY
(SCCR2.7)
БББББББ
Á
MODE SELECTED
1
0
STANDBY
1
1
HALT
0
X
IDLE
X = don’t care
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6–7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.
T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is always generated, regardless of the interrupt enable flags.
The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the
STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.
Page 16
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
clock modules
The ‘370Cx9x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4
(standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing
process of a TMS370 microcontroller. The ‘370C090A ROM-masked devices of fer both options to meet system
engineering requirements. Only one of the two clock options is allowed on the ROM device while the EPROM
device ’792 has only the divide-by-4 clock.
The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.
The divide-by-1 provides a 1-to-1 match of the external resonator frequency (CLKIN) to the internal system clock
(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external
resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four . The clock
module then divides the resulting signal by four to provide the four-phased internal system clock signals. The
resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:
Divide-by-4 option : SYSCLK
+
external resonator frequency
4
+
CLKIN
4
Divide-by-1 option : SYSCLK
+
external resonator frequency 4
4
+
CLKIN
The main advantage of choosing a divide-by-1 oscillator is that EMI is reduced. The harmonics of low-speed
resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The
divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper
decay of emissions produced by the oscillator.
Page 17
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
system configuration registers
Table 10 contains system configuration and control functions and registers for controlling EEPROM
programming. The privileged bits are shown in a bold typeface and shaded.
Table 10. Peripheral File Frame 1: System Configuration Registers
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
Á
Á
P010
ÁÁ
Á
COLD
START
OSC
POWER
PF AUTO
WAIT
ÁÁ
Á
OSC FLT
FLAG
ÁÁÁ
Á
MC PIN
WPO
ÁÁ
Á
MC PIN
DATA
ÁÁÁ
Á
—
ÁÁ
Á
µP/µC
MODE
ÁÁ
Á
SCCR0
P011
—
—
—
AUTOWAIT
DISABLE
—
MEMORY
DISABLE
—
—
SCCR1
Á
Á
P012
HALT/
STANDBY
PWRDWN/
IDLE
ÁÁ
Á
—
BUS
STEST
CPU
STEST
ÁÁ
Á
—
INT1
NMI
PRIVILEGE
DISABLE
ÁÁ
Á
SCCR2
P013
t
o
P016
Reserved
Á
Á
P017
ÁÁ
Á
INT1
FLAG
ÁÁÁ
Á
INT1
PIN DATA
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
INT1
POLARITY
ÁÁÁ
Á
INT1
PRIORITY
ÁÁ
Á
INT1
ENABLE
ÁÁ
Á
INT1
Á
Á
P018
to
P019
ББББББББББББББББББББББББББ
Á
Reserved
ÁÁ
Á
P01A
BUSY
—
—
—
—
AP
W1W0
EXE
DEECTL
P01B Reserved
P01C
BUSY
VPPS
—
—
—
—
W0
EXE
EPCTL
Á
Á
Á
Á
P01D
to
P01F
Reserved
ÁÁ
Á
ÁÁ
Á
Page 18
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
digital port control registers
Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11 displays the
specific addresses, registers, and control bits within this peripheral file frame.
Table 11. Peripheral File Frame 2: Digital Port Control Registers
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ÁÁÁÁ
REG
P020
Reserved
ÁÁÁÁ
APORT1
P021
Port A Control Register 2 (must be 0)
ÁÁÁÁ
APORT2
P022
Port A Data
ÁÁÁÁ
ADATA
P023
Port A Direction
ÁÁÁÁ
ADIR
ÁÁ
Á
P024
to
P02B
ББББББББББББББББББББББББББ
Á
Reserved
ÁÁÁÁ
Á
ÁÁ
Á
P02C
Port D Control Register 1 (must be 0)
—
—
—
ÁÁÁÁ
DPORT1
P02D
Port D Control Register 2† (must be 0)
—
—
—
ÁÁÁÁ
DPORT2
P02E
Port D Data
—
—
—
ÁÁÁÁ
DDATA
P02F
Port D Direction
—
—
—
DDIR
ÁÁÁÁ
†
To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Table 12. Port Configuration Register Setup
PORT PIN
abcd
00q1
abcd
00y0
A 0–7 Data out q Data in y
D 3–7 Data out q Data in y
a = Port x control register 1
b = Port x control register 2
c = Data
d = Direction
timer 1 module
The programmable timer 1 (T1) module of the TMS370Cx9x provides the designer with the enhanced timer
resources required to perform real-time system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD, allow program selection of input clock
sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and
compare) for special timer function control. The T1 module includes three external device pins that can be used
for multiple counter functions (operation-mode dependent) or used as general-purpose I/O pins. The T1 module
block diagram is shown in Figure 5.
Page 19
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
T1IC/CR
Edge
Select
16-Bit
Counter
T1EVT
MUX
MUX
16-Bit
Register
T1PWM
PWM
Toggle
16
16-Bit
WatchdogCounter
(Aux. Timer)
Interrupt
Logic
Capt/Comp
16-Bit
Register
Compare
Interrupt
Logic
8-Bit
Prescaler
Figure 5. Timer 1 Block Diagram
D
Three T1 I/O pins:
– T1IC/CR: Timer 1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin
– T1PWM: Timer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
– T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin
D
Two operation modes:
– Dual-compare mode: Provides PWM signal.
– Capture/compare mode: Provides input capture pin.
D
One 16-bit general-purpose resettable counter
D
One 16-bit compare register with associated compare logic
D
One 16-bit capture / compare register, which, depending on the mode of operation, operates as either
capture or compare registers.
D
One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer
if watchdog feature is not needed.
D
Prescaler/clock sources that determines one of eight clock sources for general-purpose timer
D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC/CR).
Page 20
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
D
Interrupts that can be generated on the occurrence of:
– A capture
– A compare equal
– A counter overflow
– An external edge detection
D
Sixteen T1 module control registers: Located in the PF frame beginning at address P040.
Table 13 lists the T1 module control registers.
Table 13. Timer 1 Module Register Memory Map
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
Modes: Capture/Compare and Dual-Compare
P040
Bit 15
T1 Counter MSbyte
Bit 8
T1CNTR
P041
Bit 7
T1 Counter LSbyte
Bit 0
P042
Bit 15
Compare Register MSbyte
Bit 8
T1C
P043
Bit 7
Compare Register LSbyte
Bit 0
P044
Bit 15
Capture/Compare Register MSbyte
Bit 8
T1CC
P045
Bit 7
Capture/Compare Register LSbyte
Bit 0
P046
Bit 15
Watchdog Counter MSbyte
Bit 8
WDCNTR
P047
Bit 7
Watchdog Counter LSbyte
Bit 0
P048
Bit 7
Watchdog Reset Key
Bit 0
WDRST
Á
Á
Á
Á
P049
ÁÁÁ
Á
ÁÁÁ
Á
WD OVRFL
TAP SEL
†
ÁÁ
Á
ÁÁ
Á
WD
INPUT
SELECT2
†
ÁÁÁ
Á
ÁÁÁ
Á
WD
INPUT
SELECT1
†
ÁÁ
Á
ÁÁ
Á
WD
INPUT
SELECT0
†
ÁÁ
Á
ÁÁ
Á
—
ÁÁÁ
Á
ÁÁÁ
Á
T1
INPUT
SELECT2
ÁÁ
Á
ÁÁ
Á
T1
INPUT
SELECT1
ÁÁÁ
Á
ÁÁÁ
Á
T1 INPUT
SELECT0
ÁÁ
Á
ÁÁ
Á
T1CTL1
P04A
WD OVRFL
RST ENA
†
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
—
—
T1 SW
RESET
T1CTL2
Mode: Dual-Compare
Á
Á
P04B
ÁÁÁ
Á
T1EDGE
INT FLAG
ÁÁ
Á
T1C2
INT FLAG
ÁÁÁ
Á
T1C1
INT FLAG
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
T1EDGE
INT ENA
ÁÁ
Á
T1C2
INT ENA
ÁÁÁ
Á
T1C1
INT ENA
ÁÁ
Á
T1CTL3
P04C
T1
MODE = 0
T1C1
OUT ENA
T1C2
OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
T1EDGE
POLARITY
T1CR
RST ENA
T1EDGE
DET ENA
T1CTL4
Mode: Capture/Compare
Á
Á
P04B
ÁÁÁ
Á
T1EDGE
INT FLAG
ÁÁ
Á
—
ÁÁÁ
Á
T1C1
INT FLAG
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
T1EDGE
INT ENA
ÁÁ
Á
—
ÁÁÁ
Á
T1C1
INT ENA
ÁÁ
Á
T1CTL3
P04C
T1
MODE = 1
T1C1
OUT ENA
—
T1C1
RST ENA
—
T1EDGE
POLARITY
—
T1EDGE
DET ENA
T1CTL4
Modes: Capture/Compare and Dual-Compare
Á
Á
P04D
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁ
Á
T1EVT
DATA IN
ÁÁÁ
Á
T1EVT
DATA OUT
ÁÁ
Á
T1EVT
FUNCTION
ÁÁÁ
Á
T1EVT
DATA DIR
ÁÁ
Á
T1PC1
P04E
T1PWM
DATA IN
T1PWM
DATA OUT
T1PWM
FUNCTION
T1PWM
DATA DIR
T1IC/CR
DATA IN
T1IC/CR
DATA OUT
T1IC/CR
FUNCTION
T1IC/CR
DATA DIR
T1PC2
Á
Á
P04F T1 STEST
T1
PRIORITY
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
T1PRI
†
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
Page 21
TMS370Cx9x
8-BIT MICROCONTROLLER
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timer 1 module (continued)
The T1 capture/compare mode block diagram is illustrated in Figure 6. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,
bit 0, in the T1CTL2 register.
T1CTL4.2
16
Compare=
Edge
Select
T1IC/CR
T1EDGE POLARITY
T1EDGE DET ENA
Prescale
Clock
Source
16-Bit
Counter
MSB
LSB
T1CNTR.15-0
Reset
T1C1
RST ENA
T1 SW
RESET
T1CTL2.0
T1CTL4.4
T1PC2.3-0
T1CTL4.0
T1EDGE INT FLAG
T1EDGE INT ENA
T1CTL3.7
T1CTL3.2
T1 OVRFL INT FLAG
T1 OVRFL INT ENA
T1CTL2.3
T1CTL2.4
T1C1 INT FLAG
T1C1 INT ENA
T1CTL3.5
T1CTL3.0
T1C1
OUT ENA
T1PWM
T1CTL4.6
Toggle
T1PC2.7-4
16-Bit
Capt/Comp
MSB
LSB
Register
T1CC.15-0
T1C.15-0
16-Bit
Compare
MSB
LSB
Register
T1 PRIORITY
T1PRI.6
Level 1 Int
Level 2 Int
0
1
Figure 6. Capture/Compare Mode
Page 22
TMS370Cx9x
8-BIT MICROCONTROLLER
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22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,
bit 0, in the T1CTL2 register.
T1CTL4.1
T1CTL4.4
Prescaler
Clock
Source
16-Bit
Counter
16-Bit
16
Compare=
Compare=
Reset
T1C1
RST ENA
T1 SW
RESET
Edge
Select
T1EDGE DET ENA
Output
Enable
Capt/Comp
Register
MSB
LSB
MSB
LSB
T1CR OUT ENA
T1IC/CR
T1EDGE POLARITY
Toggle
16-Bit
Compare
MSB
LSB
Register
T1CC.15-0
T1C1 INT FLAG
T1CTL3.0
T1CTL3.5
T1C1 INT ENA
T1C2 INT FLAG
T1CTL3.1
T1CTL3.6
T1C2 INT ENA
T1 OVRFL INT FLAG
T1CTL2.4
T1CTL2.3
T1 OVRFL INT ENA
T1EDGE INT FLAG
T1CTL3.2
T1CTL3.7
T1EDGE INT ENA
T1 PRIORITY
T1C2 OUT ENA
T1C1 OUT ENA
T1CTL4.3
T1CTL4.6
T1CTL4.5
T1PWM
T1PC2.7-4
T1PRI.6
T1C.15-0
T1CNTR.15-0
T1CTL2.0
T1CR
RST ENA
T1PC2.3-0
T1CTL4.0
T1CTL4.2
Level 1 Int
Level 2 Int
0
1
Figure 7. Dual-Compare Mode
Page 23
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
The TMS370Cx9x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be
software programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used.
The WD function is to monitor software and hardware operation and implement a system reset when the WD
counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value). The
WD can be configured as one of the three mask options: standard WD, hard WD, or simple counter.
D
Standard watchdog configuration for EPROM and mask-ROM devices (see Figure 8)
– Watchdog mode
– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
– Generates a system reset if an incorrect value is written to the WD reset key or if the counter
overflows
– A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a
system reset
– Non-watchdog mode
– Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer
16-Bit
Watchdog Counter
Reset
Prescaler
Clock
Watchdog Reset Key
WD OVRFL
TAP SEL
WD OVRFL
RST ENA
System Reset
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.7
T1CTL2.5
WD OVRFL
INT ENA
Interrupt
T1CTL2.6
WD OVRFL
INT FLAG
Figure 8. Standard Watchdog
Page 24
TMS370Cx9x
8-BIT MICROCONTROLLER
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
D
Hard watchdog configuration for mask-ROM device only (see Figure 9)
– Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter
overflows.
– Automatic activation of the WD timer upon power-up reset
– INT1 is enabled as nonmaskable interrupt during low-power modes
– A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system
reset.
16-Bit
Watchdog Counter
Reset
Prescaler
Clock
Watchdog Reset Key
WD OVRFL
TAP SEL
System Reset
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.5
WD OVRFL
INT FLAG
Figure 9. Hard Watchdog
Page 25
TMS370Cx9x
8-BIT MICROCONTROLLER
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25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer 1 module (continued)
D
Simple-counter configuration for mask-ROM devices only (see Figure 10)
– Simple counter can be configured as an event counter, pulse accumulator, or an interval timer.
16-Bit
Watchdog Counter
Reset
Prescaler
Clock
Watchdog Reset Key
WD OVRFL
TAP SEL
T1CTL1.7
WDRST.7-0
WDCNTR.15-0
T1CTL2.5
WD OVFL
INT FLAG
WD OVRFL
INT ENA
Interrupt
T1CTL2.6
Figure 10. Simple Counter
analog-to-digital converter 3 module
The analog-to-digital converter 3 module is an 8-bit, successive approximation converter with internal
sample-and-hold circuitry . The module has fifteen analog input channels – eight of the channels are multiplexed
with port E – that allow the processor to convert the voltage levels from up to fifteen different sources. The ADC3
module features include the following:
D
Minimum conversion time: 32.8 µs at 5-MHz SYSCLK
D
Seventeen external pins:
– Fifteen analog input channels (AN0–AN14), eight (AN0–AN7) of which can be software configured as
digital inputs (E0–E7) if not needed as analog channels
– AN6–AN7 can also be configured as positive input voltage reference
–V
CC3
: ADC3 module high-voltage reference input
–V
SS3
: ADC3 module low-voltage reference input
D
The ADDATA register, which contains the digital result of the last ADC3 conversion
D
ADC3 operations can be accomplished through either interrupt driven or polled algorithms
D
Six ADC3 module control registers are located in the ADC3 peripheral control register frame beginning at
address 1070h.
Page 26
TMS370Cx9x
8-BIT MICROCONTROLLER
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26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
The ADC3 module control registers are illustrated in Table 14.
Table 14. ADC3 Module Control Register Memory Map
ÁÁÁÁ
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
ÁÁ
Á
P070
ÁÁ
Á
CONVERT
START
ÁÁ
Á
SAMPLE
START
ÁÁÁ
Á
REF VOLT
SELECT1
ÁÁÁÁ
ÁÁÁ
Á
REF VOLT
SELECT0
ÁÁ
Á
AD INPUT
SELECT3
ÁÁÁ
Á
AD INPUT
SELECT2
ÁÁ
Á
AD INPUT
SELECT1
ÁÁ
Á
AD INPUT
SELECT0
ÁÁÁ
Á
ADCTL
ÁÁ
Á
P071
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁÁÁ
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
AD READY
ÁÁ
Á
AD INT
FLAG
ÁÁ
Á
AD INT
ENA
ÁÁÁ
Á
ADSTAT
P072
A/D Conversion Data Register
ADDATA
ÁÁ
Á
ÁÁ
Á
P073
to
P07C
БББББББББББББББББББББББББ
Á
БББББББББББББББББББББББББ
Á
Reserved
ÁÁÁ
Á
ÁÁÁ
Á
P07D
Port E Data Input Register
ADIN
P07E
Port E Input Enable Register
ADENA
ÁÁ
Á
P07F AD STEST
AD
PRIORITY
AD ESPEN
ÁÁÁÁ
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
AD RATE
SELECT1
ÁÁ
Á
AD RATE
SELECT0
ÁÁÁ
Á
ADPRI
Page 27
TMS370Cx9x
8-BIT MICROCONTROLLER
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
The A/D module block diagram is illustrated in Figure 11.
ADCTL.5–4
5 4
ADENA.0
REF VOLTS SELECT
ADCTL.3–0
2 1 0
AD INPUT SELECT
ADIN.0
Port E Input
ENA 0
Port E Data
AN 0
AN0
ADENA.1
ADIN.1
Port E Input
ENA 1
Port E Data
AN 1
AN1
ADENA.5
ADIN.5
Port E Input
ENA 5
Port E Data
AN 5
AN5
ADENA.6
ADIN.6
Port E Input
ENA 6
Port E Data
AN 6
AN6
ADENA.7
ADIN.7
Port E Input
ENA 7
Port E Data
AN 7
AN7
AN8
AN9
V
CC3
V
SS3
ADCTL.6
SAMPLE
START
ADCTL.7
CONVERT
START
ADDATA.7–0
A-to-D
Conversion
Data Register
ADSTAT.2
AD READY
AD PRIORITY
ADPRI.6
0
1
Level 1 INT
Level 2 INT
AD INT FLAG
ADSTAT.1
AD INT ENA
ADSTAT.0
A/D
ADPRI.1–0
1 0
AD RATE
SELECTS
3
AN14
Figure 11. ADC3 Block Diagram
Page 28
TMS370Cx9x
8-BIT MICROCONTROLLER
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
T able 15. ADC3 Peripheral Control Register (ADCTL)
ÁÁÁÁ
Bit #
7
ÁÁÁÁ
6
5
4
3
2
1
0
P070
CONVERT
START
ÁÁÁÁ
SAMPLE
START
REF VOLT
SELECT1
REF VOLT
SELECT0
AD INPUT
SELECT3
AD INPUT
SELECT2
AD INPUT
SELECT1
AD INPUT
SELECT0
RW–0
ÁÁÁÁ
RW–0
RW–0
RW–0
RW–0
RW–0
RW–0
RW–0
ÁÁÁÁ
R = read, W = write, –n = value of the bit after the register is reset
BIT 0–3 AD INPUT SELECT 0–3 (Analog Input Channel Select Bits 0–3)
These bits select the channel used for conversion. Channels should be changed only after the
ADC3 has cleared the SAMPLE ST ART and CONVERT ST ART bits. Changing the channel while
either SAMPLE START or CONVERT START is 1 invalidates the conversion in progress.
БББББ
Á
AD INPUT
SELECT 3
ÁÁÁÁ
Á
AD INPUT
SELECT 2
ÁÁÁÁ
Á
AD INPUT
SELECT 1
БББББ
Á
AD INPUT
SELECT 0
ÁÁÁÁ
Á
AD INPUT
CHANNEL
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
БББББ
Á
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
BIT 4–5 REF VOLT SELECT 4–5 (Reference Voltage (+V
REF
) Select Bits 4–5)
These bits select the channel the ADC3 uses for the positive voltage reference. These bits must
not change during the entire conversion.
REF VOLT
SELECT 1
REF VOLT
SELECT 0
+V
REF
SOURCE
ÁÁÁÁ
Á
ÁÁÁÁ
Á
0
0
1
БББББ
Á
БББББ
Á
0
1
0
ÁÁÁÁ
Á
ÁÁÁÁ
Á
V
CC3
AN6
AN7
BIT 6 SAMPLE START (Sample Start)
Setting this bit stops any ongoing conversion and starts sampling the selected input channel to
begin a new conversion. This bit is cleared by the ADC3. Entering HAL T or STANDBY mode clears
this bit and aborts any sampling in progress.
BIT 7 CONVERT START (Conversion Start)
Setting this bit starts the conversion. This bit is cleared by the ADC3. Entering HAL T or STANDBY
mode clears this bit and aborts any conversion in progress.
Page 29
TMS370Cx9x
8-BIT MICROCONTROLLER
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29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
T able 16. ADC3 Peripheral Control Register (ADSTAT)
Bit #
7
6
5
4
3
2
1
0
P071
—
—
—
—
—
AD
READY
AD INT
FLAG
AD INT
ENA
R–0
RC–0
RW–0
R = read, W = write, C = clear only, –n = value of the bit after the register is reset
BIT 0 AD INT ENA (ADC3 Interrupt Enable)
This bit controls the ADC3 module’s ability to generate an interrupt.
0 = Disable ADC3 interrupt.
1 = Enable ADC3 interrupt.
BIT 1 AD INT FLAG (ADC3 Interrupt Flag)
The ADC3 module sets this bit at the end of an A/D conversion. If this bit is set while the AD INT
ENA bit is set, an interrupt request is generated. Clearing this flag clears pending ADC3 interrupt
requests. This bit is cleared by the system reset or by entering HAL T or STANDBY mode. Software
cannot set this bit.
BIT 2 AD READY (ADC3 Converter Ready)
The ADC3 module sets this bit whenever a conversion is not in progress and the ADC3 is ready
for a new conversion to start. Writing to this bit has no effect on its state.
0 = Conversion in process.
1 = Converter ready.
BIT 3–7 Reserved (Read data is indeterminate)
Table 17. ADC3
Conversion Data Register (DATA)
Bit #
7
6
5
4
3
2
1
0
P072
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
R–0
R–0
R–0
R–0
R–0
R–0
R–0
R–0
R = read, –n = value of the bit after the register is reset
The analog-to-digital conversion data is loaded into this register at the end of a conversion and remains until
replaced by another conversion
Table 18. AN0–AN7 Data Input Register (ADIN)
Bit #
7
6
5
4
3
2
1
0
Á
Á
Á
Á
P07D
ÁÁÁ
Á
ÁÁÁ
Á
PORT E
DATA IN
AN7
ÁÁÁ
Á
ÁÁÁ
Á
PORT E
DATA IN
AN6
ÁÁ
Á
ÁÁ
Á
PORT E
DATA IN
AN5
ÁÁÁ
Á
ÁÁÁ
Á
PORT E
DATA IN
AN4
ÁÁÁ
Á
ÁÁÁ
Á
PORT E
DATA IN
AN3
ÁÁÁ
Á
ÁÁÁ
Á
PORT E
DATA IN
AN2
ÁÁ
Á
ÁÁ
Á
PORT E
DATA IN
AN1
ÁÁÁ
Á
ÁÁÁ
Á
PORT E
DATA IN
AN0
R–0
R–0
R–0
R–0
R–0
R–0
R–0
R–0
R = read, –n = value of the bit after the register is reset
Page 30
TMS370Cx9x
8-BIT MICROCONTROLLER
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30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 module (continued)
The ADIN register shows the data present at the pins configured for general-purpose input instead of ADC3
channels. A bit is configured as general-purpose input if the corresponding bit of the port-enable register
is a 1. Pins configured as ADC3 channels are read as 0’s. Writing to this address has no effect.
Table 19. AN0–AN7 Input-Enable Register (ADENA)
ÁÁÁÁ
Bit #
7
6
5
4
3
2
1
0
ÁÁ
Á
P07E
ÁÁÁ
Á
INPUT
ENA 7
ÁÁÁÁ
Á
ÁÁ
Á
INPUT
ENA 6
ÁÁÁ
Á
INPUT
ENA 5
ÁÁÁ
Á
INPUT
ENA 4
ÁÁ
Á
INPUT
ENA 3
ÁÁÁ
Á
INPUT
ENA 2
ÁÁÁ
Á
INPUT
ENA 1
ÁÁÁ
Á
INPUT
ENA 0
RW–0
ÁÁÁÁ
RW–0
RW–0
RW–0
RW–0
RW–0
RW–0
RW–0
R = read, –n = value of the bit after the register is reset
The ADENA register individually configures the pins AN0–AN7 as either analog input channels
or as general-purpose input pins
0 = The pin becomes an analog-input channel for the ADC3. When the bit is 0, the
corresponding bit in the ADIN register reads a 0.
1 = Enables the pin as a general-purpose input pin and its digital value can be read from the
corresponding bit in the ADIN register.
Table 20. Analog Interrupt Priority/Conversion Rate Register (ADPRI)
ÁÁÁÁ
Bit #
7
ÁÁÁÁ
6
5
4
3
2
1
0
P07F
AD
STEST
ÁÁÁÁ
AD
PRIORITY
AD
ESPEN
—
—
—
AD RATE
SELECT1
AD RATE
SELECT0
RP–0
ÁÁÁÁ
RP–0
RP–0
RW–0
RW–0
R = read, W = write, P = privileged write, –n = value of the bit after the register is reset
BIT 0–1 AD RATE SELECT 0–1 (ADC3 Conversion Rate Select Bits 0–1)
These bits determine the conversion rate of the ADC3 as a function of the system-clock frequency. Note that
only the default selection (0,0) provides full XT AL2/CLKIN frequency range together with 8-bit precision. Other
selections allow maintaining minimum conversion time at lower system-clock rates.
AD RATE
SELECT 1
AD RATE
SELECT 0
CONVERSION TIME
(NUMBER OF SYSTEM CLOCK CYCLES)
MAXIMUM SYSCLK
FREQUENCY
0
0
1
1
0
1
0
1
164
84
44
22
5 MHz ≥ SYSCLK > 2.5 MHz
2.5 MHz ≥ SYSCLK > 1.25 MHz
1.25 MHz ≥ SYSCLK > 0.625 MHz
0.625 MHz ≥ SYSCLK ≥ 0.5 MHz
NOTE: If selections different from (0,0) are used at XT AL2/CLKIN frequencies higher than specified in this table, the
8-bit precision of the ADC3 is not assured.
BIT 2–4 RESERVED (Read data is indeterminate)
Page 31
TMS370Cx9x
8-BIT MICROCONTROLLER
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31
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analog-to-digital converter 3 module (continued)
BIT 5 AD ESPEN (Emulator Suspend Enable)
Normally this bit has no effect. However , when using the XDS emulator to debug a program, this
bit determines what happens to the ADC3 when the program is suspended by an action such as
a hardware or software breakpoint.
0 = When the emulator is suspended, the ADC3 continues to run until the conversion is
complete.
1 = When the emulator is suspended, the ADC3 is frozen so that its state can be examined at
the point that the emulator was suspended. The conversion data is indeterminate upon
restart.
BIT 6 AD PRIORITY (ADC3 interrupt priority select)
This bit selects the priority level of the ADC3 interrupt.
0 = ADC3 Interrupt is a higher priority (level 1) request.
1 = ADC3 Interrupt is a lower priority (level 2) request.
BIT 7 AD STEST (This bit must be cleared to ensure proper operation)
instruction set overview
Table 21 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the
‘370Cx9x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the
opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction
of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.
For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes
in eight SYSCLK cycles.
Page 32
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
Template Release Date: 7–11–94
32
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
Table 21. TMS370 Family Opcode/Instruction Map
†
MSN
012345678 9 A B C D E F
0
JMP
#ra
2/7
INCW
#ra,Rd
3/11
MOV
Ps,A
2/8
CLRC /
TST A
1/9
MOV
A,B
1/9
MOV
A,Rd
2/7
TRAP
15
1/14
LDST
n
2/6
1JNra
2/5
MOV
A,Pd
2/8
MOV
B,Pd
2/8
MOV
Rs,Pd
3/10
MOV
Ps,B
2/7
MOV
B,Rd
2/7
TRAP
14
1/14
MOV
#ra[SP],A
2/7
2JZra
2/5
MOV
Rs,A
2/7
MOV
#n,A
2/6
MOV
Rs,B
2/7
MOV
Rs,Rd
3/9
MOV
#n,B
2/6
MOV
B,A
1/8
MOV
#n,Rd
3/8
MOV
Ps,Rd
3/10
DEC
A
1/8
DEC
B
1/8
DEC
Rd
2/6
TRAP
13
1/14
MOV
A,*ra[SP]
2/7
3JCra
2/5
AND
Rs,A
2/7
AND
#n,A
2/6
AND
Rs,B
2/7
AND
Rs,Rd
3/9
AND
#n,B
2/6
AND
B,A
1/8
AND
#n,Rd
3/8
AND
A,Pd
2/9
AND
B,Pd
2/9
AND
#n,Pd
3/10
INC
A
1/8
INC
B
1/8
INC
Rd
2/6
TRAP
12
1/14
CMP
*n[SP],A
2/8
4JPra
2/5
OR
Rs,A
2/7
OR
#n,A
2/6
OR
Rs,B
2/7
OR
Rs,Rd
3/9
OR
#n,B
2/6
OR
B,A
1/8
OR
#n,Rd
3/8
OR
A,Pd
2/9
OR
B,Pd
2/9
OR
#n,Pd
3/10
INV
A
1/8
INV
B
1/8
INV
Rd
2/6
TRAP
11
1/14
extend
inst,2
opcodes
L
S
5
JPZ
ra
2/5
XOR
Rs,A
2/7
XOR
#n,A
2/6
XOR
Rs,B
2/7
XOR
Rs,Rd
3/9
XOR
#n,B
2/6
XOR
B,A
1/8
XOR
#n,Rd
3/8
XOR
A,Pd
2/9
XOR
B,Pd
2/9
XOR
#n,Pd
3/10
CLR
A
1/8
CLR
B
1/8
CLR
Rn
2/6
TRAP
10
1/14
N
6
JNZ
ra
2/5
BTJO
Rs,A,ra
3/9
BTJO
#n,A,ra
3/8
BTJO
Rs,B,ra
3/9
BTJO
Rs,Rd,ra
4/11
BTJO
#n,B,ra
3/8
BTJO
B,A,ra
2/10
BTJO
#n,Rd,ra
4/10
BTJO
A,Pd,ra
3/11
BTJO
B,Pd,ra
3/10
BTJO
#n,Pd,ra
4/11
XCHB
A
1/10
XCHB A /
TST B
1/10
XCHB
Rn
2/8
TRAP
9
1/14
IDLE
1/6
7
JNC
ra
2/5
BTJZ
Rs.,A,ra
3/9
BTJZ
#n,A,ra
3/8
BTJZ
Rs,B,ra
3/9
BTJZ
Rs,Rd,ra
4/11
BTJZ
#n,B,ra
3/8
BTJZ
B,A,ra
2/10
BTJZ
#n,Rd,ra
4/10
BTJZ
A,Pd,ra
3/10
BTJZ
B,Pd,ra
3/10
BTJZ
#n,Pd,ra
4/11
SWAP
A
1/11
SWAP
B
1/11
SWAP
Rn
2/9
TRAP
8
1/14
MOV
#n,Pd
3/10
8JVra
2/5
ADD
Rs,A
2/7
ADD
#n,A
2/6
ADD
Rs,B
2/7
ADD
Rs,Rd
3/9
ADD
#n,B
2/6
ADD
B,A
1/8
ADD
#n,Rd
3/8
MOVW
#16,Rd
4/13
MOVW
Rs,Rd
3/12
MOVW
#16[B],Rpd
4/15
PUSH
A
1/9
PUSH
B
1/9
PUSH
Rd
2/7
TRAP
7
1/14
SETC
1/7
9JLra
2/5
ADC
Rs,A
2/7
ADC
#n,A
2/6
ADC
Rs,B
2/7
ADC
Rs,Rd
3/9
ADC
#n,B
2/6
ADC
B,A
1/8
ADC
#n,Rd
3/8
JMPL
lab
3/9
JMPL
*Rp
2/8
JMPL
*lab[B]
3/11
POP
A
1/9
POP
B
1/9
POP
Rd
2/7
TRAP
6
1/14
RTS
1/9
A
JLE
ra
2/5
SUB
Rs,A
2/7
SUB
#n,A
2/6
SUB
Rs,B
2/7
SUB
Rs,Rd
3/9
SUB
#n,B
2/6
SUB
B,A
1/8
SUB
#n,Rd
3/8
MOV
& lab,A
3/10
MOV
*Rp,A
2/9
MOV
*lab[B],A
3/12
DJNZ
A,#ra
2/10
DJNZ
B,#ra
2/10
DJNZ
Rd,#ra
3/8
TRAP
5
1/14
RTI
1/12
B
JHS
ra
2/5
SBB
Rs,A
2/7
SBB
#n,A
2/6
SBB
Rs,B
2/7
SBB
Rs,Rd
3/9
SBB
#n,B
2/6
SBB
B,A
1/8
SBB
#n,Rd
3/8
MOV
A, & lab
3/10
MOV
A, *Rp
2/9
MOV
A,*lab[B]
3/12
COMPL
A
1/8
COMPL
B
1/8
COMPL
Rd
2/6
TRAP
4
1/14
PUSH
ST
1/8
†
All conditional jumps (opcodes 01– 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ
instructions have a relative address as the last operand.
Page 33
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
• 33
Table 21. TMS370 Family Opcode/Instruction Map† (Continued)
MSN
01 2 3 4 5 6 7 8 9 A B C D E F
C
JNV
ra
2/5
MPY
Rs,A
2/46
MPY
#n,A
2/45
MPY
Rs,B
2/46
MPY
Rs,Rd
3/48
MPY
#n,B
2/45
MPY
B,A
1/47
MPY
#n,Rs
3/47
BR
lab
3/9
BR
*Rp
2/8
BR
*lab[B]
3/11
RR
A
1/8
RR
B
1/8
RR
Rd
2/6
TRAP
3
1/14
POP
ST
1/8
L
D
JGE
ra
2/5
CMP
Rs,A
2/7
CMP
#n,A
2/6
CMP
Rs,B
2/7
CMP
Rs,Rd
3/9
CMP
#n,B
2/6
CMP
B,A
1/8
CMP
#n,Rd
3/8
CMP
& lab,A
3/11
CMP
*Rp,A
2/10
CMP
*lab[B],A
3/13
RRC
A
1/8
RRC
B
1/8
RRC
Rd
2/6
TRAP
2
1/14
LDSP
1/7
S
N
EJGra
2/5
DAC
Rs,A
2/9
DAC
#n,A
2/8
DAC
Rs,B
2/9
DAC
Rs,Rd
3/11
DAC
#n,B
2/8
DAC
B,A
1/10
DAC
#n,Rd
3/10
CALL
lab
3/13
CALL
*Rp
2/12
CALL
*lab[B]
3/15
RL
A
1/8
RL
B
1/8
RL
Rd
2/6
TRAP
1
1/14
STSP
1/8
F
JLO
ra
2/5
DSB
Rs,A
2/9
DSB
#n,A
2/8
DSB
Rs,B
2/9
DSB
Rs,Rd
3/11
DSB
#n,B
2/8
DSB
B,A
1/10
DSB
#n,Rd
3/10
CALLR
lab
3/15
CALLR
*Rp
2/14
CALLR
*lab[B]
3/17
RLC
A
1/8
RLC
B
1/8
RLC
Rd
2/6
TRAP
0
1/14
NOP
1/7
Second byte of two-byte instructions (F4xx): F4 8
MOVW
*n[Rn]
4/15
DIV
Rn.A
3/14-63
F4 9
JMPL
*n[Rn]
4/16
Legend:
* = Indirect addressing operand prefix
& = Direct addressing operand prefix
F4 A
MOV
*n[Rn],A
4/17
# = immediate operand
#16 = immediate 16-bit number
lab = 16-label
F4 B
MOV
A,*n[Rn]
4/16
n = immediate 8-bit number
Pd = Peripheral register containing destination type
Pn = Peripheral register
p
F4 C
BR
*n[Rn]
4/16
Ps=Peri heral register containing source byte
ra = Relative address
Rd = Register containing destination type
Rn = Re
g
ister file
F4 D
CMP
*n[Rn],A
4/18
Rn Register file
Rp = Register pair
Rpd= Destination register pair
Rps = Source Register pair
F4 E
CALL
*n[Rn]
4/20
Rs = Register containing source byte
F4 F
CALLR
*n[Rn]
4/22
†
All conditional jumps (opcodes 01– 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ
instructions have a relative address as the last operand.
Page 34
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
development system support
The TMS370 family development support tools include an assembler, a C compiler, a linker, CDT, and an
EEPROM/UVEPROM programmer.
D
Assembler/linker (Part No. TMDS3740850–02 for PC)
– Includes extensive macro capability
– Provides high-speed operation
– Provides format conversion utilities for popular formats
D
ANSI C compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3,
or Sun-4)
– Generates assembly code for the TMS370 that can be easily inspected
– Improves code execution speed and reduces code size with optional optimizer pass
– Enables direct referencing of the TMS370’s port registers by using a naming convention
– Provides flexibility in specifying the storage for data objects
– Interfaces C functions and assembly functions easily
– Includes assembler and linker
D
CDT370 (compact development tool) PACT real-time in-circuit emulation
– Base (Part Number EDSCDT37P – for PC, requires cable)
– Cable for 40-pin SDIP (Part No. EDSTRG40SDIL05)
– Cable for 44-pin PLCC (Part No. EDSTRG44PLCC05)
– Includes EEPROM and EPROM programming support
– Allows inspection and modification of memory locations
– Uploads/downloads program and data memory
– Executes programs and software routines
– Includes 1024-sample trace buffer
– Includes single-step executable instructions
– Uses software breakpoints to halt program execution at selected address
D
Microcontroller programmer
– Base (Part No. TMDS3760500A — for PC, requires programmer head)
– Single unit head for 44-pin PLCC and 40-pin SDIP (Part No. TMDS3780513A)
– Includes PC-based, window /function-key oriented user interface for ease of use and rapid learning
environment
HP700 is a trademark of Hewlett-Packard Company.
Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.
Page 35
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device numbering conventions
Figure 12 illustrates the numbering and symbol nomenclature for the TMS370Cx9x family.
0370 9 0C
Prefix: TMS = Standard prefix for fully qualified devices
SE = System evaluator (window EPROM) that is used for
prototyping purpose
Family: 370 = TMS370 8-Bit Microcontroller Family
Technology: C = CMOS
Program Memory Types: 0 = Mask ROM
7 = EPROM
Device Type: 9 = ’x9x devices containing the following modules:
– Timer 1
– Analog-to-Digital Converter 3 (ADC3)
Memory Size: 0 = 4K bytes
2 = 8K bytes
Temperature Ranges: A = –40°Cto 85°C
L= 0°Cto 70°C
T=–40°Cto 105°C
Packages: FN = Plastic Leaded Chip Carrier
FZ = Ceramic Leaded Chip Carrier
N = Plastic Dual-In-Line
JD = Ceramic Dual-in-Line
ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured
as one of the three different mask options:
– A standard watchdog
– A hard watchdog
– A simple watchdog
The clock can be either:
– Divide-by-4 clock
– Divide-by-1 (PLL) clock
The low-power mode can be either:
– Enabled
– Disabled
None = For EPROM device, standard watchdog, divide-by-4
clock, and low-power modes are enabled
TMS
AFNL
Figure 12. TMS370Cx9x Family Nomenclature
Page 36
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device part numbers
Table 22 provides all the TMS370Cx9x devices available. The device part-number nomenclature is designed
to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock
and watchdog-timer options desired. Each device can only have one of the three possible watchdog-timer
options and one of the two clock options. The options to be specified pertain solely to orders involving ROM
devices.
T able 22. Device Part Numbers
DEVICE PART NUMBERS
FOR 44 PINS (LCC)
DEVICE PART NUMBERS
FOR 40 PINS (SDIP)
ББББББББ
Á
TMS370C090AFNA
TMS370C090AFNL
TMS370C090AFNT
БББББББ
Á
TMS370C090ANJA
‡
TMS370C090ANJL
‡
TMS370C090ANJT
‡
TMS370C792FNT
TMS370C792NJT
‡
SE370C792FZT
†
SE370C792JCT
†
†
System evaluators are for use only in prototype environment, and their
reliability has not been characterized.
‡
The NJ designator for the 40-pin plastic shrink DIP package was formerly
known as N2. The mechanical drawing of the NJ is identical to the N2
package and did not need to be requalified.
Page 37
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
new code release form
Figure 13 shows a sample of the new code release form.
NEW CODE RELEASE FORM
TEXAS INSTRUMENTS
TMS370 MICROCONTROLLER PRODUCTS
DATE:
T o release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:
1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)
2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.
Company Name:
Street Address:
Street Address:
City: State Zip
Contact Mr./Ms.:
Phone: ( ) Ext.:
Customer Purchase Order Number:
Customer Part Number:
Customer Application:
Customer Print Number *Yes: #
No: (Std. spec to be followed)
*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM
code processing starts.
TMS370 Device:
TI Customer ROM Number:
(provided by T exas Instruments)
CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS
OSCILLAT OR FREQUENCY
MIN TYP MAX
[] External Drive (CLKIN)
[] Crystal
[] Ceramic Resonator
Low Power Modes
[] Enabled
[] Disabled
Watchdog counter
[] Standard
[] Hard Enabled
[] Simple Counter
Clock Type
[] Standard (/4)
[] PLL (/1)
[] Supply Voltage MIN: MAX:
(std range: 4.5V to 5.5V)
NOTE:
Non ’A’ version ROM devices of the TMS370 microcontrollers will have the
“Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog
options. See the
TMS370 Family User’s Guide
(literature number SPNU127)
or the
TMS370 Family Data Manual
(literature number SPNS014B).
TEMPERATURE RANGE
[] ’L’: 0° to 70°C (standard)
[] ’A’: –40° to 85°C
[] ’T’: –40° to 105°C
PACKAGE TYPE
[] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC
[] “FN” 28-pin PLCC [] “FN” 68-pin PLCC
[] “N” 40-pin PDIP [] “NM” 64-pin PSDIP
[] “NJ” 40-pin PSDIP (formerly known as N2)
SYMBOLIZA TION BUS EXPANSION
[] TI standard symbolization
[] TI standard w/customer part number
[] Customer symbolization
(per attached spec, subject to approval)
[] YES [] NO
NON-STANDARD SPECIFICATIONS:
ALL NON-STANDARDS SPECIFICA TIONS MUST BE APPROVED BY THE TI ENGINEERING ST AFF: If the customer requires expedited production material
(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the
satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard
TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the
TI part number.
RELEASE AUTHORIZATION:
This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must
be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification
code is approved by the customer.
1. Customer: Date: 2. TI: Field Sales:
Marketing:
Prod. Eng.:
Proto. Release:
Figure 13. Sample New Code Release Form
Page 38
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
38
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Table 23. Peripheral File Frame Compilation
Table 23 is a collection of all the peripheral file frames using the ’Cx9x (provided for a quick reference).
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
Á
Á
P010
ÁÁÁ
Á
COLD
START
OSC
POWER
PF AUTO
WAIT
ÁÁ
Á
OSC FLT
FLAG
ÁÁ
Á
MC PIN
WPO
ÁÁÁ
Á
MC PIN
DATA
ÁÁ
Á
—
ÁÁÁ
Á
µP/µC
MODE
ÁÁ
Á
SCCR0
P011
—
—
—
AUTOWAIT
DISABLE
—
MEMORY
DISABLE
—
—
SCCR1
Á
Á
P012
HALT/
STANDBY
PWRDWN/
IDLE
ÁÁÁ
Á
—
BUS
STEST
CPU
STEST
ÁÁÁ
Á
—
INT1
NMI
PRIVILEGE
DISABLE
ÁÁ
Á
SCCR2
P013
to
P016
Reserved
P017
INT1
FLAG
INT1
PIN DATA
—
—
—
INT1
POLARITY
INT1
PRIORITY
INT1
ENABLE
INT1
Á
P018
БББББББББББББББББББББББББББ
ÁÁ
Á
Á
to
P019
БББББББББББББББББББББББББББ
Á
Reserved
ÁÁ
Á
P01A
BUSY
—
—
—
—
AP
W1W0
EXE
DEECTL
P01B Reserved
P01C
BUSY
VPPS
—
—
—
—
W0
EXE
EPCTL
Á
Á
P01D
to
P01F
Reserved
ÁÁ
Á
P020
Reserved
APORT1
P021
Port A Control Register 2 (must be 0)
APORT2
P022
Port A Data
ADATA
P023
Port A Direction
ADIR
Á
Á
P024
to
P02B
БББББББББББББББББББББББББББ
Á
Reserved
ÁÁ
Á
P02C
Port D Control Register 1 (must be 0)
—
—
—
DPORT1
P02D
Port D Control Register 2† (must be 0)
—
—
—
DPORT2
P02E
Port D Data
—
—
—
DDATA
P02F
Port D Direction
—
—
—
DDIR
Modes: Capture/Compare and Dual-Compare
P040
Bit 15
T1 Counter MSbyte
Bit 8
T1CNTR
P041
Bit 7
T1 Counter LSbyte
Bit 0
P042
Bit 15
Compare Register MSbyte
Bit 8
T1C
P043
Bit 7
Compare Register LSbyte
Bit 0
P044
Bit 15
Capture/Compare Register MSbyte
Bit 8
T1CC
P045
Bit 7
Capture/Compare Register LSbyte
Bit 0
P046
Bit 15
Watchdog Counter MSbyte
Bit 8
WDCNTR
P047
Bit 7
Watchdog Counter LSbyte
Bit 0
P048
Bit 7
Watchdog Reset Key
Bit 0
WDRST
†
To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Page 39
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 23. Peripheral File Frame Compilation (Continued)
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
Modes: Capture/Compare and Dual-Compare (Continued)
Á
Á
P049
ÁÁ
Á
WD OVRFL
TAP SEL
†
ÁÁÁ
Á
WD
INPUT
SELECT2
†
ÁÁ
Á
WD
INPUT
SELECT1
†
ÁÁ
Á
WD
INPUT
SELECT0
†
ÁÁÁ
Á
—
ÁÁ
Á
T1
INPUT
SELECT2
ÁÁÁ
Á
T1
INPUT
SELECT1
ÁÁ
Á
T1 INPUT
SELECT0
ÁÁ
Á
T1CTL1
P04A
WD OVRFL
RST ENA
†
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
—
—
T1 SW
RESET
T1CTL2
Mode: Dual-Compare
Á
Á
P04B
ÁÁ
Á
T1EDGE
INT FLAG
ÁÁÁ
Á
T1C2
INT FLAG
ÁÁ
Á
T1C1
INT FLAG
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
T1EDGE
INT ENA
ÁÁÁ
Á
T1C2
INT ENA
ÁÁ
Á
T1C1
INT ENA
ÁÁ
Á
T1CTL3
P04C
T1
MODE = 0
T1C1
OUT ENA
T1C2
OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
T1EDGE
POLARITY
T1CR
RST ENA
T1EDGE
DET ENA
T1CTL4
Mode: Capture/Compare
Á
Á
P04B
ÁÁ
Á
T1EDGE
INT FLAG
ÁÁÁ
Á
—
ÁÁ
Á
T1C1
INT FLAG
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
T1EDGE
INT ENA
ÁÁÁ
Á
—
ÁÁ
Á
T1C1
INT ENA
ÁÁ
Á
T1CTL3
P04C
T1
MODE = 1
T1C1
OUT ENA
—
T1C1
RST ENA
—
T1EDGE
POLARITY
—
T1EDGE
DET ENA
T1CTL4
Modes: Capture/Compare and Dual-Compare
Á
Á
P04D
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
T1EVT
DATA IN
ÁÁ
Á
T1EVT
DATA OUT
ÁÁÁ
Á
T1EVT
FUNCTION
ÁÁ
Á
T1EVT DATA
DIR
ÁÁ
Á
T1PC1
P04E
T1PWM
DATA IN
T1PWM
DATA OUT
T1PWM
FUNCTION
T1PWM
DATA DIR
T1IC/CR
DATA IN
T1IC/CR
DATA OUT
T1IC/CR
FUNCTION
T1IC/CR DATA
DIR
T1PC2
Á
Á
P04F T1 STEST
T1
PRIORITY
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁ
Á
T1PRI
P070
CONVERT
START
SAMPLE
START
REF VOLT
SELECT1
REF VOLT
SELECT0
AD INPUT
SELECT3
AD INPUT
SELECT2
AD INPUT
SELECT1
AD INPUT SE-
LECT0
ADCTL
Á
Á
P071
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
AD READY
ÁÁÁ
Á
AD INT
FLAG
ÁÁ
Á
AD INT ENA
ÁÁ
Á
ADSTAT
P072
A-to-D Conversion Data Register
ADDATA
Á
Á
P073
to
P07C
ББББББББББББББББББББББББББ
Á
Reserved
ÁÁ
Á
P07D
Port E Data Input Register
ADIN
P07E
Port E Input Enable Register
ADENA
Á
Á
P07F AD STEST
AD
PRIORITY
AD ESPEN
ÁÁ
Á
—
ÁÁÁ
Á
—
ÁÁ
Á
—
ÁÁÁ
Á
AD RATE
SELECT1
ÁÁ
Á
AD RATE
SELECT0
ÁÁ
Á
ADPRI
†
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
Page 40
TMS370Cx9x
8-BIT MICROCONTROLLER
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range V
CC
(see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, All pins except MC –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (V
I
< 0 or V
I
> V
CC)
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current per buffer, IO (VO = 0 to VCC)‡ ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum I
CC
current 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum I
SS
current – 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA:L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A version – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T version – 40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer
can affect the levels on other buffers.
NOTE 1: Unless otherwise noted, all voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage (see Note 1) 4.5 5 5.5
V
CC
RAM data-retention supply voltage (see Note 2) 3 5.5
V
V
CC3
Analog supply voltage (see Note 1) 3 5.5 V
V
SS3
Analog supply ground – 0.3 0 0.3 V
p
All pins except MC V
SS
0.8 V
VILLow-level input voltage
MC, normal operation V
SS
0.3 V
All pins except MC, XTAL2/CLKIN, and
RESET
2 V
CC
V
IH
High-level input voltage
XTAL2/CLKIN
0.8 V
CC
V
CC
V
RESET 0.7 V
CC
V
CC
EEPROM write protect override (WPO) 11.7 12 13
V
MC
MC (mode control) voltage
EPROM programming voltage (VPP)
13 13.2 13.5
V
Microcomputer V
SS
0.3
L version 0 70
T
A
Operating free-air temperature
A version
– 40 85
°C
T version – 40 105
NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.
2. RESET
must be externally activated when VCC or SYSCLK is out of the recommended operating range.
Page 41
TMS370Cx9x
8-BIT MICROCONTROLLER
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41
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OL
Low-level output voltage IOL = 1.4 mA 0.4 V
p
IOH = –50 µA 0.9 V
CC
VOHHigh-level output voltage
IOH = –2 mA 2.4
V
0 V < VI ≤ 0.3 V 10
p
MC
0.3 V < VI ≤ 13 V 650
µ
A
IIInput current
12 V ≤ VI ≤ 13 V See Note 3 50 mA
I/O pins 0 V ≤ VI ≤ V
CC
± 10 µA
I
OL
Low-level output current VOL = 0.4 V 1.4 mA
p
VOH = 0.9 V
CC
– 50 µA
IOHHigh-level output current
VOH = 2.4 V – 2 mA
SYSCLK
= 5 MHz
See Notes 4 and 5
30
45
Supply current (operating mode)
y(g)
=
SYSCLK
= 3 MHz
See Notes 4 and 5
2030mA
OSC POWER bit = 0 (see Note 6)
SYSCLK
= 0.5 MHz
See Notes 4 and 5
7
11
SYSCLK = 5 MHz See Notes 4 and 5 10 17
I
CC
Supply current (STANDBY mode)
SYSCLK = 3 MHz See Notes 4 and 5 8 11
mA
OSC POWER bit = 0 (see Note 7)
SYSCLK = 0.5 MHz See Notes 4 and 5 2 3.5
Supply current (STANDBY mode)
SYSCLK = 3 MHz See Notes 4 and 5 6 8.6
y( )
OSC POWER bit = 1 (see Note 8)
SYSCLK = 0.5 MHz See Notes 4 and 5 2 3
mA
Supply current (HALT mode) XTAL2/CLKIN < 0.2 V See Note 4 2 30 µA
NOTES: 3. Input current IPP is a maximum of 50 mA only when programming EPROM.
4. In single chip mode, ports are configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC – 0.2V .
5. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current
can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance
in pF).
6. Maximum operating current for TMS370Cx9x = 7.6 (SYSCLK) + 7 mA.
7. Maximum standby current for TMS370Cx9x = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).
8. Maximum standby current for TMS370Cx9x = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit =1, only valid up to 3-MHz SYSCLK).
Page 42
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
External
Clock Signal
XTAL1XTAL2/CLKIN
C2
(see Note B)
C1
(see Note B)
Crystal/Ceramic
Resonator
(see Note A)
XTAL1XTAL2/CLKIN
C3
(see Note B)
NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.
B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic
resonators.
Figure 14. Recommended Crystal/Clock Connections
1.2 kΩ
20 pF
V
O
Load Voltage
Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V
Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V
NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN
driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
Figure 15. Typical Output Load Circuit (see Note A)
V
CC
GND
300 Ω
20 Ω
I/O
Pin Data
Output
Enable
V
CC
GND
INT1
6 kΩ
20 Ω
30 Ω
Figure 16. T yplcal Buffer Circuitry
Page 43
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A Address IE Initial
AR Array PGM Program
B Byte R Read
CI XTAL2/CLKIN SC SYSCLK
D Data W Write
E EDS WT WAIT
FE Final
Lowercase subscripts and their meanings are:
c cycle time (period) r rise time
d delay time su setup time
f fall time v valid time
h hold time w pulse duration (width)
The following additional letters are used with these meanings:
H High
L Low
V Valid
Z High impedance
All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18.
0.8 V (Low)
2 V (High)
0.8 V (Low)
0.8 VCC V (High)
Figure 17. XTAL2/CLKIN Measurement Points Figure 18. General Measurement Points
Page 44
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
external clocking requirements for clock divided by 4
†
(see Figure 19)
NO. PARAMETER MIN MAX UNIT
1 t
w(Cl)
Pulse duration, XTAL2/CLKIN (see Note 9) 20 ns
2 t
r(Cl)
Rise time, XTAL2/CLKIN 30 ns
3 t
f(CI)
Fall time, XTAL2/CLKIN 30 ns
4 t
d(CIH-SCL)
Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns
CLKIN Crystal operating frequency 2 20 MHz
SYSCLK System clock
‡
0.5 5 MHz
†
For VIL and VIH, refer to recommended operating conditions.
‡
SYSCLK = CLKIN/4
NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a
low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
3
2
1
4
SYSCLK
Figure 19. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL)
†
(see Figure 20)
NO. PARAMETER MIN MAX UNIT
1 t
w(Cl)
Pulse duration, XTAL2/CLKIN (see Note 9) 20 ns
2 t
r(Cl)
Rise time, XTAL2/CLKIN 30 ns
3 t
f(CI)
Fall time, XTAL2/CLKIN 30 ns
4 t
d(CIH-SCH)
Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns
CLKIN Crystal operating frequency 2 5 MHz
SYSCLK System clock
§
2 5 MHz
†
For VIL and VIH, refer to recommended operating conditions.
§
SYSCLK = CLKIN/1
NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a
low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
3
2
1
4
SYSCLK
Figure 20. External Clock Timing for Divide-by-1
Page 45
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
switching characteristics and timing requirements
†
NO. PARAMETER MIN MAX UNIT
Divide-by-4 200 2000 ns
5
tcCycle time, SYSCLK
Divide-by-1 (PLL) 200 500 ns
6 t
w(SCL)
Pulse duration, SYSCLK low 0.5tc – 20 0.5t
c
ns
7 t
w(SCH)
Pulse duration, SYSCLK high 0.5tc0.5tc + 20 ns
†
tc = system-clock cycle time = 1/SYSCLK
5
6
7
SYSCLK
Figure 21. Switching Characteristics
general purpose output signal switching time requirements
MIN NOM MAX UNIT
trRise time 30 ns
tfFall time 30 ns
t
f
t
r
Figure 22. Signal Switching Timing
recommended EEPROM timing requirements for programming
MIN MAX UNIT
t
w(PGM)B
Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms
t
w(PGM)AR
Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms
Page 46
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
recommended EPROM operating conditions for programming
MIN NOM MAX UNIT
V
CC
Supply voltage 4.75 5.5 6 V
V
PP
Supply voltage at MC pin 13 13.2 13.5 V
I
PP
Supply current at MC pin during programming (VPP = 13 V) 30 50 mA
Divide-by-4 0.5 5
SYSCLK
System clock
Divide-by-1 2 5
MH
z
recommended EPROM timing requirements for programming
MIN NOM MAX UNIT
t
w(EPGM)
Pulse duration, programming signal (see Note 10) 0.40 0.50 3 ms
NOTE 10: Programming pulse is active when both EXE (EPCTL.0) and V
PPS
(EPCTL.6) are set.
Page 47
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3
The ADC3 has a separate power bus for its analog circuitry . These pins are referred to as V
CC3
and V
SS3
. The
purpose is to enhance ADC3 performance by preventing digital switching noise of the logic circuitry that can
be present on V
SS
and VCC from coupling into the ADC3 analog stage. All ADC3 specifications are given with
respect to V
SS3
unless otherwise noted.
Resolution 8-bits (256 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic Yes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode 00h to FFh (00 for VI ≤ V
SS3
≤; FF for VI ≤ V
ref
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion time (excluding sample time) 164 t
c
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
pp
4.5 5 5.5
V
CC3
Analog suppl
y v
oltage
VCC–0.3 VCC+0.3
V
V
SS3
Analog ground VSS–0.3 VSS+0.3 V
V
ref
Non-V
CC3
reference
†
2.5 V
CC3VCC3
+ 0.1 V
Analog input for conversion V
SS3
V
ref
V
†
V
ref
must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.
operating characteristics over recommended ranges operating conditions
PARAMETER MIN MAX UNIT
Absolute accuracy
‡
V
CC3
= 5.5 V V
rerf
= 5.1 V ±1.5 LSB
Differential/integral linearity error
‡§
V
CC3
= 5.5 V V
rerf
= 5.1 V ±0.9 LSB
pp
Converting 2 mA
I
CC3
Analog supply current
Nonconverting 5 µA
I
I
Input current, AN0–AN14 0 V ≤ VI ≤ 5.5 V 2 µA
I
ref
Input charge current 1 mA
p
SYSCLK ≤ 3 MHz 24 kΩ
Z
ref
Source impedance of V
ref
3 MHz < SYSCLK ≤ 5 MHz 10 kΩ
‡
Absolute resolution = 20 mV. At V
ref
= 5 V, this is one LSB. As V
ref
decreases, LSB size decreases; therefore, the absolute accuracy and
differential/integral linearity errors in terms of LSBs increase.
§
Excluding quantization error of 1/2 LSB
Page 48
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog-to-digital converter 3 (continued)
The ADC3 module allows complete freedom in design of the sources for the analog inputs. The period of the
sample time is user-defined so that the high-impedance sources can be accommodated without penalty to the
low-impedance sources. The sample period begins when the SAMPLE ST ART bit of the ADC3 control register
(ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT ST ART,
ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE ST ART and CONVERT ST ART bits,
signaling that a conversion has started and that the analog signal can be removed.
analog timing requirements
†
MIN MAX UNIT
t
su(S)
Setup time, analog to sample command 0 ns
t
h(AN)
Hold time, analog input from start of conversion
†
(N+2)t
c
ns
t
w(C)
Conversion time
†
(10N + 4) t
c
ns
t
w(S)
Pulse duration, sample time per kilohm of source impedance
‡
1 µs/kΩ
†
N = 16, 8, 4, or 2 upon selected conversion rate.
‡
The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time of 1µs.
Analog In
Sample Time
Convert Time
Analog In Stable
t
h(AN)
t
w(S)
t
su(S)
t
su(S)
t
w(C)
Figure 23. Analog Timing
Page 49
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table 24 is designed to aid the user in referencing a device part number to a mechanical drawing. The table
shows a cross-reference of the device part number to the TMS370 generic package name and the associated
mechanical drawing by drawing number and name.
Table 24. TMS370Cx9x Family Package Type and Mechanical Cross-Reference
PKG TYPE
(mil pin spacing)
TMS370 GENERIC NAME
PKG TYPE NO. AND
MECHANICAL NAME
DEVICE PART NUMBERS
ÁÁÁÁ
Á
ÁÁÁÁ
Á
FN – 44 pin
(50-mil pin spacing)
БББББББББ
Á
БББББББББ
Á
PLASTIC LEADED CHIP CARRIER
(PLCC)
ББББББББББ
Á
ББББББББББ
Á
FN(S-PQCC-J**) PLASTIC J-LEADED
CHIP CARRIER
БББББ
Á
БББББ
Á
TMS370C090AFNA
TMS370C090AFNL
TMS370C090AFNT
TMS370C792FNT
ÁÁÁÁ
Á
FZ – 44 pin
(50-mil pin spacing)
БББББББББ
Á
CERAMIC LEADED CHIP CARRIER
(CLCC)
ББББББББББ
Á
FZ(S-CQCC-J**) J-LEADED CERAMIC
CHIP CARRIER
БББББ
Á
SE370C792FZT
JC – 40 pin
(70-mil pin spacing)
CERAMIC SHRINK DUAL-IN-LINE
PACKAGE (CSDIP)
JC(R-CDIP-T40) CERAMIC SIDE-BRAZE
DUAL-IN-LINE PACKAGE
SE370C792JCT
ÁÁÁÁ
Á
ÁÁÁÁ
Á
NJ – 40 pin
(70-mil pin spacing)
†
БББББББББ
Á
БББББББББ
Á
PLASTIC SHRINK DUAL-IN-LINE
PACKAGE (PSDIP)
ББББББББББ
Á
ББББББББББ
Á
NJ(R-PDIP-T**) PLASTIC SHRINK
DUAL-IN-LINE PACKAGE
БББББ
Á
БББББ
Á
TMS370C090ANJA
TMS370C090ANJL
TMS370C090ANJT
TMS370C792NJT
†
NJ formerly known as N2; the mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
Page 50
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84
1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF
D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
Page 51
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER
4040219/B 03/95
0.180 (4,57)
0.140 (3,55)
C
0.020 (0,51)
0.032 (0,81)
A B
A
B
0.025 (0,64) R TYP
0.026 (0,66)
0.120 (3,05)
0.155 (3,94)
0.014 (0,36)
0.120 (3,05)
0.040 (1,02) MIN
0.090 (2,29)
0.040 (1,02) 45°
A
MIN MAX
0.485
(12,32) (12,57)
0.495
0.455
(11,56)(10,92)
0.430
MAXMIN
BC
MIN MAX
0.410
(10,41) (10,92)
0.430
0.6300.6100.630 0.6550.6950.685
(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)
0.7400.6800.730 0.7650.7950.785
(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)
PINS**
28
44
52
NO. OFJEDEC
MO-087AC
MO-087AB
MO-087AA
OUTLINE
28 LEAD SHOWN
Seating Plane
(at Seating
Plane)
1426
25
19
18
12
11
5
0.050 (1,27)
0.9300.9100.930 0.9550.9950.985
(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)
68MO-087AD
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
Page 52
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
JC (R-CDIP-T40) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
4040223-2/B 04/95
0.175 (4,46) TYP
0.020 (0,51)
0.012 (0,31)
0.016 (0,41)
Seating Plane
0.610 (15,49)
1
0.032 (0,81) TYP
0.009 (0,23)
0.590 (14,99)
1.335 (33,91)
1.325 (33,66)
1.386 (35,20)
1.414 (35,92)
0.600 (15,24)
0.580 (14,73)
0.040 (1,02)
0.060 (1,52)
20
40 21
0.093 (2,38)
0.077 (1,96)
0.070 (1,78)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
Page 53
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
NJ (R-PDIP-T**) PLASTIC SHRINK DUAL-IN-LINE PACKAGE
4040034/B 04/95
40 PIN SHOWN
2.031
54
(51,60)
40
1.425
(36,20)
DIM
A MAX
PINS **
21
20
0.200 (5,08) MAX
0.560 (14,22) MAX
0.125 (3,18) MIN
Seating Plane
0.010 (0,25) NOM
0.600 (15,24)
A
40
1
0.048 (1,216)
0.032 (0,816)
0.014 (0,36)
0.022 (0,56)
0.020 (0,51) MIN
0°–15°
M
0.010 (0,25)
0.070 (1,78)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Page 54
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