Datasheet S3C9424, S3C9428, S3P9428 Datasheet (Samsung)

S3C9424/C9428/P9428 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM87RI PRODUCT FAMILY

Samsung’s SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.

A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.

S3C9424/C9428/P9428 MICROCONTROLLER

The S3C9424/C9428/P9428 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87Ri CPU core. The S3C9424/C9428/P9428 is a versatile microcontroller, with its
A/D converter, SIO, IIC and a zero-crossing detection capability it can be used in a wide range of general
purpose applications.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9424/C9428/P9428 have 4K-byte or
8K-byte of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM.

Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:

• Four configurable I/O ports (24 pins)

• Nine interrupt sources with one vector and one interrupt level

• Two 8-bit timer/counter with various operating modes

• Analog to digital converter with 12 input channels and 10-bit resolution

• One synchronous SIO module

• One IIC module

• Two 12-bit PWM output

The S3C9424/C9428/P9428 microcontroller is ideal for use in a wide range of electronic applications requiring
simple timer/counter, PWM, ADC, SIO, IIC, ZCD and capture functions. S3C9424/C9428/P9428 is available in a
28/32-pin SOP and a 30-pin SDIP package.

OTP

The S3P9428 is an OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. The
S3P9428 has on-chip 8-K-byte one-time-programmable EPROM instead of masked ROM. The S3P9428 is fully
compatible with the S3C9424/C9428, in function, in D.C. electrical characteristics and in pin configuration.

1-1

PRODUCT OVERVIEW S3C9424/C9428/P9428

FEATURES

CPU

• SAM87RI CPU core

Memory

• 208-byte general purpose register area (RAM)

• 4K/8K byte internal program memory (ROM)

Instruction Set

• 41 instructions

• The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction

Instruction Execution Time

• 375 ns at 16 MHz fosc(minimum)

Interrupts

• 9 interrupt sources and 1 vector

• One interrupt level

General I/O

• Four I/O ports (total 24pins)

Timer/Counters

• One 8-bit basic timer for watchdog function

• One 8-bit timer/counter with three operating
mode

• One 8-bit timer/counter

PWM module

• 12-bit PWM 2-ch (Max: 250KHz)

• 6-bit base + 6-bit extension frame

• One 8-bit timer/counter

A/D Converter

• 12 analog input pins

• 10-bit conversion resolution

Buzzer Frequency Range

• 200 Hz to 20 kHz signal can be generated

Oscillator Freqeuncy

• 1-MHz to 16-MHz external crystal oscillator
Maximum 16-MHz CPU clock

• RC: 4MHz(typ)

• Bit programmable ports

Serial I/O

• One synchronous serial I/O module

• Selectable transmit and receive rates

Multi-Master IIC-Bus

• Serial peripheral interface

Zero-Crossing Detection Circuit

• Zero crossing detection circuit that generates a
digital signal in synchronism with an AC signal
input

Built-in reset Circuit (LVD)

• Low voltage detector for safe reset

Operating Temperature Range

• – 40°C to + 85°C

Operating Voltage Range

• 3.0 V to 5.5 V (LVD)

• 1.8 V to 5.5 V (No LVD)

OTP Interface Protocol Spec

• Serial OTP

Package Types

• S3C9424/C9428
32-pin SOP-450 (3V LVD)
30-pin SDIP-400 (3V LVD)
28-pin SOP-375

1-2

S3C9424/C9428/P9428 PRODUCT OVERVIEW

BLOCK DIAGRAM

X

X

OUT

T0 (CAP)

T0(PWM)

AD0-AD11

P1.1/BUZ

P0.0-P0.7

SCK,SO, SI, AD8-AD11

Basic
Timer

IN

OSC

Timer 0

Timer 1

ADC

BUZ

Port 0

Port I/O and Interrupt

Control

SAM87RI CPU

P1.0-P1.3

T0, BUZ, INT0, INT1

Port 1

Port 2

Port 3

ZCD

IIC

P2.0-P2.7
AD0-AD7

P3.0-P3.3

ZCD

P2.7/SCLK
P2.6/SDAT

P0.7/PWM0
P1.3/PWM1

PWM

4K/8K ROM

Register File

Figure 1-1. Block Diagram

208-Byte

SIO

P0.0/SCK
P0.1/SO
P0.2/SI

1-3

PRODUCT OVERVIEW S3C9424/C9428/P9428

PIN ASSIGNMENTS

VSS

XIN

XOUT

TEST

P0.1/SO

P0.0/SCK

RESET

P3.0
P3.2

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5

AVSS

1
2
3
4
5
6
7

S3C9424/C9428

8
9
10
11
12
13
14
15
16

32-SOP

(Top View)

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VDD

P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0

P3.1
P3.3

P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT

AVREF

Figure 1-2. Pin Assignment Diagram (32-Pin SOP Package)

1-4

S3C9424/C9428/P9428 PRODUCT OVERVIEW

PIN ASSIGNMENTS (Continued)

VSS

XIN

XOUT

TEST

P0.1/SO

P0.0/SCK

RESETRESET

P3.0

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5

AVSS

1
2
3
4
5
6

S3C9424/C9428

7
8
9
10
11
12
13
14
15

30-SDIP

(Top View)

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

VDD

P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0

P3.1

P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT

AVREF

Figure 1-3. Pin Assignment Diagram (30-Pin SDIP Package)

VSS

XIN

XOUT

TEST

P0.1/SO

P0.0/SCK

RESETRESET

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5

AVSS

1
2
3
4
5
6

S3C9424/C9428

7
8
9
10
11
12
13
14

28-SOP

(Top View)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VDD

P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT

AVREF

Figure 1-4. Pin Assignment Diagram (28-Pin SOP Package)

1-5

PRODUCT OVERVIEW S3C9424/C9428/P9428

PIN DESCRIPTIONS

Table 1-1. S3C9424/C9428/P9428 Pin Descriptions

Pin

Names

P0.0-P0.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-

P1.0-P1.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-

P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-

Pin

Type

Pin Description Pin

pull, open-drain output. Pull-up resistors are assignable by
software.

pull output.
Pull-up resistors are assignable by software. Port 1 pins can
also be used as alternative functions.

Share

Type

E

Pins

SCK,SO,SI

, CLO,

E-1

AD8-AD11

D T0/ZCD

BUZ
INT0

INT1

E-1 AD0-AD7
pull, open drain output. Pull up resistors are assignable by
software. Port 2 can also be used as external interrupt, A/D
input.

P3.0-P3.3 O Push-pull or open-drain output port.

E-2 –
Pull-up resistors are assignable by software.

XIN, X

OUT

RESET

TEST I Test signal input pin (for factory use only: must be connected

– Crystal/ceramic, or RC oscillator signal for system clock. – –

I

System RESET signal input pin.

B –

– –

to VSS)

AV

REF

VDD, V

, AV

SS

SS

– A/D converter reference voltage input and ground – –
– Voltage input pin and ground – –

SCK I/O Serial interface clock input or output E P0.0
SO O Serial data output E P0.1
SI I Serial data output E P0.2
CLO O System clock output port E P0.3
SCLK

SDAT

I/O IIC CLOCK

IIC DATA

E-1 P2.7

P2.6
BUZ O 200 Hz-20 kHz frequency output for buzzer sound. D P1.1
ZCD I Zero crossing detector input D P1.0
T0 I/O Timer 0 capture input or 10-bit PWM output D P1.0
INT0

INT1
PWM0

PWM1

I External interrupt input D P1.2

P1.3

O 12-bit PWM output E-1

D

P0.7

P1.3
AD0-AD11 I A/D converter input E-1 P2.0-P2.7

P0.4-P0.7

1-6

S3C9424/C9428/P9428 PRODUCT OVERVIEW

PIN CIRCUITS

VDD

P-Channel

In

N-Channel

Figure 1-5. Pin Circuit Type A

VDD

Pull-Up
Resistor

In

Data

Output

DIsable

Resistor

Enable

Output

DIsable

VDD

Figure 1-7. Pin Circuit Type C

VDD

Pull-up
Resistor

P-Channel

Data

Circuit

Type C

P-Channel

Out

N-Channel

I/O

Figure 1-6. Pin Circuit Type B

Data

Figure 1-8. Pin Circuit Type D

1-7

PRODUCT OVERVIEW S3C9424/C9428/P9428

V

DD

DD

V

47K

VDD

PNE

Pull-up

DD

V

Resistor

PNE

Data

Output

Disable

Data

Input

Figure 1-9. Pin Circuit Type E

PNE

V

DD

P-CH

N-CH

P-CH

V

DD

Pull-up
Enable

I/O

Pull-up
Resistor

Pull-up
Enable

I/O

Data

Output

Disable

Pull-up
Enable

Out

Figure 1-11. Pin Circuit Type E-2

Output

Disable

Analog Input

1-8

N-CH

Input

Figure 1-10. Pin Circuit Type E-1

S3C9424/C9428/P9428 ELECTRICAL DATA

16 ELECTRICAL DATA

OVERVIEW

In this section, the following S3C9424/C9428/P9428 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings

— D.C. electrical characteristics
— A.C. electrical characteristics
— Operating Voltage Range
— Schmitt trigger input characteristics
— Oscillator characteristics
— Oscillation stabilization time
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET

— Power-on RESET circuit characteristics
— A/D converter electrical characteristics
— Zero-crossing detector
— Zero Crossing Waveform Diagram

16-1

ELECTRICAL DATA S3C9424/C9428/P9428

Table 16-1. Absolute Maximum Ratings

(TA = 25°C)

Parameter Symbol Conditions Rating Unit

Supply voltage
Input voltage
Output voltage
Output current

V

DD

I

V

V

OH

I

O

All input ports
All output ports
One I/O pin active – 25 mA

– – 0.3 to + 6.5 V

– 0.3 to V

DD

+ 0.3

– 0.3 to VDD + 0.3

V
V

high All I/O pins active – 80
Output current

I

OL

One I/O pin active + 30 mA

low Total pin current for ports 1, 2, 3 + 100

Total pin current for ports 0 + 200

Operating

T

A

– – 40 to + 85

°

C

temperature
Storage

T

STG

– – 65 to + 150

°

C

temperature

16-2

S3C9424/C9428/P9428 ELECTRICAL DATA

Table 16-2. D.C. Electrical Characteristics(30SDIP, 32SOP)

(T

= – 40°C to + 85°C, VDD = 3.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input high
voltage

Input low
voltage

Output high
voltage

Output low
voltage

Input high
leakage current

Input low
leakage current

Output high

V

V
V

V
V

V

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

IH1

IH3
IL1

IL2
OH

OL

Ports 0, 1, 2 and

RESET

X

and X

IN

OUT

Ports 0, 1, 2 and

RESET

X

and X

IN

OUT

IOH = – 10 mA
ports 0-3

IOL = 25 mA
port 0-3

All input pins except
I

LIH2

XIN, X

OUT

All input pins except
I

and RESET

LIL2

XIN, X

OUT

All output pins

VDD= 3.0 to 5.5 V 0.8 V

VDD – 0.1

VDD= 3.0 to 5.5 V

VDD= 4.5 to 5.5 V V

VDD= 4.5 to 5.5 V

VIN = V

VIN = V

DD

DD

VIN = 0 V

– –

DD

– 0.4 2.0 V

– – 1

– – – 1

VIN = 0 V
V

OUT

= V

DD

– – 2

DD

–

– 1.5 VDD –

0.4

V

DD

0.2 V

DD

0.1
– V

20

– 20

V

V

µA

µA

µA

leakage current
Output low

I

LOL

All output pins

V

OUT

= 0 V

– – – 2

µA

leakage current
Pull-up resistor

Supply current

R

I

DD1

VIN = 0 V Port 0-2 VDD = 5 V

P

RESET

RUN mode 16-MHz

VDD = 5 V
VDD = 4.5 to 5.5 V

30 47 70

100 200 350

– 11 20 mA

KΩ

CPU clock
4-MHz CPU clock

VDD = 3 V

1.5 4

I

DD2

Idle mode 16-MHz
CPU clock

4-MHz CPU clock

I

DD3

NOTE: D.C. electrical values for Supply current (I

resisters, output port drive current, ZCD and ADC.

Stop mode

VDD = 4.5 to 5.5 V

VDD = 3.3 V
VDD = 4.5 to 5.5 V
VDD = 3.3 V

to I

DD1

DD3

– 3 8

0.5 2

– 65 100

45 80

) do not include current drawn through internal pull-up

µA

16-3

ELECTRICAL DATA S3C9424/C9428/P9428

Table 16-3. D.C. Electrical Characteristics (28SOP)

(T

= – 40°C to + 85°C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input high
voltage

Input low
voltage

Output high
voltage

Output low
voltage

Input high
leakage current

Input low
leakage current

Output high

V

V

V

V

V

V

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

IH1

IH3

IL1

IL2

OH

OL

Ports 0, 1, 2 and

RESET

X

and X

IN

OUT

Ports 0, 1, 2 and

RESET

X

and X

IN

OUT

IOH = – 10 mA
ports 0-3

IOL = 25 mA
port 0-3

All input pins except
I

LIH2

XIN, X

OUT

All input pins except
I

and RESET

LIL2

XIN, X

OUT

All output pins

VDD= 1.8 to 5.5 V 0.8 V

VDD – 0.1

VDD= 1.8 to 5.5 V

VDD= 4.5 to 5.5 V V

VDD= 4.5 to 5.5 V

VIN = V

VIN = V

DD

DD

VIN = 0 V

– –

DD

– 0.4 2.0 V

– – 1

– – – 1

VIN = 0 V
V

OUT

= V

DD

– – 2

DD

–

– 1.0 VDD –

0.4

V

DD

0.2 V

DD

0.1
– V

20

– 20

V

V

µA

µA

µA

leakage current
Output low

I

LOL

All output pins

V

OUT

= 0 V

– – – 2

µA

leakage current
Pull-up resistor

Supply current

R

I

DD1

VIN = 0 V Port 0-2 VDD = 5 V

P

RESET

RUN mode 16-MHz

VDD = 5 V
VDD = 4.5 to 5.5 V

30 47 70

100 200 350

– 11 20 mA

KΩ

CPU clock
3-MHz CPU clock

VDD = 1.8 to 2.2 V

1 3

I

DD2

Idle mode 16-MHz
CPU clock

3-MHz CPU clock

I

DD3

NOTE: D.C. electrical values for Supply current (I

resisters, output port drive current, ZCD and ADC.

16-4

Stop mode

DD1

VDD = 4.5 to 5.5 V

VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V
VDD = 3 V
VDD = 1.8 to 2.2 V

to I

) do not include current drawn through internal pull-up

DD3

– 3 9

0.3 1.0

– 0.1 5

µA

S3C9424/C9428/P9428 ELECTRICAL DATA

Table 16-4. A.C. Electrical Characteristics

(T

= –40°C to + 85°C, V

A

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

t

Interrupt input
high, low width

RESET input
low width

INTH

t

INTL

t

RSL

–

,

Port 1v(INT0, INT1)
V

= 5V ± 10%

DD

Input
V

= 5V ± 10%

DD

tINTL tINTH

tRSL

– 200 – ns

– 1 – us

1/tCPU

0.8 VDD

0.2 VDD

NOTE: The unit tcpu means one CPU clock period.

Figure 16-1. Input Timing Measurement Points

16-5

ELECTRICAL DATA S3C9424/C9428/P9428

CPU Clock

16MHz

8MHz

4MHz
3MHz
2MHz
1MHz

1 2 3 4 5 6 72.7 5.5

1.8 4.5
Supply Voltage (V)

Figure 16-2. Operating Voltage Range (KS86C4204/C4208)

VOUT

VDD

A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD

VSS

A

0.3 VDD

B C

D

0.7 VDD

VIN

Figure 16-3. Schimtt Trigger Input Characteristic Diagram

16-6

S3C9424/C9428/P9428 ELECTRICAL DATA

Table 16-5. Oscillator Characteristics (30SDIP, 32SOP)

(TA = – 40°C to + 85°C)

Oscillator Clock Circuit Test Condition Min Typ Max Unit

Main crystal or
ceramic

External clock
(Main system)

RC oscillator

XIN XOUT

C1 C2

XIN XOUT

XIN XOUT

R

V

= 4.5 to 5.5 V

DD

V

= 3.0 to 4.5 V

DD

V

= 4.5 to 5.5 V

DD

V

= 3.0 to 4.5 V

DD

VDD = 4.75 to 5.25 V

Tolerance: 10%

1
1

1
1

–
–

–
–

– 4 –

16

8

16

8

Table 16-6. Oscillation Stabilization Time (28SOP)

(TA = – 40°C to + 85°C)

Oscillator Clock Circuit Test Condition Min Typ Max Unit

V

= 4.5 to 5.5 V

Main crystal or
ceramic

XIN XOUT

DD

V

= 2.7 to 4.5 V

DD

VDD = 1.8 to 2.7 V

1
1
1

–
–
–

16

8
3

MHz

MHz

External clock
(Main system)

RC oscillator

C1 C2

XIN XOUT

XIN XOUT

R

V

= 4.5 to 5.5 V

DD

V

= 2.7 to 4.5 V

DD

VDD = 1.8 to 2.7 V

VDD = 4.75 to 5.25 V

Tolerance: 10%

1
1
1

–
–
–

– 4 –

16

8
3

16-7

ELECTRICAL DATA S3C9424/C9428/P9428

Table 16-7. Oscillation Stabilization Time

(TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5 V)

Oscillator Test Condition Min Typ Max Unit

Main crystal fosc > 1.0 MHz – – 20 ms
Main ceramic

Oscillation stabilization occurs when VDD is equal

– – 10

to the minimum oscillator voltage range.

External clock

XIN input high and low width (tXH, tXL)

25 – 500 ns

(main system)
Oscillator

t

when released by a reset

WAIT

(1)

–

216/fosc

– ms

stabilization
wait time

NOTES:

1. fosc is the oscillator frequency.

2. The duration of the oscillator stabilization wait time, t
setting in the basic timer control register, BTCON.

t

when released by an interrupt

WAIT

(2)

, when it is released by an interrupt is determined by the

WAIT

– – –

16-8

S3C9424/C9428/P9428 ELECTRICAL DATA

Table 16-8. Data Retention Supply Voltage in Stop Mode

(TA = – 40°C to + 85°C, V

= 1.8 V to 5.5V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Data retention

V

DDDR

Stop mode 1.8 – 5.5 V

supply voltage
Data retention

I

DDDR

Stop mode; V

DDDR

= 1.8 V

– 0.1 5 µA

supply current

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

Internal RESET

VDD

RESET

~

~

Execution Of

Stop Instrction

Operation

~

~

Stop Mode

Data Retention Mode

VDDDR

0.2 VDD

Oscillation

Stabilization Time

Normal
Operating
Mode

0.8 VDD

tWAIT

NOTE: tWAIT is the same as 4096 x 16 x 1/fosc

Figure 16-4. Stop Mode Release Timing When Initiated by a RESETRESET

16-9

ELECTRICAL DATA S3C9424/C9428/P9428

Table 16-9. Power-on RESETRESET Circuit Characteristics

(TA = – 40 °C to + 85 °C, V

= 3.0 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Power-on reset

V

DDH

voltage high
Power-on reset

V

DDL

voltage low
Power supply

t

r

voltage rise time
Power supply

t

off

voltage off time
Power-on reset circuit

cunsumption current

NOTES:

1. 216/fx (= 6.55 ms at fx = 10 MHz)

2. Current consumed when power-on reset circuit is provided internally.

(2)

VDD

I

DDPR

VDD = 5 V ± 10%
VDD = 3.3 V

3.0 – 5.5 V

0 2.6 3.0 V

10 (1) us

0.5 s

65 100

µA

45 80

VDDH

toff tr

Figure16-5. Power-on RESETRESET Timing

VDDL

16-10

S3C9424/C9428/P9428 ELECTRICAL DATA

Table 16-10. A/D Converter Electrical Characteristics

(TA = – 40°C to + 85°C, VDD = 1.8/3.0 V to 5.5 V, VSS = 0 V)

Parameter Symbol Test Conditions Min Typ Max Unit

Total accuracy

VDD = 5.12 V

– –

± 3

LSB

CPU clock = 10 MHz
AV

= 5.12 V

REF

AVSS = 0 V

Integral linearity error ILE “ – –
Differential linearity error DLE “ – –
Offset error of top EOT “ –
Offset error of bottom EOB “ –
Conversion time

(1)

Analog input voltage
Analog input impedance
ADC reference voltage
ADC reference ground

Analog input current
ADC block
current

(2)

t
V

AV

AV

I

I

CON

IAN

R

AN
REF

ADIN

ADC

fosc = 10 MHz 20 – –

–

AV
– 2 – –
– 2.5 –

SS

AV
AV
AV
AV

REF
REF
REF
REF

–

= VDD = 5 V
= VDD = 5 V
= VDD = 3 V
= VDD = 5 V

V

SS

SS

– – 10
– 1 3 mA

– 100 500 nA

±1 ±3
±1 ± 2

–

–

0.5 1.5

Power down mode

NOTES:

1. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends.

2. I

is operating current during A/D conversion.

ADC

± 2
± 1

AV

REF

V

DD

VSS +

0.3

LSB

µs

V

MΩ

V
V

µA

Digital Output

11 1111 1111
11 1111 1110
11 1111 1101

.
.
.
.
.
.

.
00 0000 0010
00 0000 0001
00 0000 0000

Analog Input

VEOBAVSS V2 V(K-1) V(K) VEOT AVREF

Figure 16-6. Definition of DLE and ILE

16-11

ELECTRICAL DATA S3C9424/C9428/P9428

Table 16-11. Zero Crossing Detector

(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, V

= 0 V)

SS

Parameter Symbol Test Conditions Min Typ Max Unit

Zero-crossing
detection input

V

ZC

AC connection

1.0 – 3.0 Vp-p

c = 0.1 µF

voltage
Zero-crossing

detection accuracy

V

AZC

fZC = 60 Hz
(sine wave)

– –

± 150

VDD = 5 V
f

= 10 MHz

OSC

Zero-crossing
detection input

f

ZC

– 40 – 200 Hz

frequency

1/fzc

mV

AC input VAZ(P-P)

ZCINT

VAZC

Figure 16-7. Zero Crossing Waveform Diagram

16-12

S3C9424/C9428/P9428 MECHANICAL DATA

17 MECHANICAL DATA

OVERVIEW

The S3C9424/C9428 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package
(32-SOP-450A) and a 28-pin SOP package (28-SOP-375). Package dimensions are shown in Figures 17-1, 17-2,
and 17-3

#30 #16

30-SDIP-400

8.94 ± 0.2

27.88MAX

27.48 ± 0.2

0.56 ± 0.1

(1.30)

1.12 ± 0.1

#15#1

1.778

10.16

3.81 ± 0.2

5.08 MAX

3.30 ± 0.3

0.51 MIN

0-15

+ 0.1

0.25

- 0.05

NOTE: Dimensions are in millimeters.

Figure 17-1. 30-Pin SDIP Package Dimensions

17-1

MECHANICAL DATA S3C9424/C9428/P9428

0-8

#17#32

32-SOP-450A

12.00 ± 0.3

#1 #16

19.90 ± 0.2

(0.43)

NOTE: Dimensions are in millimeters

0.40 ± 0.1

Figure 17-2. 32-SOP-450A Package Dimensions

1.27

2.40 MAX

2.00 ± 0.2

0.05 MIN

8.34 ± 0.2

11.43

0.78 ± 0.2

+ 0.1

0.20

- 0.05

17-2

S3C9424/C9428/P9428 MECHANICAL DATA

8

#15#28

28-SOP-375

10.45 ± 0.3

#1 #14

18.02 MAX

17.62 ± 0.2

(0.56)

NOTE: Dimensions are in millimeters

0.41 ± 0.1

Figure 17-3. 28-SOP-375 Package Dimensions

1.27

7.70 ± 0.2

2.50 MAX

2.15 ± 0.1

0.05 MIN

0.15

9.53

0.60 ± 0.2

+ 0.10

- 0.05

17-3

S3C9424/C9428/P9428 S3P9428 OTP

18 S3P9428 OTP

OVERVIEW

The S3P9428 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

S3C9424/C9428 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.

The S3P9428 is fully compatible with the S3C9424/C9428, both in function and in pin configuration. Because of
its simple programming requirements, the S3P9428 is ideal for use as an evaluation chip for the
S3C9424/C9428.

VSS

XIN

XOUT

TEST/VPP

P0.1/SO

P0.0/SCK

RESETRESET

P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5

AVSS

Figure 18-1. Pin Assignment Diagram (30-Pin SDIP Package)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

NOTE: The bolds indicate an OTP pin name.

S3P9428

30-SDIP

(Top View)

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

VDD

P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF

18-1

S3P9428 OTP S3C9424/C9428/P9428

VSS

XIN

XOUT

TEST/VPP

P0.1/SO

P0.0/SCK

RESETRESET

P3.0

P3.2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5

AVSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

NOTE: The bolds indicate an OTP pin name.

S3P9428

32-SOP

(Top View)

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VDD

P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF

Figure 18-2. Pin Assignment Diagram (32-Pin SOP Package)

VSS

XIN

XOUT

TEST/VPP

P0.1/SO

P0.0/SCK

RESETRESET

P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5

AVSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

NOTE: The bolds indicate an OTP pin name.

S3P9428

28-SOP

(Top View)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VDD

P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF

Figure 18-3. Pin Assignment Diagram (28-Pin SOP Package)

18-2

S3C9424/C9428/P9428 S3P9428 OTP

Table 18-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P0.3 SDAT S3P9428

- 30 SDIP: 28

- 32 SOP: 30

P0.2 SCLK S3P9428

I/O Serial data pin (output when reading, Input

when writing) Input and push-pull output
port can be assigned

I Serial clock pin (input only pin)

- 30 SDIP: 29

- 32 SOP: 31

V

TEST

RESET RESET

VDD/V

SS

(TEST)

PP

VDD/V

SS

S3P9428

4 I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)

7 I Chip Initialization

I Logic power supply pin.

- 30 SDIP: 30/1

- 32 SOP: 32/1

Table 18-2. Comparison of S3P9428 and S3C9424/C9428 Features

Characteristic S3P9428 S3C9424/C9428

Program Memory 8-Kbyte EPROM 4/8-Kbyte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5) 3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
VDD = 5 V, V

(TEST) = 12.5 V

PP

Pin Configuration 30 SDIP/32 SOP/28SOP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V

(TEST) pin of the S3P9428, the EPROM programming mode is entered. The

PP
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.

Table 18-3. Operating Mode Selection Criteria

V

DD

V

pp

(TEST)

REG/MEMMEM

ADDRESS(A15-A0) R/W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

18-3