Page 1
Product Overview
Address Spaces
Addressing Modes
Control Registers
Interrupt Structure
Instruction Set
Page 2
S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.
S3C8625/C8627/C8629/P8629 MICROCONTROLLERS
S3C8625/C8627/C8629/P8629 single-chip 8-bit
microcontrollers are based on the powerful SAM8
CPU architecture. The internal register file is logically
expanded to increase the on-chip register space.
S3C8625/C8627/C8629/P8629 contain 16/32 K bytes
of on-chip program ROM.
In line with Samsung's modular design approach, the
following peripherals are integrated with the SAM8
core:
— Four programmable I/O ports (total 27 pins)
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
— One 12-bit counter with selectable clock sources,
including Hsync or Csync input
— One interval timer
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
— DDC and normal Multi-master IIC-bus
— 4-channel A/D converter (8-bit resolution)
S3C8625/C8627/C8629/P8629 are a versatile
microcontrollers which are ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, A/D converter, and multi-master
IIC-bus support with DDC. They are available in a 42pin SDIP or a 44-pin QFP package.
OTP
S3C8625/C8627/C8629 microcontrollers are also available in OTP (One Time Programmable) version named,
S3P8629. S3P8629 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of masked
ROM. S3P8629 is comparable to S3C8625/C8627/C8629, both in function and pin configuration except its ROM
size.
1-1
Page 3
PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629
FEATURES
CPU
• SAM8 CPU core
Memory
• 16/24/32-Kbyte internal program memory (ROM)
• 464-byte general-purpose register area
Instruction Set
• 78 instructions
• IDLE and STOP instructions added for
power-down modes
Instruction Execution Time
• Minimum 500 ns (with 12 MHz CPU clock)
Interrupts
• Ten interrupt sources
• Ten interrupt vectors
• Seven interrupt level
• Fast interrupt feature
Pulse Width Modulator (PWM)
• 8-bit PWM: 7-CH
Sync-Processor Block
• Vsync-I, Hsync-I, Csync-I input and Vsync-O,
Hsync-O, Clamp-O output pins
• Pseudo sync signal output
• Auto SOG detection
• Auto Hsync polarity detection
DDC Multi-Master IIC-Bus 1-Ch
• Serial Peripheral Interface
• Support for Display Data Channel
(DDC1/DDC2B/DDC2Bi/DDC2B+)
Normal Multi-Master IIC-Bus 1-Ch
• Serial Peripheral Interface
A/D Converter
• 4-channel; 8-bit resolution
General I/O
• Four I/O Ports (total 27pins)
8-Bit Basic Timer
• Programmable timer for oscillation stabilization
interval control or watchdog timer function
• Three selective internal clock frequencies
Timer/Counters
• One 8-bit Timer/Counter with several clock
sources (Capture mode)
• One 12-bit Counter with H-sync and several clock
sources
• One Interval Timer
Oscillator Frequency
• 8 MHz to 12 MHz crystal operation
• Internal Max. 12 MHz CPU clock
Operating Temperature Range
• – 40 °C to + 85 °C
Operating Voltage Range
• 4.0 V to 5.5 V
Package Types
• 42-pin SDIP, 44-pin QFP
1-2
Page 4
S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW
BLOCK DIAGRAM
X
X
OUT
PWM0
•
•
•
•
PWM6
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
MT0CAP
INT0-INT2
IN
RESET
MAIN
OSC
8-BIT
PWM
(7-CH)
Sync-
Processor
8-Bit
Counter
(Timer M0)
P0.0−P0.7/INT0−INT2
PORT 0
INTERNAL BUS
I/O PORT and INTERRUPT
CONTROL
SAM8 CPU
16/24/32-
Kbyte
ROM
P2.0−P2.7
PORT 2
464-Byte
Register File
VDD, AVREF
V
, V
SS1
TEST
PORT 1
PORT3
ADC
Multi
Master
IIC-Bus
SS2
P1.0–P1.2
P3.0–P3.7
AD0−AD3
SCL1
SDA1
12-Blt
Counter
(Timer M1)
MT1CK
Interval
Timer
(Timer M2)
Multi Master IIC-Bus
and DDC1/2B/2Bi/2B+
SCL0 SDA0
Figure 1-1. Block Diagram
1-3
Page 5
PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629
PIN ASSIGNMENTS
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
P0.4/TM0CAP
P0.5/TM1CK
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
V
DD
V
SS1
X
OUT
X
TEST
SDA0
SCL0
RESET
P1.2
P2.0/PWM0
P2.1/PWM1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN
15
16
17
18
19
20
21
S3C8625/
C8627/C8629
42-SDIP
(Top View)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
AVREF
V
SS2
P2.7/Csync-I
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
1-4
Figure 1-2. S3C8625/C8627/C8629 42-SDIP Pin Assignment
Page 6
S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW
P0.4/TM0CAP
P0.0/INT0
P0.1/INT1
P0.2/INT2
P3.3/AD3
P0.5/TM1CK
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
VDD
V
SS1
X
OUT
TEST
SDA0
XIN
P0.3
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
15
14
13
12
P2.0/PWM0
P1.2
RESET
SCL0
N.C.
39
40
S3C8625/
C8627/C8629
44-QFP
(Top View)
17
16
N.C.
P2.1/PWM1
P3.6
P3.7
37
38
19
18
P2.3/PWM3
P2.2/PWM2
P3.4
P3.5
34
35
36
22
21
20
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
33
32
31
30
29
28
27
26
25
24
23
P3.2/AD2
P3.1/AD1
P3.0 / AD0
AVREF
V
SS2
P2.7/Csync-I
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
Figure 1-3. S3C8627/C8629 44-QFP Pin Assignment
1-5
Page 7
PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629
PIN DESCRIPTIONS
Table 1-1. S3C8625/C8627/C8629/P8629 Pin Descriptions
Pin
Names
P0.0
P0.1
P0.2
P0.3
P0.4
Pin
Type
Description
I/O General-purpose, 8-bit I/O port. Shared
functions include three external interrupt
inputs and I/O for timer M0 and M1.
Selective configuration of port 0 pins to
input or output mode is supported.
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
I/O General-purpose, 3-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-
drain mode, or IIC-bus clock and data I/O.
P2.0
P2.1
P2.2
P2.3
P2.4
I/O General-purpose, 8-bit I/O port Selective
configuration of port 2 pins to input or
output mode is supported. The port 2 pin
circuits are designed to push-pull PWM
output and Csync signal input.
P2.5
P2.6
P2.7
P3.0–P3.3
P3.4–P3.7
I/O General-purpose, 8-bit I/O port Selective
configuration port 3 pins to input or output
mode is supported. Multiplexed for
alternative use as A/D converter inputs
AD0–AD3.
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
SCL0
VDD, V
SS1
AVREF, V
XIN, X
OUT
RESET
,
SS2
I
The pins are sync processor signal I/O, IIC-
I
bus clock, and data I/O.
O
O
O
I/O
I/O
– Power pins
ADC power pins
– System clock I/O pins – 14, 13 –
I System reset pin B 18 –
TEST I Factory test pin input
0V:Normal operation,5V:Factory test mode
Pin
Circuit
Type
D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
D-1
E
A
A
A
A
A
G-3
G-3
–
–
SDIP Pin
Numbers
1
2
3
4
5
6
7
8
9
10
19
20
21
22
23
24
25
26
32
35–38,
39–42
31
30
27
28
29
16
17
11, 12
34, 33
– 15 –
Shared
Functions
INT0
INT1
INT2
TM0CAP
TM1CK
SDA1
SCL1
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
AD0–AD3
–
–
1-6
Page 8
S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW
PIN CIRCUITS
V
DD
V
DD
Data or
Other
Function
Output
RESET
Data
V
SS
Output
Figure 1-4. Pin Circuit Type A
V
DD
280 K
Ω
Noise Filter
Output
Disable
Digital Input
TTL Input
or ADC Input
Figure 1-6. Pin Circuit Type D-1
V
SS
Figure 1-5. Pin Circuit Type B (RESETRESET)
1-7
Page 9
PRODUCT OVERVIEW S3C8625/C8627/C8629/P8629
V
DD
Typical
47-K
Ω
Pull-up Enable
V
DD
Data
Output
Open drain
Output Disable
V
SS
Input
Data
Open drain
Output Disable
Input
Figure 1-7. Pin Circuit Type E
V
SS
V
DD
Output
1-8
Figure 1-8. Pin Circuit Type E-1
Page 10
S3C8625/C8627/C8629/P8629 PRODUCT OVERVIEW
Output
Data
V
SS
Input
Figure 1-9. Pin Circuit Type G-3
1-9
Page 11
S3C8625/C8627/C8629/P8629 ELECTRICAL DATA
19 ELECTRICAL DATA
OVERVIEW
In this section, S3C8625/C8627/C8629 electrical characteristics are presented in tables and graphs. The
information is arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in stop mode
— Stop mode release timing when initiated by a reset
— I/O capacitance
— A/D Converter electrical characteristics
— A.C. electrical characteristics
— Input timing measurement points for P0.0–P0.2, TM0CAP, and TM1CK
— Oscillation characteristics
— Oscillation stabilization time
— Clock timing measurement points for X
— Schmitt trigger characteristics
IN
19-1
Page 12
ELECTRICAL DATA S3C8625/C8627/C8629/P8629
Table 19-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter Symbol Conditions Rating Unit
Supply voltage
V
DD
– – 0.3 to + 6.5 V
Input voltage V
Output voltage V
Output current
I
V
I1
I2
O
OH
Type C (n-channel, open-drain) – 0.3 to + 7.0 V
All port pins except V
I1
– 0.3 to VDD + 0.3
All output pins – 0.3 to VDD + 0.3 V
One I/O pin active – 10 mA
High
All I/O pins active – 60
Output current
I
OL
One I/O pin active + 30 mA
Low
Total pin current except port 3 + 100
Sync-processor I/O pins and IIC-bus
+ 150
clock and data pins
Operating
T
A
– – 40 to + 85 °
temperature
Storage
T
STG
– – 65 to + 150 °
temperature
Table 19-2. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V)
A
Parameter Symbol Conditions Min Typ Max Unit
Input High
V
IH1
All input pins except V
IH2
and V
IH3
0.8 V
DD
– V
DD
voltage
Input Low
V
IH2
V
IH3
V
IL1
X
IN
2.7 V
TTL input (HsyncI, VsyncI, and CsyncI) 2.0 V
All input pins except V
IL2
and V
IL3
– – 0.2 V
DD
DD
DD
voltage
Output High
V
IL2
V
IL3
V
OH1IOH
X
IN
1.0
TTL input (HsyncI, VsyncI, and CsyncI) 0.8
= – 8 mA; Port 3 only V
– 1.0 – – V
DD
voltage
V
OH2IOH
= – 2 mA
Ports 0, 2, ClampO, H, and VsyncO
V
OH3IOH
= – 6 mA; Port 1
C
C
V
V
19-2
Page 13
S3C8625/C8627/C8629/P8629 ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued)
(T
= – 40 °C to + 85 °C, V
A
= 4.0 V to 5.5 V)
DD
Parameter Symbol Conditions Min Typ Max Unit
Output Low
V
OL1
IOL = 8 mA; port 3 only – – 0.4 V
voltage
V
OL2
IOL = 2 mA
0.4
Port 0, 2, ClampO, H, and VsyncO
V
OL3
IOL = 6 mA
0.6
Port 1; SCL and SDA
Input High
leakage current
Input Low
leakage current
Output High
I
LIH1
I
LIH2
I
LIH3
I
LIL1
I
LIL2
I
LIL3
I
LOH1
VIN = V
All input pins except X
V
VIN = V
V
X
V
V
V
DD
,
IN
= V
IN
= 0 V; All input pins except X
IN
OUT
= 0 V; X
IN
= 0 V; X
IN
OUT
X
;
DD
OUT
X
only 2.5 6 20
;
DD
and RESET
,
= V
IN
OUT
only – 2.5 – 6 – 20
IN
DD
only – – 20
only – – – 20
X
OUT
– – 3 µA
,
IN
– – – 3 µA
– – 3 µA
leakage current
Output Low
I
LOL1
V
= 0 V – – – 3 µA
OUT
leakage current
Pull-up resistor R
L1
V
= 0 V
IN
20 47 80
kΩ
Ports 3.7–3.4
R
L2
V
= 0 V
IN
150 280 480
RESET only
Supply current
(note)
I
DD1
I
DD2
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
Idle mode; 12 MHz crystal
– 15 30 mA
5 10
C1 = C2 = 22pF
I
DD3
Stop mode 1 10 µA
NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.
19-3
Page 14
ELECTRICAL DATA S3C8625/C8627/C8629/P8629
Table 19-3. Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention
V
DDDR
Stop mode 2 – 5.5 V
supply voltage
Data retention
I
DDDR
Stop mode, V
= 2.0 V – – 5 µA
DDDR
supply current
NOTES:
1. During the oscillator stabilization wait time (t
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
), all CPU operations must be stopped.
WAIT
OSCILLATION
STABILIZATION
TIME
NORMAL
OPERATING
MODE
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
: t
NOTE
WAIT
~
~
~
~
is the same as 4,096 x x32 x 1/f
STOP MODE
DATA RETENTION
MODE
V
DDDR
OSC
RESET
OCCURS
t
.
WAIT
Figure 19-1. Stop Mode Release Timing When Initiated by a Reset
Table 19-4. Input/Output Capacitance
(T
= –40 °C to + 85 °C, V
A
DD
= 0 V)
Parameter Symbol Conditions Min Typ Max Unit
Input
capacitance
Output
C
C
IN
OUT
f = 1 MHz; unmeasured pins
are connected to V
SS
– – 10 pF
capacitance
I/O capacitance C
IO
19-4
Page 15
S3C8625/C8627/C8629/P8629 ELECTRICAL DATA
Table 19-5. A/D Converter Electrical Characteristics
(T
= – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V, VSS = 0 V)
A
Parameter Symbol Conditions Min Typ Max Unit
Resolution – 8 – bit
Total accuracy VDD = 5 V
– –
± 2
LSB
Conversion time = 5 µs
Integral linearity error ILE AV
Differential linearity error DLE AV
Offset error of top EOT
Offset error of bottom EOB
Conversion time
(1)
Analog input voltage V
Analog input impedance R
Analog reference voltage AV
Analog ground
Analog input current I
Analog block Current
(2)
AV
t
CON
IAN
AN
REF
SS
ADIN
I
ADC
(4)
= 5 V –
REF
= 0 V –
SS
± 1 ± 2
± 0.5 ± 2
8 bit conversion
34 x n/f
OSC
(3)
– AV
n=1,4,8,16
,
17 – 170
SS
– AV
– 2 1000 –
– 2.5 – V
– V
AV
= VDD = 5V – – 10
REF
AV
= VDD = 5V – 1 3 mA
REF
AV
= VDD = 3V 0.5 1.5 mA
REF
AV
= VDD = 5V
REF
When power down mode
SS
– V
100 500 nA
± 1
± 1
REF
DD
SS
µs
V
mΩ
V
V
µA
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2. I
3. f
4. VSS port shaves with the AVSS for S3C8625/C8627/C8629.
is an operating current during the A/D conversion.
ADC
is the main oscillator clock.
OSC
19-5
Page 16
ELECTRICAL DATA S3C8625/C8627/C8629/P8629
Table 19-6. A.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, V
A
= 4.0 V to 5.5V)
DD
Parameter Symbol Conditions Min Typ Max Unit
Noise Filter t
NF1H
t
NF1L
t
NF2
INT0–2, TM0CAP and
TM1CK (RC delay)
RESET only (RC delay)
300 – – ns
800 – –
t
NF1L
t
NF2
0.8 V
0.2 V
DD
DD
t
NF1H
Figure 19-2. Input Timing Measurement Points for P0.0–P0.2, TM0CAP, and TM1CK
19-6
Page 17
S3C8625/C8627/C8629/P8629 ELECTRICAL DATA
Table 19-7. Oscillation Characteristics
(TA = – 40 °C + 85 °C)
Oscillator Clock Circuit Conditions Min Typ Max Unit
Main crystal or
ceramic
C1
C2
X
X
IN
OUT
V
= 4.0 V to 5.5 V 8 – 12 MHz
DD
External clock
(main)
X
X
IN
OUT
V
= 4.0 V to 5.5 V 8 – 12 MHz
DD
NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot
select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.
Table 19-8. Oscillation Stabilization Time
(T
= – 40 °C + 85 °C, VDD = 4.0 V to 5.5 V)
A
Oscillator Test Condition Min Typ Max Unit
Crystal VDD = 4.0 V to 5.5 V – – 20 ms
Ceramic VDD = 4.0 V to 5.5V – – 10
External clock XIN input high and low level width
25 – 500 ns
(tXH, tXL)
NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after
a power-on occurs, or when Stop mode is released.
1 / f
X
t
XL
X
IN
Figure 19-3. Clock Timing Measurement Points for X
t
XH
VDD − 0.5 V
0.4 V
IN
19-7
Page 18
ELECTRICAL DATA S3C8625/C8627/C8629/P8629
V
out
V
DD
A : 0.2 V
DD
B : 0.4 V
C : 0.6 V
D : 0.8 V
V
SS
V
in
DD
DD
DD
A B C D
Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)
19-8
Page 19
S3C8625/C8627/C8629/P8629 MECHANICAL DATA
20 MECHANICAL DATA
OVERVIEW
The S3C8625/C8627/C8629 microcontroller is available in a 42-pin SDIP package (Samsung part number 42SDIP-600) and a 44-QFP package (Samsung part number 44-QFP-1010B).
14.00 ± 0.2
(1.77)
0.50 ± 0.1
42 22
42-SDIP-600
#1 21
39.10 ± 0.2
1.00 ± 0.1
1.778
15.24
5.08MAX
0.51MIN 3.50 ± 0.2
3.30 ± 0.3
+0.1
– 0.05
0.25
0 ~ 15 °
: Dimensions are in millimeters.
NOTE
Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
20-1
Page 20
MECHANICAL DATA S3C8625/C8627/C8629/P8629
13.20
10.00
± 0.3
± 0.2
0~8°
0.15
+0.10
- 0.05
±0.20
0.80
± 0.3
13.20
± 0.2
10.00
44-QFP-1010B
0.10 MAX
#44
0.80
: Dimensions are in millimeters.
NOTE
Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
#1
0.35
+0.10
- 0.05
(1.00)
0.05 MIN
2.05
± 0.10
2.30 MAX
20-2
Page 21
S3C8625/C8627/C8629/P8629 KS88P6232 OTP
21 S3P8629 OTP
OVERVIEW
The S3P8629 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C8625/C8627/C8629 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is
accessed by serial data format.
The S3P8629 is fully compatible with the S3C8625/C8627/C8629, both in function and in pin configuration.
Because of its simple programming requirements, the S3P8629 is ideal for use as an evaluation chip for the
S3C8625/C8627/C8629.
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.4/TM0CAP
P0.5/TM1CK
/P1.0/SDA1
SDAT
/P1.1/SCL1
SCLK
RESET
P2.0/PWM0
P2.1/PWM1
/TEST
V
PP
/RESET
P0.3
P0.6
P0.7
V
DD
V
SS1
X
OUT
X
SDA0
SCL0
P1.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN
15
16
17
18
19
20
21
S3P8629
42-SDIP
(Top View)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0 /AD0
AVREF
V
SS2
P2.7/Csync-I
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
The bolds indicate an OTP pin name.
NOTE:
Figure 21-1. S3P8629 Pin Assignments (42-SDIP Package)
21-1
Page 22
KS88P6232 OTP S3C8625/C8627/C8629/P8629
P0.4/TM0CAP
P0.0/INT0
P0.1/INT1
P0.2/INT2
P3.3/AD3
P0.5/TM1CK
P0.6
P0.7
SDAT/P1.0/SDA1
SCLK/P1.1/SCL1
VDD
V
SS1
X
OUT
XIN
VPP/TEST
SDA0
44
P0.3
43
42
41
40
N.C.
39
P3.7
38
P3.6
37
1
2
3
4
5
6
7
8
S3P8629
44-QFP
(Top View)
9
10
11
19
18
17
16
15
14
13
12
P3.5
36
20
P3.4
35
21
34
22
33
32
31
30
29
28
27
26
25
24
23
P3.2/AD2
P3.1/AD1
P3.0/AD0
AVREF
V
SS2
P2.7/Csync-I
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
N.C.
P2.1/PWM1
P2.0/PWM0
P1.2
RESET/RESET
SCL0
NOTE: The bolds indicate an OTP pin name.
Figure 21-2. S3P8629 Pin Assignments (44-QFP Package)
21-2
Page 23
S3C8625/C8627/C8629/P8629 KS88P6232 OTP
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P1.0 SDAT 9 (4) I/O Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P1.1 SCLK 10 (5) I Serial clock pin. Input only pin.
TEST VPP (TEST) 15 (10) I Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET RESET
V
DD/VSS1
VDD/V
SS1
18 (13) I Chip Initialization
11/12 (6/7) I Logic power supply pin. VDD should be tied to +5
V during programming.
NOTE: Parentheses indicate 44-QFP OTP pin number.
Table 21-2. Comparison of S3P8629 and S3C8625/C8627/C8629 Features
Characteristic S3P8629 S3C8625/C8627/C8629
Program Memory 32-Kbyte EPROM 16/24/32-Kbyte mask ROM
Operating Voltage (VDD) 4.0 V to 5.5 V 4.0 V to 5.5V
OTP Programming Mode VDD = 5 V, V
(TEST)=12.5V
PP
Pin Configuration 42SDIP, 44QFP 42SDIP, 44QFP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P8629, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 21-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
ADDRESS
(A15–A0)
R/W MODE
5 V 5 V 0 0000H 1 EPROM read
12.5 V 0 0000H 0 EPROM program
12.5 V 0 0000H 1 EPROM verify
12.5 V 1 0E3FH 0 EPROM read protection
NOTE: "0" means Low level; "1" means High level.
21-3
Page 24
KS88P6232 OTP S3C8625/C8627/C8629/P8629
D.C. ELECTRICAL CHARACTERISTICS
Table 21-4. D.C. Electrical Characteristics
(T
= – 40 °C to + 85 °C, V
A
Parameter Symbol Conditions Min Typ Max Unit
Input High
I
LIH1
leakage current
I
LIH2
I
LIH3
Input Low
I
LIL1
leakage current
I
LIL2
I
LIL3
Output High
I
LOH1
leakage current
Output Low
I
LOL1
leakage current
Pull-up resistor R
Supply current
(note)
R
I
DD1
I
DD2
I
DD3
L1
L2
= 4.0 V to 5.5 V)
DD
VIN = V
All input pins except X
V
VIN = V
V
X
V
V
V
V
V
DD
X
,
IN
OUT
= V
IN
= 0 V; All input pins except X
IN
OUT
= 0 V; X
IN
= 0 V; X
IN
OUT
OUT
= 0 V
IN
X
;
DD
;
DD
and RESET
,
= V
DD
= 0 V – – – 3 µA
only – – 20
OUT
X
only 2.5 6 20
IN
,
IN
only – – – 20
OUT
only – 2.5 – 6 – 20
IN
– – 3 µA
– – – 3 µA
– – 3 µA
20 47 80
kΩ
Ports 3.7–3.4
V
= 0 V
IN
150 280 480
RESET only
Operation mode; 12 MHz crystal
– 15 30 mA
C1 = C2 = 22pF
Idle mode; 12 MHz crystal
5 10
C1 = C2 = 22pF
Stop mode 1 10 µA
NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.
21-4
Loading...