Datasheet S3C821A, S3P821A Datasheet (Samsung)

S3C821A/P821A PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLES

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.

S3C821A/P821A MICROCONTROLLER

The S3C821A/P821A single-chip CMOS
microcontroller is fabricated using the highly
advanced CMOS process, based on Samsung’s
newest CPU architecture.

The S3C821A is a microcontroller with a 48-Kbyte
mask-programmable ROM embedded.

The S3P821A is a microcontroller with a 48-Kbyte
one-time-programmable ROM embedded.

Using a proven modular design approach, Samsung
engineers have successfully developed the
S3C821A/P821A by integrating the following
peripheral modules with the powerful SAM8 core:

— Six programmable I/O ports, including five 8-bit

ports and one 7-bit port, for a total of 47 pins.

— Twelve bit-programmable pins for external

interrupts.

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit

timer/counter with selectable operating modes.
— Watch timer for real time.
— 4-input A/D converter
— Serial I/O interface

The S3C821A/P821A is versatile microcontroller for
cordless phone, pager, etc. They are currently
available in 80-pin TQFP and 80-pin QFP package.

OTP

The S3P821A is an OTP (One Time Programmable) version of the S3C821A microcontroller. The S3P821A
microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of a masked ROM. The
S3P821A is comparable to the S3C821A, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C821A/P821A

FEATURES

CPU

• SAM8 CPU core

Memory

• Data memory: 1040-byte of internal register file
(Excluding LCD RAM)

• Program memory: 48-Kbyte internal program
memory (ROM)

External Interface

• 64-Kbyte external data memory area

Instruction Execution Time

• 750 ns at 8 MHz (minimum, Main oscillator)

• 183 µs at 32,768 Hz (minimum, Sub oscillator)

Interrupts

• 7 interrupt levels and 19 interrupt sources

• 19 vectors

• Fast interrupt processing feature (for one
selected interrupt level)

I/O Ports

• Five 8-bit I/O ports (P0–P4) and one 7-bit I/O
port (P5) for a total of 47 bit-programmable pins

8-Bit Basic Timer

• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function

Watch Timer

• Time internal generation: 3.91 ms, 0.5 s at
32,768 Hz

• Four frequency outputs to BUZ pin

• Clock source generation for LCD

Timers and Timer/Counters

LCD Controller/Driver

• Up to 32 segment pins

• 3, 4, and 8 common selectable

• Choice of duty cycle

• All dots can be switched on/off

• Internal resistor circuit for LCD bias

Serial Port

• One synchronous SIO

A/D Converter

• 8-bit conversion resolution × 4 channel

• 34 µs conversion time (4 MHz CPU clock, fxx/4)

Oscillation Sources

• Crystal, ceramic, or RC for main system clock

• Crystal or external oscillator for subsystem clock

• Main system clock frequency: 8 MHz

• Subsystem clock frequency: 32.768 kHz

Power-down Modes

• Main idle mode (only CPU clock stops)

• Sub idle mode

• Stop mode (main/sub system oscillation stops)

Operating Temperature Range

• – 40 °C to + 85 °C

Operating Voltage Range

• 2.0 V to 5.5 V at 32 kHz (sub clock)-6 MHz
(main clock)

• 2.2 V to 5.5 V at 8 MHz

Package Type

• 80-pin TQFP, 80-pin QFP

• One 8-bit timer/counter (Timer 0) with three
operating modes: Interval, Capture, and PWM

• One 16-bit timer/counter (Timer 1) with two 8-bit
timer/counter modes

1-2

S3C821A/P821A PRODUCT OVERVIEW

BLOCK DIAGRAM

X

X

OUT

X

X

OUT

T1CK

TA
TB

T0CK

T0/T0CAP/

T0PWM

IN

IN

RESET

MAIN

OSC

SUB

OSC

TIMER 1

A and B

TIMER 0

P0.0-P0.7

PORT 0

P1.0-P1.7

PORT 1

INTERNAL BUS

I/O PORT and INTERRUPT

CONTROL

SAM8 CPU

48-KB ROM

1-KBYTE

REGISTER

FILE

P2.0-P2.7

PORT 2

PORT 3

PORT 4

PORT 5

P3.0-P3.7

P4.0-P4.7

P5.0-P5.6

SCK

SI

SO

AV

SIO

AV

SS

REF

A/D

CONVERTER

VDD1 (INTERNAL)
VSS1 (INTERNAL)
VDD2 (EXTERNAL)

WATCH

TIMER

VSS2 (EXTERNAL)

ADC0-ADC3

Figure 1-1. S3C821A Simplified Block Diagram

LCD

DRIVER

BUZ

COM0-COM3
SEG0-SEG3/
COM4-COM7
SEG4-SEG31
VLC1

1-3

PRODUCT OVERVIEW S3C821A/P821A

PIN ASSIGNMENTS

P1.0/SEG24/AD0

P0.7/SEG23/A15

P0.6/SEG22/A14

P0.5/SEG21/A13

P0.4/SEG20/A12

P0.3/SEG19/A11

P0.2/SEG18/A10

P0.1/SEG17/A9

P0.0/SEG16/A8

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

P1.1/SEG25/AD1
P1.2/SEG26/AD2
P1.3/SEG27/AD3
P1.4/SEG28/AD4
P1.5/SEG29/AD5
P1.6/SEG30/AD6
P1.7/SEG31/AD7

P2.0/AS

P2.1/DR

VDD1(INT)

VSS1

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

80797877767574737271706968676564636261

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

AVREF

P2.6/INT2/TA

P2.7/INT3/TB

P2.5/INT1/T1CK

S3C821A

(80-TQFP)

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

AVSS

P3.4

P3.5

P3.6

P4.0/INT4

P4.1/INT5

P4.2/INT6

P4.3/INT7

60

40

P4.4/INT8

P4.5/INT9

P4.6/INT10

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG4
SEG3/COM7
SEG2/COM6
SEG1/COM5
SEG0/COM4
COM3
COM2
COM1
COM0
VDD2 (EXT)
VSS2
VLC1
P5.6
P5.5
P5.4
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
P4.7/INT11

1-4

P3.7/T0/T0PWM/T0CAP

Figure 1-2. S3C821A Pin Assignments (80-TQFP-1212)

S3C821A/P821A PRODUCT OVERVIEW

P0.6/SEG22/A14

P0.5/SEG21/A13

P0.4/SEG20/A12

P0.3/SEG19/A11

P0.2/SEG18/A10

P0.1/SEG17/A9

P0.0/SEG16/A8

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

P0.7/SEG23/A15
P1.0/SEG24/AD0
P1.1/SEG25/AD1
P1.2/SEG26/AD2
P1.3/SEG27/AD3
P1.4/SEG28/AD4
P1.5/SEG29/AD5
P1.6/SEG30/AD6
P1.7/SEG31/AD7

P2.0/AS

P2.1/DR

VDD1(INT)

VSS1

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P2.2/DW

P2.3/DM
P2.4/INT0/T0CK
P2.5/INT1/T1CK

P2.6/INT2/TA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

807978777675747372717069686766

S3C821A

(80-QFP)

65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG6
SEG5
SEG4
SEG3/COM7
SEG2/COM6
SEG1/COM5
SEG0/COM4
COM3
COM2
COM1
COM0
VDD2 (EXT)
VSS2
VLC1
P5.6
P5.5
P5.4
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
P4.7/INT11
P4.6/INT10
P4.5/INT9

252627282930313233343536373839

P3.4

P3.5

AVREF

P3.0/ADC0

P3.1/ADC1

P2.7/INT3/TB

P3.2/ADC2

AVSS

P3.3/ADC3

P3.6

P4.0/INT4

P4.1/INT5

P3.7/T0/T0PWM/T0CAP

40

P4.2/INT6

P4.3/INT7

P4.4/INT8

Figure 1-3. S3C821A Pin Assignments (80-QFP-1420C)

1-5

PRODUCT OVERVIEW S3C821A/P821A

PIN DESCRIPTIONS

Table 1-1. S3C821A Pin Descriptions

Pin

Names

Pin

Type

Pin

Description

P0.0–P0.7 I/O 4-bit-programmable I/O port.

Pull-up resistors and open-drain outputs
are software assignable. Pull-up resistors
are automatically disabled for output
pins. Configurable as LCD segments/
external interface address and data lines

P1.0–1.7 I/O 4-bit-programmable I/O port.

Pull-up resistors and open-drain outputs
are software assignable. Pull-up resistors
are automatically disabled for output
pins. Configurable as LCD segments/
external interface address and data lines

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

P3.0–P3.3

I/O 1-bit-programmable I/O port.

Pull-up resistors are software assignable,
and automatically disabled for output
pins. P2.0–P2.3 can alternately be used
as external interface lines. P2.4–P2.7 are
configurable as alternate functions or
external interrupts at falling edge with
noise filters.

I/O 1-bit-programmable I/O port.

Pull-up resistors are software assignable,
and automatically disabled for output

P3.4–P3.6

pins. P3.0–P3.3 can alternately be used
as ADC. P3.7 is configurable as an
alternate function.

P3.7

P4.0–P4.7 I/O 1-bit-programmable I/O port.

Pull-up resistors and open-drain outputs
are software assignable. Pull-up resistors
are automatically disabled for output
pins. P4.0–P4.7 are configurable as
external interrupts at a selectable edge
with noise filters.

P5.0
P5.1
P5.2
P5.3

P5.4–P5.6

I/O 1-bit-programmable I/O port.

Pull-up resistors are software assignable,
and automatically disabled for output
pins.
P5.0–P5.3 are configurable as alternate
functions. If SCK and SI are used as
input, these pins have noise filters.

Circuit

Type

Pin

Numbers

H-32 72–79

(74-80, 1)

H-32 80, 1–7

(2-9)

D-4 8 (10)

9 (11)
18 (20)
19 (21)
20 (22)
21 (23)
22 (24)
23 (25)

F-16

25–28

(27–30)

D-4

30–32

(32–34)

D-4

33 (35)

E-4 34–41

(36–43)

D-4 42 (44)

43 (45)
44 (46)
45 (47)

46–48

(48–50)

(note)

Share

Pins

SEG16/A8

–

SEG23/A15

SEG24/AD0

–

SEG31/AD7

AS

DR
DW
DM

INT0/T0CK
INT1/T1CK

INT2/TA
INT3/TB

ADC0–ADC3

T0/T0PWM/

T0CAP

INT4–INT11

SCK

SI

SO

BUZ

NOTE: Parentheses indicate pin number for 80-QFP package.

1-6

S3C821A/P821A PRODUCT OVERVIEW

Table 1-1. S3C821A Pin Descriptions (Continued)

Pin

Names

V

, V

SS1

DD1

X

X

,

OUT

IN

TEST – Chip test input pin

Pin

Type

Pin

Description

Circuit

Type

Pin

Numbers

(note)

– Power input pins for internal power block – 10, 11 (12, 13) –

– Main oscillator pins – 12, 13 (14, 15) –

– 14 (16) –

Share

Pins

Hold GND when the device is operating

XTIN, XT

RESET

OUT

– Sub oscillator pins for sub-system clock – 15, 16 (17,18) –

I

RESET signal input pin. Schmitt trigger

B 17 (19) –

input with internal pull-up resistor.

INT0–INT3 I/O External interrupts input with noise filter. D-4 20–23 (22–25) P2.4–P2.7

T0CK I/O 8Bit Timer 0 external clock input. D-4 20 (22) P2.4
T1CK I/O Timer 1/A external clock input. D-4 21 (23) P2.5

TA I/O Timer 1/A clock output D-4 22 (24) P2.6
TB I/O Timer B clock output D-4 23 (25) P2.7

T0 I/O Timer 0 clock output D-4 33 (35) P3.7

T0PWM I/O Timer 0 PWM output D-4 33 (35) P3.7

T0CAP I/O Timer 0 capture input D-4 33 (35) P3.7

ADC0–ADC3 I/O Analog input pins for A/D converts

F-16 25–28 (27–30) P3.0–P3.3

module

AV

REF

, AV

SS

– A/D converter reference voltage and

– 24, 29 (26, 31) –

ground

INT4–INT11 I/O External interrupts input with noise filter. E-4 34–41 (36–43) P4.0–P4.7

BUZ I/O Buzzer signal output D-4 45 (47) P5.3

SCK, SI, SO I/O Serial clock, serial data input, serial data

D-4 42–44 (44–46) P5.0–P5.2

output

V

SS2

V

LC1

, V

DD2

– LCD bias voltage input pins – 49 (51) –
– Power input pins for external power block – 50, 51 (52, 53) –

COM0–COM3 O LCD Common signal output H-30 52–55 (54–57) –

SEG0–SEG3

O LCD Common or Segment signal output H-31 56–59 (58–61) –

(COM4–COM7)

SEG4–SEG15 O LCD segment signal output H-29 60–71 (62–73) –

NOTE: Parentheses indicate pin number for 80-QFP package.

1-7

PRODUCT OVERVIEW S3C821A/P821A

Table 1-1. S3C821A Pin Descriptions (Continued)

Pin

Names

SEG16–

Pin

Type

Pin

Description

Circuit

Type

Pin

Numbers

I/O LCD segment signal output H-32 72–79 (74–80, 1) P0.0–P0.7

SEG23

SEG24–

I/O LCD segment signal output H-32 80, 1–7 (2–9) P1.0–P1.7

SEG31

A8–A15 I/O External interface address lines H-32 72–79 (74–80, 1) P0.0–P0.7

AD0–AD7 I/O External interface address/data lines H-32 80, 1–7 (2–9) P1.0–P1.7

AS

DR
DW
DM

NOTE: Parentheses indicate pin number for 80-QFP package.

I/O Address strobe D-4 8 (10) P2.0
I/O Data read D-4 9 (11) P2.1
I/O Data write D-4 18 (20) P2.2
I/O Data memory select D-4 19 (21) P2.3

Share

Pins

1-8

S3C821A/P821A PRODUCT OVERVIEW

PIN CIRCUITS

V

V

DD

DATA

DD

INPUT

Figure 1-4. Pin Circuit Type A

V

DD

PULL-UP
RESISTOR

RESET

P-CHANNEL

N-CHANNEL

Noise Filter

OUTPUT

DISABLE

PULL-UP

ENABLE

OUTPUT

DISABLE

V

SS

Figure 1-6. Pin Circuit Type C

V

DD

DATA

CIRCUIT

TYPE C

OUTPUT

I/O

Figure 1-5. Pin Circuit Type B

SCHMITT TRIGER

Figure 1-7. Pin Circuit Type D-4

1-9

PRODUCT OVERVIEW S3C821A/P821A

V

DD

PULL-UP

RESISTOR

PULL-UP
ENABLE

V

DD

OPEN-DRAIN EN

DATA

OUTPUT

DISABLE

PULL-UP

ENABLE

DATA

OUTPUT

DISABLE

V

SS

Figure 1-8. Pin Circuit Type E-4

CIRCUIT

TYPE C

I/O

V

DD

I/O

1-10

ADEN

ADSELECT

DATA

T0 ADC

Figure 1-9. Pin Circuit Type F-16

S3C821A/P821A PRODUCT OVERVIEW

V

LC1

V

LC1

V

LC2

V

LC3

V

LC4

V

SS

Figure 1-10. Pin Circuit Type H-29

V

LC1

V

LC2

OUTPUT

V

LC3

V

LC4

V

LC5

V

SS

Figure 1-12. Pin Circuit Type H-31

OUTPUT

V

LC5

V

SS

Figure 1-11. Pin Circuit Type H-30

OUTPUT

1-11

PRODUCT OVERVIEW S3C821A/P821A

V

DD

PULL-UP
RESISTOR

V

DD

OPEN-DRAIN EN

PULL-UP
ENABLE

DATA

LCD OUT EN

SEG

OUTPUT

DISABLE

V

SS

CIRCUIT

TYPE H-29

Figure 1-13. Pin Circuit Type H-32

I/O

1-12

S3C821A/P821A ELECTRICAL DATA

17 ELECTRICAL DATA

OVERVIEW

In this section, S3C821A electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt
— Stop mode release timing when initiated by a Reset
— I/O capacitance
— A.C. electrical characteristics
— A/D converter electrical characteristics
— Input timing for external interrupts (P4, P2.4–P2.7)

— Input timing for RESET
— Serial data transfer timing
— Oscillation characteristics
— Oscillation stabilization time
— Operating voltage range

17-1

ELECTRICAL DATA S3C821A/P821A

Table 17-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage
Input voltage
Output voltage
Output current High

V

DD

I

V

V

OH

All I/O ports

IN

O

One I/O port active – 18 mA

– – 0.3 to + 6.5 V

– 0.3 to VDD + 0.3

–

– 0.3 to VDD + 0.3

V
V

All I/O ports active – 60

Output current Low

I

OL

One I/O port active + 30 (peak value) mA

(note)

+ 15

Ports 0, 1, 2, and 3 + 100 (peak value)

(note)

+ 60

Ports 4 and 5 + 100 (peak value)

(note)

+ 60

Operating

T

A

– – 40 to + 85

°

C

temperature
Storage temperature

T

STG

– – 65 to + 150

°

C

NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × Duty .

17-2

S3C821A/P821A ELECTRICAL DATA

Table 17-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 2.0 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage

V

DD

f

OSC

= 8 MHz

2.2 – 5.5 V

(Instruction clock = 1.33 MHz)
f

OSC

= 6 MHz

2.0

(Instruction clock = 1 MHz)

Input High

V

IH1

P0 and P1

0.7 V

DD

–

V

DD

V

voltage

Input Low voltage

Output High
voltage

Output Low
voltage

Input High
leakage current

Input Low
leakage current

Output High
leakage current

Output Low
leakage current

|V

COMi|

–

DD

voltage drop

V
V
V
V
V
V

V

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

I

LOL

V

IH2
IH3

IL1
IL2
IL3

OH

OL

DC

RESET, P2, P3, P4, and P5
X

XT

,

IN

IN

P0 and P1 0 –
RESET, P2, P3, P4, and P5

X

XT

,

IN

IN

V

= 3 V; IOH = – 200 µA

DD

All output pins
V

= 3 V; IOL= 1 mA

DD

All output pins
VIN = V

DD

All input pins except those specified
below for I

VIN = V
X

,

IN

V

IN

X

OUT

= 0 V

DD

LIH2

XT

,

and XT

,

IN

OUT

All input pins except those specified
below for I

V

= 0 V

IN

X

X

,

IN

OUT

V

= V

OUT

and RESET

LIL2

XT

,

,

IN

DD

and XT

OUT

All output pins
V

= 0 V

OUT

All output pins
VDD = 2.7 V to 5.5 V
– 15 µA per common pin

0.8 V

DD

V

– 0.1 V

DD

V

DD
DD

0.3 V

0.2 V

0.1

V

DD

– 1.0

– –

– 0.4 1.0

– – 1 µA

20

– – – 1

– 20

– – 1

– – – 1

– – 120 mV

DD
DD

(i = 0–7)
|VDD–SEGx|

voltage drop

V

DS

V

= 2.7 V to 5.5 V

LCD

– 15 µA per segment pin

– – 120

(x = 0–31)

17-3

ELECTRICAL DATA S3C821A/P821A

Table 17-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, V

A

Parameter Symbol Conditions Min Typ Max

V

LC2

output

V

LC2

voltage
V

LC3

output

V

LC3

voltage
V

LC4

output

V

LC4

voltage
V

LC5

output

V

LC5

voltage
Pull-up resistors

R

L1

= 2.0 V to 5.5 V)

DD

VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
V

= V

LC1

DD

VIN = 0 V; TA = 25 °C

0.8 V

DD

0.8 V

DD

– 0.15

0.6 V

DD

0.6 V

DD

– 0.15

0.4 V

DD

0.4 V

DD

– 0.15

0.2 V

DD

0.2 V

DD

– 0.15

30 80 200

0.8 V
+ 0.15

0.6 V
+ 0.15

0.4 V
+ 0.15

0.2 V
+ 0.15

DD

DD

DD

DD

Unit

V

kΩ

VDD = 3.0 ± 10 %; Ports 0–5

LCD voltage
dividing resistor

Supply current

(note)

R

R

I

DD1

I

DD2

I

DD3

I

DD4

I

DD5

L2

LCD

VIN = 0 V; TA = 25 °C
VDD = 3.0 ± 10 %

RESET only
V

= 2.7 V to 5.5 V

LCD

TA = 25 °C
Run mode; VDD=5.0V±10%

Crystal oscillator

4.19 MHz

C1 = C2 = 22 pF
V

= 3.0 V ± 10 %

DD

4.19 MHz
Idle mode; VDD=5.0 V± 0 %
Crystal oscillator

4.19 MHz
C1 = C2 = 22 pF

V

= 3.0 V ± 10 %

DD

4.19 MHz
Run mode; VDD = 3.0 V ± 10 %

32 kHz crystal oscillator
Idle mode; VDD = 3.0 V ± 10 %

32 kHz crystal oscillator
Stop mode; V

Stop mode; V

= 5.0 V ± 10 %

DD

= 3.0 V ± 10 %

DD

200 450 800

45 65 80

kΩ

6.0 MHz – 6.0 12 mA

4.5 9.0

6.0 MHz 2.9 5.8

2.0 4.0

6.0 MHz 1.3 2.6

1.2 2.4

6.0 MHz 0.6 1.2

0.4 0.8
20 40 µA

7 14

0.5 3

0.3 2

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and
ADC.

2. I

3. I

4. I

17-4

and I

DD1

and I

DD3

is current when main system clock and subsystem clock oscillation stops.

DD5

include power consumption for subsystem clock oscillation.

DD2

are current when main system clock oscillation stops and the subsystem clock is used.

DD4

S3C821A/P821A ELECTRICAL DATA

Table 17-3. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply

V

DDDR

– 2.2 – 3.4 V

voltage
Data retention supply

I

DDDR

current
Oscillator stabilization

t

WAIT

wait time

NOTES:

1. fx

is the main oscillator frequency.

2. The duration of the oscillation stabilization time (t

V

= 1.0 V

DDDR

Stop mode
Released by RESET

Released by interrupt –

) when it is released by an interrupt is determined by

WAIT

– – 1 µA

–

216/fx

(2)

(1)

– ms
–

the setting in the basic timer control register, BTCON.

V

DD

EXECUTION OF

STOP INSTRUCTION

Interrupt Request

Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt

IDLE MODE

(Basic Timer active)

~

~

DATA RETENTION MODE

~

~

STOP MODE NORMAL

OPERATING
MODE

V

DDDR

0.8 V

DD

t

WAIT

17-5

ELECTRICAL DATA S3C821A/P821A

OSCILLATION

RESET

OCCURS

STABILIZATION

TIME

V

DD

RESET

~

~

~

~

EXECUTION OF

STOP INSTRUCTION

STOP MODE NORMAL

DATA RETENTION MODE

V

DDDR

0.2 V

DD

t

WAIT

Figure 17-2. Stop Mode Release Timing When Initiated by a RESETRESET

0.8 V

OPERATING
MODE

DD

17-6

S3C821A/P821A ELECTRICAL DATA

Table 17-4. Input/output Capacitance

(T

= – 25 °C, V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

C

C

OUT

IN

f = 1 MHz; unmeasured pins
are connected to V

SS

– – 10 pF

Input
capacitance

Output
capacitance

I/O capacitance

C

IO

Table 17-5. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

SCK cycle time

t

KCY

External SCK source 1,000 – – ns
Internal SCK source 1,000

SCK high, low
width

SI setup time to
SCK high

SI hold time to
SCK high

Output delay for
SCK to SO

Interrupt input,
high, low width

RESET input low
width

t

INTH

t

KH, tKL

t

SIK

t

KSI

t

KSO

,

t

RSL

t

External SCK source 500

t

Internal SCK source

KCY

/2–50
External SCK source 250
Internal SCK source 250

External SCK source 400
Internal SCK source 400

External SCK source – – 300 ns
Internal SCK source 250

INTL

All interrupt
V

= 3 V

DD

Input

500 700 – ns

2,000 – –

VDD = 3 V

17-7

ELECTRICAL DATA S3C821A/P821A

Table 17-6. A/D Converter Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V, VSS = 0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Resolution – 8 – bit
Total accuracy

Conversion time

(1)

Analog input voltage
Analog input impedance
Analog reference voltage
Analog ground
Analog input current

t

V

AV

AV
I

CON

IAN

R

AN

REF

ADIN

VDD = 5.12 V
AV
AV

8 bit conversion
34 x n/fxx

SS

AV

= 5.12 V

REF

= 0 V

SS

= VDD = 5V

REF

– –

17 – 170

(2)

n=1,4,8,16

,

–

AV

SS

–
– 2 1,000 –
– 2.5 –
–

V

SS

–

– – 10

± 2

AV

REF

V

DD

VSS + 0.3

LSB

µs

V

MΩ

V
V

µA

NOTES:

1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.

2. fxx is a selected system clock for peripheral hardware.

17-8

S3C821A/P821A ELECTRICAL DATA

RESET

NOTE

t

INTL

0.2 V

: The unit t

0.8 V

DD

means one CPU clock period.

CPU

DD

t

INTH

Figure 17-3. Input Timing for External Interrupts

t

RSL

0.2 V

DD

SCK

SI

SO

t

KSO

Figure 17-4. Input Timing for RESETRESET

t

KCY

t

KL

t

SIK

INPUT DATA

OUTPUT DATA

t

KSI

t

KH

0.8 V

0.2 V

DD

DD

0.8 V

0.2 V

DD
DD

Figure 17-5. Serial Data Transfer Timing

17-9

ELECTRICAL DATA S3C821A/P821A

OUT

OUT

Table 17-7. Main System Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Parameter

Crystal

Ceramic

External clock

RC

C1

C2

C1

C2

X

X

X

X

Main oscillation

IN

frequency

OUT

Main oscillation

IN

frequency

XIN input

X

X

IN

OUT

frequency

Frequency 3.0 V 0.4 – 2

X

IN

R

X

OUT

Condition (VDD)

Min Typ Max Unit

2.2 V–5.5 V 0.4 – 8 MHz

2.0 V–5.5 V 0.4 – 6

2.2 V–5.5 V 0.4 – 8

2.0 V–5.5 V 0.4 – 6

2.2 V–5.5 V 0.4 – 8

2.0 V–5.5 V 0.4 – 6

Table 17-8. Subsystem Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Parameter

Crystal

External clock

17-10

C1

C2

XT

XT

XT

XT

IN

OUT

Sub oscillation
frequency

IN

XT

IN

frequency

input

Condition (VDD)

Min Typ Max Unit

2.0 V–5.5 V 32 32.768 35 kHz

2.0 V–5.5 V 32 – 500 kHz

S3C821A/P821A ELECTRICAL DATA

Table 17-9. Main Oscillation Stabilization Time

(TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V)

Oscillator Test Condition Min Typ Max Unit

Crystal fx > 400 kHz – – 20 ms
Ceramic

Oscillation stabilization occurs when VDD is equal

– – 10 ms

to the minimum oscillator voltage range.

External clock

XIN input High and Low width (tXH, tXL)

1 / f

25 – 500 ns

x

t

XL

X

IN

Figure 17-6. Clock Timing Measurement at X

t

XH

VDD – 0.1 V

0.1 V

IN

Table 17-10. Sub Oscillation Stabilization Time

(TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V)

Oscillator Test Condition Min Typ Max Unit

Crystal – – – 10 s
External clock

XTIN input High and Low width (tXH, tXL)

1 / f

1 – 18

xt

µs

XT

t

XTL

IN

Figure 17-7. Clock Timing Measurement at XT

t

XTH

VDD – 0.1 V

0.1 V

IN

17-11

ELECTRICAL DATA S3C821A/P821A

INSTRUCTION

CLOCK

1.33 MHz

1.00 MHz

8.33 kHz

INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

1 54 6

2 3 7

2.2 5.5

SUPPLY VOLTAGE (V)

f

x

(Main oscillation

frequency)

8 MHz

6 MHz

400 kHz

Figure 17-8. Operating Voltage Range

17-12

S3C821A/P821A MECHANICAL DATA

18 MECHANICAL DATA

OVERVIEW

The S3C821A microcontroller is currently available in 80-pin QFP and TQFP package.

23.90

± 0.3

± 0.3

17.90

± 0.2

14.00

#80

0.80

#1

20.00

± 0.2

80-QFP-1420C

0.35

± 0.1

±

0.15 MAX

(0.80)

(1.00)

0−8°

0.15

0.10 MAX

± 0.20

0.80

0.05 MIN

2.65

± 0.10

3.00 MAX

+0.10

- 0.05

NOTE: Dimensions are in millimeters.

Figure 18-1. 80-Pin QFP Package Demensions

0.80

± 0.20

18-1

MECHANICAL DATA S3C821A/P821A

14.00BSC

−

12.00BSC

0
7°

0.09−0.20

80-TQFP-1212

14.00BSC

12.00BSC

0.60 ± 0.15

#80

#1

0.50

NOTE: Dimensions are in millimeters.

Figure 18-2. 80-Pin TQFP Package Demensions

0.17−0.27

±

0.08 MAX M

0.05-0.15

1.00 ± 0.05

1.20 MAX

(1.25)

18-2

S3C821A/P821A S3P821A OTP

20 S3P821A OTP

OVERVIEW

The S3P821A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C821A

microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.

The S3P821A is fully compatible with the S3C821A, both in function and in pin configuration. Because of its
simple programming requirements, the S3P821A is ideal as an evaluation chip for the S3C821A.

20-1

S3P821A OTP S3C821A/P821A

P1.0/SEG24/AD0

P0.7/SEG23/A15

P0.6/SEG22/A14

P0.5/SEG21/A13

P0.4/SEG20/A12

P0.3/SEG19/A11

P0.2/SEG18/A10

P0.1/SEG17/A9

P0.0/SEG16/A8

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

P1.1/SEG25/AD1
P1.2/SEG26/AD2
P1.3/SEG27/AD3
P1.4/SEG28/AD4
P1.5/SEG29/AD5
P1.6/SEG30/AD6
P1.7/SEG31/AD7

SDAT/P2.0/AS

SCLK/P2.1/DR

VDD1/VDD1

VSS1/VSS1

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESET/RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

80797877767574737271706968676564636261

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

AVREF

P2.6/INT2/TA

P2.7/INT3/TB

P2.5/INT1/T1CK

S3P821A

(80-TQFP)

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

AVSS

P3.4

P3.5

P3.6

P4.0/INT4

P4.1/INT5

P4.2/INT6

P4.3/INT7

60

40

P4.4/INT8

P4.5/INT9

P4.6/INT10

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG4
SEG3/COM7
SEG2/COM6
SEG1/COM5
SEG0/COM4
COM3
COM2
COM1
COM0
VDD2 (EXT)
VSS2
VLC1
P5.6
P5.5
P5.4
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
P4.7/INT11

20-2

P3.7/T0/T0PWM/T0CAP

Figure 20-1. S3P821A Pin Assignments (80-TQFP-1212 Package)

S3C821A/P821A S3P821A OTP

P0.6/SEG22/A14

P0.5/SEG21/A13

P0.4/SEG20/A12

P0.3/SEG19/A11

P0.2/SEG18/A10

P0.1/SEG17/A9

P0.0/SEG16/A8

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

P0.7/SEG23/A15
P1.0/SEG24/AD0
P1.1/SEG25/AD1
P1.2/SEG26/AD2
P1.3/SEG27/AD3
P1.4/SEG28/AD4
P1.5/SEG29/AD5
P1.6/SEG30/AD6
P1.7/SEG31/AD7

SDAT/P2.0/AS

SCLK/P2.1/DR

VDD1/VDD1

VSS1/VSS1

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESETRESET/RESET

P2.2/DW

P2.3/DM
P2.4/INT0/T0CK
P2.5/INT1/T1CK

P2.6/INT2/TA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

807978777675747372717069686766

S3P821A

(80-QFP)

65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG6
SEG5
SEG4
SEG3/COM7
SEG2/COM6
SEG1/COM5
SEG0/COM4
COM3
COM2
COM1
COM0
VDD2 (EXT)
VSS2
VLC1
P5.6
P5.5
P5.4
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
P4.7/INT11
P4.6/INT10
P4.5/INT9

252627282930313233343536373839

P3.4

P3.5

AVREF

P3.0/ADC0

P3.1/ADC1

P2.7/INT3/TB

P3.2/ADC2

AVSS

P3.3/ADC3

P3.6

P4.0/INT4

P4.1/INT5

P3.7/T0/T0PWM/T0CAP

40

P4.2/INT6

P4.3/INT7

P4.4/INT8

Figure 20-2. S3P821A Pin Assignments (80-QFP-1420C Package)

20-3

S3P821A OTP S3C821A/P821A

Table 20-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P2.0 SDAT 8 (10) I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input/push-pull output port.

P2.1 SCLK 9 (11) I/O Serial clock pin. Input only pin.

V

PP

TEST 14 (16) I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)

RESET RESET

V

DD1/VSS1

V

DD1/VSS1

17 (19) I Chip Initialization

10 (12)/11 (13) – Logic power supply pin. V

should be tied to + 5

DD

V during programming.

NOTE: ( ) means 80 QFP package.

Table 20-2. Comparison of S3P821A and S3C821A Features

Characteristic S3P821A S3C821A

Program Memory 48-K byte EPROM 48-K byte mask ROM
Operating Voltage (VDD) 2.0 V to 5.5 V 2.0 V to 5.5 V

OTP Programming Mode VDD = 5 V, V

(TEST) = 12.5 V

PP

Pin Configuration 80 QFP/80 TQFP 80 QFP/80 TQFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (TEST) pin of the S3P821A, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 20-3 below.

Table 20-3. Operating Mode Selection Criteria

V

DD

V

PP

(TEST)

REG/

MEMMEM

ADDRESS

(A15–A0)

R/W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

20-4

S3C821A/P821A S3P821A OTP

Table 20-4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 2.0 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage V

DD

f

OSC

= 8 MHz

2.2 – 5.5 V
(Instruction clock = 1.33 MHz)
f

OSC

= 6 MHz

2.0
(Instruction clock = 1 MHz)

Input High

V

IH1

P0 and P1 0.7 V

DD

– V

DD

V

voltage

Input Low voltage V

Output High
voltage

Output Low
voltage

Input High

I

leakage current

I

Input Low
leakage current

Output High

I

leakage current
Output Low

leakage current
|V

DD–COMi

|

voltage drop

V

IH2

V

IH3

V
V
V

OH

V

LIH1

LIH2

I

LIL1

I

LIL2

LOH

I

LOL

V

IL1
IL2
IL3

OL

DC

RESET, P2, P3, P4, and P5
X

XT

,

IN

IN

P0 and P1 0 – 0.3 V
RESET, P2, P3, P4, and P5

X

XT

,

IN

IN

V

= 3 V; IOH = – 200 µA

DD

All output pins
V

= 3 V; IOL= 1 mA

DD

All output pins
VIN = V

DD

All input pins except those specified
below for I

VIN = V
X

,

IN

V

IN

X

OUT

= 0 V

DD

LIH2

XT

,

and XT

,

IN

OUT

All input pins except those specified
below for I

V

= 0 V

IN

X

X

,

IN

OUT

V

= V

OUT

and RESET

LIL2

XT

,

,

IN

DD

and XT

OUT

All output pins
V

= 0 V

OUT

All output pins
VDD = 2.7 V to 5.5 V
– 15 µA per common pin

0.8 V

DD

V

– 0.1 V

DD

V

DD
DD

0.2 V

0.1

V

– 1.0 – –

DD

– 0.4 1.0

– – 1 µA

20

– – – 1

– 20

– – 1

– – – 1

– – 120 mV

DD
DD

(i = 0-7)
|VDD–

SEGx

|

voltage drop

V

DS

V

= 2.7 V to 5.5 V

LCD

– 15 µA per segment pin

– – 120

(x = 0-31)

20-5

S3P821A OTP S3C821A/P821A

Table 20-4. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, V

A

Parameter Symbol Conditions Min Typ Max

V

LC2

output

V

LC2

voltage
V

LC3

output

V

LC3

voltage
V

LC4

output

V

LC4

voltage
V

LC5

output

V

LC5

voltage
Pull-up resistors R

L1

= 2.0 V to 5.5 V)

DD

VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
V

= V

LC1

DD

VIN = 0 V; TA = 25°C

0.8 V

DD

0.8 V

DD

– 0.15

0.6 V

DD

0.6 V

DD

– 0.15

0.4 V

DD

0.4 V

DD

– 0.15

0.2 V

DD

0.2 V

DD

– 0.15

30 80 200

0.8 V
+ 0.15

0.6 V
+ 0.15

0.4 V
+ 0.15

0.2 V
+ 0.15

DD

DD

DD

DD

Unit

V

kΩ

VDD = 3.0 ± 10%; Ports 0–5

R

VIN = 0 V; TA = 25 °C

L2

300 500 800
VDD = 3.0 ± 10 %
RESET only

LCD voltage
dividing resistor

R

LCD

V

= 2.7 V to 5.5 V

LCD

45 65 80

kΩ

TA = 25 °C

Supply current

(note)

I

DD1

Run mode; VDD=5.0V±10%
Crystal oscillator

6.0 MHz – 6.0 12 mA

4.19 MHz 4.5 9.0

C1 = C2 = 22 pF
V

= 3.0 V ± 10 %

DD

6.0 MHz 2.9 5.8

4.19 MHz 2.0 4.0

I

DD2

Idle mode; VDD=5.0 V± 0%
Crystal oscillator

6.0 MHz 1.3 2.6

4.19 MHz 1.2 2.4

C1 = C2 = 22 pF
V

= 3.0 V ± 10 %

DD

6.0 MHz 0.6 1.2

4.19 MHz 0.4 0.8

I

DD3

Run mode; VDD = 3.0 V ± 10 %

20 40 µA

32 kHz crystal oscillator

I

DD4

Idle mode; VDD = 3.0 V ± 10 %

7 14

32 kHz crystal oscillator

I

DD5

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and
ADC.

2. I

3. I

4. I

and I

DD1

and I

DD3

is current when main system clock and subsystem clock oscillation stops.

DD5

include power consumption for subsystem clock oscillation.

DD2

are current when main system clock oscillation stops and the subsystem clock is used.

DD4

Stop mode; V
Stop mode; V

= 5.0 V ± 10 %

DD

= 3.0 V ± 10 %

DD

0.5 3

0.3 2

20-6

S3C821A/P821A S3P821A OTP

INSTRUCTION

CLOCK

1.33 MHz

1.00 MHz

8.33 kHz

INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

1 54 6

2 3 7

2.2 5.5

SUPPLY VOLTAGE (V)

f

x

(Main oscillation

frequency)

8 MHz

6 MHz

400 kHz

Figure 20-3. Operating Voltage Range

20-7