RHRP640CC, RHRP650CC and RHRP660CC are hyperfast
dual diodes with soft recovery characteristics (t
< 30ns).
rr
They have half the recovery time of ultrafast diodes and are
silicon nitride passivated ion-implanted hepaticas planar
construction.
These devices are intended for use as freewheeling/clamping
diodes and rectifiers in a variety of switching power supplies
and otherpower switching applications. Their low stored charge
and ultrafast soft recovery minimize ringing and electrical noise
in many power switching circuits reducing power loss in the
switching transistors.
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, see Tech Brief 334. . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IF = 1A, dIF/dt = 200A/µs- -30- -30- -30ns
IF = 6A, dIF/dt = 200A/µs- -35- -35- -35ns
t
a
t
b
Q
RR
C
R
θJC
IF = 6A, dIF/dt = 200A/µs-16--16--16-ns
IF = 6A, dIF/dt = 200A/µs-8.5--8.5--8.5-ns
IF = 6A, dIF/dt = 200A/µs-45--45--45-nC
VR = 10V, IF = 0A-20--20--20-pF
J
--3--3--3oC/W
DEFINITIONS
VF = Instantaneous forward voltage (pw = 300µs, D = 2%).
= Instantaneous reverse current.
I
R
t
= Reverse recovery time (See Figure 9), summation of ta + tb.
rr
= Time to reach peak reverse current (See Figure 9).
t
a
t
= Time from peak IRM to projected zero crossing of IRM based on a straight line from peak IRM through 25% of IRM (See Figure 9).
b
= Reverse recovery charge.
Q
RR
= Junction Capacitance.
C
J
R
= Thermal resistance junction to case.
θJC
pw = pulse width.
D = duty cycle.
o
C
o
C
o
C
2
Page 3
RHRP640CC, RHRP650CC, RHRP660CC
Typical Performance Curves
30
10
, FORWARD CURRENT (A)
F
I
1.0
0.5
00.5
175oC25oC100oC
1.02.0
VF, FORWARD VOLTAGE (V)
1.5
2.5
3.0
1000
100
10
1
REVERSE CURRENT (µA)
0.1
R,
I
0.01
0200400600300500
100
VR, REVERSE VOLTAGE (V)
175oC
100oC
25oC
FIGURE 1. FORWARD CURRENT vs FORWARD VOLTAGEFIGURE 2. REVERSE CURRENT vs REVERSE VOLTAGE
30
25
20
15
10
t, RECOVERY TIMES (ns)
5
TC = 25oC, dIF/dt = 200A/µs
t
rr
t
a
t
b
50
40
30
20
t, RECOVERY TIMES (ns)
10
TC = 100oC, dIF/dt = 200A/µs
t
rr
t
a
t
b
0
0.5
IF, FORWARD CURRENT (A)
61
0
0.5
IF, FORWARD CURRENT (A)
FIGURE 3. trr,taAND tbCURVES vs FORWARD CURRENTFIGURE 4. trr,taAND tbCURVES vs FORWARD CURRENT
75
60
45
30
t, RECOVERY TIMES (ns)
15
0
0.5
TC = 175oC, dIF/dt = 200A/µs
t
rr
t
a
t
b
IF, FORWARD CURRENT (A)
61
6
5
4
3
2
1
0
(AV), AVERAGE FORWARD CURRENT (A)
F
I
145
140150160170175165
SQ. WAVE
155
TC, CASE TEMPERATURE (oC)
DC
FIGURE 5. trr,taAND tbCURVES vs FORWARD CURRENTFIGURE 6. CURRENT DERATING CURVE
61
3
Page 4
RHRP640CC, RHRP650CC, RHRP660CC
Typical Performance Curves (Continued)
50
40
30
20
10
, JUNCTION CAPACITANCE (pF)
J
C
0
050100150200
FIGURE 7. JUNCTION CAPACITANCE vs REVERSE VOLTAGE
Test Circuits and Waveforms
VGE AMPLITUDE and
RG CONTROL dIF/dt
1 ANDt2
CONTROL I
F
L
t
V
, REVERSE VOLTAGE (V)
R
DUT
CURRENT
R
G
V
GE
t
1
t
2
IGBT
SENSE
+
V
DD
-
0
dI
F
I
F
dt
t
rr
t
a
t
b
0.25 I
RM
I
RM
FIGURE 8. trr TEST CIRCUITFIGURE 9. trr WAVEFORMS AND DEFINITIONS
L = 20mH
R < 0.1Ω
= 1/2LI2 [V
E
AVL
Q
= IGBT (BV
1
Q
CES
1
R(AVL)
> DUT V
/(V
R(AVL)
R(AVL)
CURRENT
SENSE
DUT
- VDD)]
)
LR
V
I
AVL
L
+
V
DD
I
L
IV
V
DD
t
0
t
1
t
2
t
FIGURE 10. AVALANCHE ENERGY TEST CIRCUITFIGURE 11. AVALANCHE CURRENT AND VOLTAGE
WAVEFORMS
4
Page 5
RHRP640CC, RHRP650CC, RHRP660CC
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
ØP
Q
D
E
1
L
1
E
H
1
D
1
b
1
A
A
1
SYMBOL
A0.1700.1804.324.57-
A
1
TERM. 4
o
45
b0.0300.0340.770.863, 4
b
1
c0.0140.0190.360.482, 3 , 4
D0.5900.61014.9915.49-
D
1
INCHESMILLIMETERS
NOTESMINMAXMINMAX
0.0480.0521.221.32-
0.0450.0551.151.392, 3
-0.160-4.06-
E0.3950.41010.0410.41-
L
o
60
1
2
e
e
1
b
c
E
1
-0.030-0.76-
e0.100 TYP2.54 TYP5
3
J
1
e
1
H
1
J
1
0.200 BSC5.08 BSC5
0.2350.2555.976.47-
0.1000.1102.542.796
L0.5300.55013.4713.97-
L
1
0.1300.1503.313.812
ØP0.1490.1533.793.88-
Q0.1020.1122.602.84-
NOTES:
1. These dimensions are withinallowable dimensionsof Rev.J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position oflead to bemeasured 0.250inches (6.35mm) frombottom of dimension D.
6. Position oflead to bemeasured 0.100inches (2.54mm) frombottom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
5
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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