Datasheet RFG70N06, RFP70N06 Datasheet (Fairchild Semiconductor)

G

D

S

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

RFG70N06, RFP70N06, RF1S70N06,

RF1S70N06SM

Data Sheet January 2002

70A, 60V, 0.014 Ohm, N-Channel Power
MOSFETs

These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.

Formerly developmental type TA78440.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG70N06 TO-247 RFG70N06

RFP70N06 TO-220AB RFP70N06

RF1S70N06 TO-262AA F1S70N06

RF1S70N06SM TO-263AB F1S70N06

NOTE: When ordering use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A.

Features

• 70A, 60V

DS(on)

= 0.014 Ω

®

Model

•r

• Temperature Compensated PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve (Single Pulse)

o

• 175

C Operating Temperature

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

Packaging

JEDEC STYLE TO-247

SOURCE

DRAIN

DRAIN

GATE

GATE

DRAIN

(BOTTOM

SIDE METAL)

JEDEC TO-220AB

SOURCE

DRAIN

(FLANGE)

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

JEDEC TO-263AB

JEDEC TO-262AA

±

µ

µ

θ

θ

RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM

Absolute Maximum Ratings

o

T

= 25

C, Unless Otherwise Specified

C

RFG70N06, RFP70N06

RF1S70N06, RF1S70N06SM UNITS

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

= 20k Ω ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

DSS

DGR

D

DM

GS

AS

D

, T

J

STG

L

pkg

Refer to Peak Current Curve

60 V
60 V
70

20 V

Refer to UIS Curve A

150

1.0

W/

-55 to 175

300
260

A

W

o

C

o

C

o

C

o

C

NOTE:

J

= 25

o

1. T

Electrical Specifications

C to 150

o

C.

o

T

= 25

C, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV

Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

Drain to Source On Resistance (Note 2) r

DS(ON)

Turn-On Time t

Turn-On Delay Time t

d(ON)

Rise Time t

Turn-Off Delay Time t

d(OFF)

Fall Time t

Turn-Off Time t

Total Gate Charge Q

(OFF)

g(TOT)

Gate Charge at 10V Q

Threshold Gate Charge Q

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Thermal Resistance, Junction to Case R

Thermal Resistance, Junction to Ambient R

DSS

DSS

GSS

(ON)

r

f

g(10)

g(TH)

ISS

OSS

RSS

JC

JA

I

= 250 µ A, V

D

V

= V

GS

V

= 60V, V

DS

V

= 0.8 x Rated BV

DS

V

= ± 20V - - ± 100 nA

GS

I

= 70A, V

D

V

= 30V, I

DD

V

= 10V, R

GS

(Figure 13)

= 0V (Figure 11) 60 - - V

GS

, I

= 250 µ A (Figure 10) 2 - 4 V

DS

D

= 0V - - 1

GS

, T

DSS

= 10V (Figure 9) - - 0.014 Ω

GS

D

GS

70A, R

≈

= 2.5 Ω

= 0.43 Ω ,

L

= 150

C

o

C--25

- - 125 ns

-12- ns

-50- ns

-40- ns

-15- ns

- - 125 ns

V

= 0V to 20V V

GS

V

= 0V to 10V - 100 115 nC

GS

V

= 0V to 2V - 5.5 6.5 nC

GS

V

= 25V, V

DS

= 0V, f = 1MHz

GS

(Figure 12)

= 48V, I

DD

R

= 0.68 Ω

L

I

= 2.2mA

g(REF)

(Figure 13)

= 70A,

D

- 185 215 nC

- 3000 - pF

- 900 - pF

- 300 - pF

- - 1.0

TO-220 and TO-263 - - 62

TO-247 - - 30

o

o

o

A

A

C/W

C/W

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%.

3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

I

= 70A - 1.5 V

SD

I

= 70A, dI

SD

/dt = 100A/ µ s - 125 ns

SD

30

10

0

25 50 75 100

125

150

50

I

D

, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

70

175

40

20

60

80

t, PULSE WIDTH (s)

50

10

-5

10

-4

10

-3

10

-2

10

-1

10

0

10

1

100

I

DM

, PEAK CURRENT (A)

1000

FOR TEMPERATURES
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

II

25

175 T

C

–

150

-----------------------







=

TC = 25oC

RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

T

= 25

C

125 150

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

1

0.5

o

C, Unless Otherwise Specified

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

0.01
10

500

100

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

OPERATION IN THIS
AREA MAY BE

10

LIMITED BY r

, DRAIN CURRENT (A)

D

I

T

= 25oC

C

= MAX RATED

T

J

SINGLE PULSE

1

1

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

-5

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

10

P

DM

t

1

t

x R

2

+ T

JC

C

θ

1

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

100µs

1ms

10ms

-2

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

1/t2

JC

θ

0

10

100

0

80

0123 5

120

160

I

D

, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

GS

= 7V

V

GS

= 10V

200

4

V

GS

= 5V

V

GS

= 4.5V

V

GS

= 20V

V

GS

= 8V

40

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC

VGS = 6V

0

0.5

1

1.5

-80 -40 0 40 80 120 160

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

200

2

2.5

VGS = 10V, ID = 70A

PULSE DURATION = 250µs

ON RESISTANCE

DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

0.5

0

-80 -40 0 40 80 120 160

T

J

, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

200

ID = 250µA

RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM

Typical Performance Curves T

300

100

, AVALANCHE CURRENT (A)

STARTING TJ = 150oC

AS

I

10

0.01

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R) ln [(IAS*R)/(1.3*RATED BV

AV

STARTING TJ = 25oC

0.1

tAV, TIME IN AVALANCHE (ms)

= 25oC, Unless Otherwise Specified (Continued)

C

- VDD)

DSS

) +1]

DSS-VDD

1

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

200

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 15V

DD

160

-55oC

25oC

175oC

10

FIGURE 7. SATURATION CHARACTERISTICS

120

80

40

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0

VGS, GATE TO SOURCE VOLTAGE (V)

468102

FIGURE 8. TRANSFER CHARACTERISTICS

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

THRESHOLD VOLTAGE

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

0.5

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

JUNCTION TEMPERATURE

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

200

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

45

30

15

0

10

7.5

5

2.5

0

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

V

GS

, GATE TO SOURCE VOLTAGE (V)

I

G(REF)

I

G(ACT)

20

I

G(REF)

I

G(ACT)

80

t, TIME (µs)

RL = 0.86Ω

I

G(REF)

= 2.2mA

V

GS

= 10V

0.75 BV

DSS

0.50 BV

DSS

0.25 BV

DSS

VDD = BV

DSS

VDD = BV

DSS

V

DD

V

DS

BV

DSS

t

P

I

AS

t

AV

0

t

ON

t

d(ON)

t

r

90%

10%

V

DS

90%

10%

t

f

t

d(OFF)

t

OFF

90%

50%

50%

10%

PULSE WIDTH

V

GS

0

0

RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM

Typical Performance Curves T

= 25oC, Unless Otherwise Specified (Continued)

C

5000

VGS = 0V, f = 1MHz

= CGS + C

C

4000

C

ISS

C
C

ISS
RSS
OSS

= C
≈ C

GD

DS

+ C

3000

2000

C

C, CAPACITANCE (pF)

1000

0

0 5 10 15 20

OSS

C

RSS

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

GD

GS

25

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

t

0.01Ω

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

DS

R

DUT

L

+

V

DD

-

V

GS

V

GS

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

R

GS

V

DD

Q

g(TH)

V

GS

= 2V

Q

g(10)

VGS = 10V

Q

g(TOT)

V

GS

= 20V

V

DS

V

GS

I

g(REF)

0

0

RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM

Test Circuits and Waveforms (Continued)

V

DS

R

L

V

I

g(REF)

GS

DUT

+

V

-

DD

FIGURE 18. GATE CHARGE TEST CIRCUIT

FIGURE 19. GATE CHARGE WAVEFORM

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM

PSPICE Electrical Model

.SUBCKT RFG70N06 2 1 3 ; rev 3/20/92

CA 12 8 5.56e-9
CB 15 14 5.30e-9
CIN 6 8 2.63e-9

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 65.18
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 3.10e-9
LSOURCE 3 7 1.82e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 4.66e-3
RLDRAIN 2 5 10
RGATE 9 20 1.21
RLGATE 1 9 31
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.92e-3
RLSOURCE 3 7 18.2
RVTO 18 19 RVTOMOD 1

RLGATE

GATE

1

LGATE

9

RGATE

10

-

6

ESG

8

+

EVTO

20

+

18

8

S1A

12

S1B

CA CB

6

-

RIN

S2A

13814

13

13

+

6

EGS

8

--

DPLCAP

VTO

-

15

S2B

EDS

CIN

RLDRAIN

5

LDRAIN

RSCL1RSCL2

+

51

5

ESCL

51

50

RDRAIN

16

+

21

MOS1

14

+

5
8

8

DBREAK

EBREAK

MOS2

RSOURCE

17

11

17
18

+

DBODY

-

RLSOURCE

7

LSOURCE

RBREAK

IT

2

DRAIN

3

SOURCE

18

RVTO

19

VBAT

+

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.605

.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8)
.MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5)
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7)
.MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6)
.MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

©2002 Fairchild Semiconductor Corporation RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. C

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS
EnSigna

TM

TM

FACT™
FACT Quiet Series™

STAR*POWER is used under license

FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™



OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench



QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER

SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™



UltraFET

VCX™



DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or
In Design

First Production

Full Production

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4