Datasheet RFG60P05E Datasheet (Intersil)

RFG60P05E

Data Sheet July 1999

60A, 50V, 0.030 Ohm, ESD Rated,
P-Channel Power MOSFET

This is a P-Channel powerMOSFETmanufacturedusingthe
MegaFET process. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. It was
designed for use in applications such as switching
regulators, switching converters, motor drivers, and relay
drivers. This type can be operated directly from integrated
circuits.

Formerly developmental type TA09835.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG60P05E TO-247 RFG60P05E

NOTE: When ordering, use the entire part number.

File Number

Features

• 60A, 50V

DS(ON)

= 0.030Ω

®

Model

•r

• Temperature Compensating PSPICE

• 2kV ESD Rated

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

2745.6

Packaging

DRAIN

(BOTTOM

SIDE METAL)

S

JEDEC STYLE TO-247

SOURCE

DRAIN

GATE

4-147

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG60P05E

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG60P05E UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) (Figure 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Single Pulse Avalanche Rating (Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Electrostatic Discharge Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

DS

GS

DM

AS
SD

D

Refer to Peak Current Curve

D

-50 V

-50 V

±20 V

60

215

1.43

A

W

W/oC

Refer to UIS Curve W/oC

2kV

MIL-STD-883, Category B(2)

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

STG

-55 to 175

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance, Junction to Case R
Thermal Resistance, Junction to Ambient R

DSSID

DSS

GSS

(ON)

r

F

g(-10)
g(TH)

ISS
OSS
RSS

θJC

θJA

= 250µA, VGS = 0V -50 - - V

= VDS, ID = 250µA -2--4V
VDS = -50V, VGS = 0V - - -1 µA
VDS = 0.8 x Rated BV

, TC = 150oC - - -25 µA

DSS

VGS = ±20V - - ±100 nA

= 60A, VGS = -10V (Figure 9) - - 0.030 Ω

VDD = -25V, ID = 30A, RL = 0.83Ω,
VGS = -10V, RGS = 2.5Ω
(Figure 13)

- - 125 ns

-20- ns

-60- ns

-65- ns

-20- ns

- - 125 ns
VGS = 0V to -20V VDD = -40V, ID = 60A,
VGS = 0V to -10V - - 225 nC
VGS = 0V to -2V - - 15 nC

RL = 0.67Ω
I

= -4mA

g(REF)

VDS = -25V, VGS = 0V, f = 1MHz
(Figure 12)

- - 450 nC

- 7200 - pF

- 1700 - pF

- 325 - pF

- - 0.70oC/W

--30oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Diode Reverse Recovery Time t

SD

RR

NOTE:

2. Pulse test: pulse width ≤ 300µs maximum, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4-148

ISD = -60A - - -1.75 V
ISD = -60A, dISD/dt = 100A/µs - - 200 ns

RFG60P05E

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

1

0.5

150

-70

-60

-50

-40

-30

-20

, DRAIN CURRENT (A)

D

I

-10

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.2

0.1

0.1

0.05

THERMAL IMPEDANCE

0.01
10

0.02

0.01

-5

SINGLE PULSE

10

-4

10

, NORMALIZED TRANSIENT

θJC

Z

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-500
TC= 25oC, TJ = MAX RATED

-100

-10

, DRAIN CURRENT (A)
I

OPERATION IN THIS

D

AREA MAY BE
LIMITED BY r

-1

-1 -10 -100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

DSS

MAX = -50V

-3

t, RECTANGULAR PULSE DURATION (s)

100ms

1ms

10ms

100ms
DC

-2

10

-500

, PEAK CURRENT (A)

-100

DM

I

-50

-5

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-1

10

VGS = -10V

-4

10

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

0

10

TC = 25oC
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:

I I

=

-3

10

t, PULSE WIDTH (s)

-2

10

2

1/t2

x R

θJC

θJC

175 T



--------------------- -



25



-1

10

150

–

10

+ T

C

1

10

C

0

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-149

RFG60P05E

Typical Performance Curves

-200

-100

STARTING TJ = 150oC

If R = 0
t

= (L) (IAS) / (1.3RATED BV

, AVALANCHE CURRENT (A)

AS

I

AV

If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV

-10

0.01 0.1 1 10
, TIME IN AVALANCHE (ms)

t

AV

DSS

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

- VDD)

- VDD) + 1]

DSS

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

-160
VDD = -15V

PULSE DURATIONM = 80µs
DUTY CYCLE = 0.5% MAX

-120

-55oC

175oC

25oC

-160

-120

-80

, DRAIN CURRENT (A)

-40

D

I

0

VGS = -20V

VGS = -10V

0-2 -4 -6 -8

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = -8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 25oC

T

C

VGS= -4.5V

VGS = -7V

VGS = -6V

VGS = -5V

FIGURE 7. SATURATION CHARACTERISTICS

2

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= -10V, ID = 60A

GS

1.5

-80

-40

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

0

I

0 -2 -4 -6 -8 -10

V

, GATE TO SOURCE VOLTAGE (V)

GS

1

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2

VGS = VDS, ID = 250µA

1.5

1

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 160120 200
TJ, JUNCTION TEMPERATURE (oC)

2

ID = 250µA

1.5

1

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATETHRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

4-150

FIGURE 11. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFG60P05E

Typical Performance Curves

Unless Otherwise Specified (Continued)

8000

C

ISS

6000

4000

2000

C, CAPACITANCE (pF)

0

0 -10 -15 -20 -25

C

OSS

C

RSS

-5

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C

≈ C

GD

DS

GD

+ C

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

-50

-37.5

VDD = BV

DSS

VDD = BV

DSS

-10

-7.5
RL = 0.83Ω
I

= 4mA

G(REF)

V

= -10V

0.75 BV

0.50 BV

0.25 BV

GS

0.75 BV

DSS

0.50 BV

DSS

0.25 BV

DSS

t, TIME (µs)

DSS
DSS

DSS

I

GREF()

80

------------------------ ­I

GACT()

-5

-2.5

0

-25

-12.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

I

G REF()

20

------------------------ ­I

G ACT()

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMSFOR

CONSTANT GATE CURRENT

t

AV

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V
V

GS

t

P

AS

R

G

DUT

I

AS

0.01Ω

-

V

DD

+

V

DD

I

AS

t

P

BV

DSS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

V

DS

R

L

0

V

GS

t

d(ON)

t

r

10%

t

d(OFF)

-

V

DD

V

GS

R

GS

DUT

+

V

DS

V

GS

0

90%

10%

50%

PULSE WIDTH

V

90%

DS

t

OFF

50%

90%

t

f

10%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

4-151

RFG60P05E

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

(Continued)

R

L

DUT

V

Q

GS

g(TH)

Q

g(-10)

Q

g(TOT)

0

VGS= -2V

V

0

I

G(REF)

-V

DD

-

V

DD

+

DS

VGS= -10V

VGS= -20V

4-152

PSPICE Electrical Model

.SUBCKT RFG60P05E 2 1 3; REV 9/20/94

CA 12 8 1.01e-8
CB 15 14 1.05e-8
CIN 6 8 6.9e-9

DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD

EBREAK 5 11 17 18 -76.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 7.9e-9
LSOURCE 3 7 4.18e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 12.83e-3
RGATE 9 20 1.5
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.25e-3
RVTO 18 19 RVTOMOD 1

GATE

LGATE

RFG60P05E

10

DPLCAP

RGATE

EVTO

+

-

18

8

2091

S1A S2A

12 15

13

8

13

+

-

ESG

8
6

-

+

VTO

-

6

RIN CIN

14
13

S2BS1B

CBCA

6

EDSEGS

8

DBODY

1817

19

DRAIN

3

SOURCE

RVTO

-

VBAT

+

2

5

RDRAIN

16
+

21

MOS1

14

+

5
8

-

8

EBREAK

MOS2

11

DBREAK

RSOURCE

17
18

LDRAIN

+

-

LSOURCE

7

RBREAK

IT

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 -0.83

.MODEL DBDMOD D (IS = 1.24e-12 RS = 4.72e-3 TRS1 = 1.43e-3 TRS2 = -4.91e-7 CJO = 6.98e-9 TT = 1.5e-7)
.MODEL DBKMOD D (RS = 1.11e-1 TRS1 = 1.34e-3 TRS2 = 4.46e-12)
.MODEL DPLCAPMOD D (CJO = 15e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD PMOS (VTO = -3.71 KP = 31.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 9.42e-4 TC2 = 0)
.MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 7.69e-6)
.MODEL RVTOMOD RES (TC1 = -3.39e-3 TC2 = 1.07e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.6 VOFF = 2.6)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.6 VOFF = 4.6)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.16 VOFF = -3.84)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.84 VOFF = 1.16)

.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature
Options; written by William J. Hepp and C. Frank Wheatley.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the rightto make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

4-153