Datasheet RF1S50N06SM, RFG50N06 Datasheet (Intersil)

RFG50N06, RFP50N06, RF1S50N06SM

Data Sheet July 1999 File Number

50A, 60V, 0.022 Ohm, N-Channel Power
MOSFETs

These N-Channel power MOSFETs are manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relaydrivers. These transistors can be operated
directly from integrated circuits.

Formerly developmental type TA49018.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG50N06 TO-247 RFG50N06
RFP50N06 TO-220AB RFP50N06
RF1S50N06SM TO-263AB F1S50N06

NOTE: When ordering, use theentire part number .Add the suffix, 9A,
to obtain the TO-263AB variant in tape and reel, i.e.RF1S50N06SM9A.

Features

• 50A, 60V

DS(ON)

= 0.022Ω

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

Symbol

D

G

S

®

Model

3575.4

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

JEDEC TO-263AB

GATE
SOURCE

(FLANGE)

DRAIN

(FLANGE)

DRAIN

SOURCE

DRAIN

GATE

4-467

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG50N06, RFP50N06, RF1S50N06SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG50N06, RFP50N06

RF1S50N06SM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

D

DM

AS

D

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

±20 V

50

(Figure 5)

(Figure 6, 14, 15)

131

0.877

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSS

DSS

GSS

ON

r

f

OFF

g(10)

g(TH)

ISS
OSS
RSS

θJC

θJA

ID = 250µA, VGS = 0V (Figure 11) 60 - - V
VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
VDS = 60V,

VGS = 0V

TC = 25oC--1µA
TC = 150oC--50µA

VGS = ±20V - - ±100 nA

= 50A, VGS = 10V (Figures 9) - - 0.022 Ω

VDD = 30V, ID = 50A
RL = 0.6Ω, VGS = 10V
RGS = 3.6Ω
(Figure 13)

- - 95 ns

-12 - ns

-55 - ns

-37 - ns

-13 - ns

- - 75 ns
VGS = 0 to 20V VDD = 48V, ID = 50A,
VGS = 0 to 10V - 67 80 nC
VGS = 0 to 2V - 3.7 4.5 nC

RL = 0.96Ω
I

= 1.45mA

g(REF)

(Figure 13)

VDS = 25V, VGS = 0V
f = 1MHz
(Figure 12)

- 125 150 nC

- 2020 - pF

- 600 - pF

- 200 - pF
(Figure 3) - - 1.14
TO-247 - - 30
TO-220, TO-263 - - 62

o
o
o

C/W
C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

4-468

SD

rr

ISD = 50A - - 1.5 V
ISD = 50A, dISD/dt = 100A/µs - - 125 ns

RFG50N06, RFP50N06, RF1S50N06SM

Typical Performance Curves

Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

2

1

0.5

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.2

0.1

0.1

THERMAL IMPEDANCE

0.05

0.02

0.01

, NORMALIZED

θJC

Z

SINGLE PULSE

0.01

-5

10

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

400

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

DSS(MAX)

T

= MAX RATED

J

SINGLE PULSE

= 60V

-3

10

-2

10

t1, RECTANGULAR PULSE DURATION (s)

3

10

TC = 25oC

100µs

1ms

, PEAK CURRENT (A)

10ms

100ms

2

10

DM

I

DC

40

10-310

-1

10

VGS = 20V

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-2

-1

10

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

1/t2

x R

θJC

θJC

0

10

FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:

175 TC–



II

=

----------------------- -



25

150



TC = 25oC

0

10

1

10

2

10

10

t, PULSE WIDTH (ms)

+ T

C

1

10

3

4

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-469

RFG50N06, RFP50N06, RF1S50N06SM

Typical Performance Curves

300

100

10

AVALANCHE CURRENT (A)

AS,

I

STARTING TJ = 150oC

If R = 0
tAV = (L) (IAS) / (1.3 RATED BV

If R ≠ 0

= (L/R) ln [(IAS*R) / (1.3 RATED BV

t

AV

1

0.01 0.1 1 10

STARTING TJ = 25oC

t

TIME IN AVALANCHE (ms)

AV,

Unless Otherwise Specified (Continued)

- VDD)

DSS

- VDD) + 1]

DSS

NOTE: Refer to Intersil Application Notes 9321 and 9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

125

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V

100

-55oC

25oC

175oC

125

VGS = 10V

100

75

50

, DRAIN CURRENT (A)

D

I

25

0

0 1.5 3.0 4.5 6.0 7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4V

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 10V, ID = 50A

V

GS

2.0

75

50

, DRAIN CURRENT (A)

D

I

25

0

012345678910

VGS, GATE TO SOURCE VOLTAGE (V)

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 160120 200
TJ, JUNCTION TEMPERATURE (oC)

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

4-470

FIGURE 11. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFG50N06, RFP50N06, RF1S50N06SM

Typical Performance Curves

Unless Otherwise Specified (Continued)

4000

VGS = 0V, f = 1MHz
C

= CGS + C

3000

ISS

C

RSS

C

OSS

C

ISS

= C

GD

= CDS + C

GD

GD

2000

C

C

OSS

RSS

C, CAPACITANCE (pF)

1000

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE(V)

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

-

60

45

30

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

I

g(REF)

20

I

g(ACT)

DSS

0.75 BV

0.50 BV

0.25 BV

DSS
DSS
DSS

RL = 1.2Ω

= 1.45mA

I

g(REF)

V

= 10V

GS

t, TIME (µs)

0.75 BV

0.50 BV

0.25 BV

VDD = BV

DSS
DSS

DSS

80

DSS

I

g(REF)

I

g(ACT)

10

7.5

5.0

2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

BV

DSS

t

P

I

AS

V

DD

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

4-471

RFG50N06, RFP50N06, RF1S50N06SM

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

(Continued)

R

L

DUT

V

DD

+

V

DD

-

VGS= 2V

0

I

g(REF)

0

V

GS

Q

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

4-472

PSPICE Electrical Model

.SUBCKT RFP50N06213
REV 2/22/93

*NOM TEMP = 25

CA 12 8 3.68e-9
CB 15 14 3.625e-9
CIN 6 8 1.98e-9

DBODY 7 5 DBDMOD
DBREAK 5 11DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 64.59
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 5.65e-9
LSOURCE 3 7 4.13e-9

MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1e-4
RGATE 9 20 0.690
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 12e-3
RVTO 18 19 RVTOMOD 1

o

C

RFG50N06, RFP50N06, RF1S50N06SM

VTO

15

EDSEGS

5

RDRAIN

16
+

21

MOS1

8

CBCA

14

+

5
8

-

GATE

1

LGATE

RGATE

ESG

EVTO
+

209

S1A S2A

12

10

-

+

-

18

8

13

8

DPLCAP

6
8

-

6

RIN CIN

14
13

S2BS1B
13

+

6
8

-

DBREAK

MOS2

EBREAK

RSOURCE

11

+

17
18

-

RBREAK

7

DRAIN

LDRAIN

DBODY

LSOURCE

SOURCE

1817

RVTO

19IT

-

VBAT

+

2

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.678

.MODEL DBDMOD D (IS=9.85e-13 RS=4.91e-3 TRS1=2.07e-3 TRS2=2.51e-7 CJO=2.05e-9 TT=4.33e-8)
.MODEL DBKMOD D (RS=1.98e-1 TRS1=2.35E-4 TRS2=-3.83e-6)
.MODEL DPLCAPMOD D (CJO=1.42e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.65 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.23e-3 TC2=-2.34e-7)
.MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.49e-5)
.MODEL RVTOMOD RES (TC1=-5.03e-3 TC2=-5.16e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.75 VOFF=-2.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-6.75)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.7 VOFF=2.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.3 VOFF=-2.7)

.ENDS

NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authors, William J. Hepp and C. Frank Wheatley.

4-473

RFG50N06, RFP50N06, RF1S50N06SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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4-474

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