Datasheet RF1S30P05SM, RFG30P05, RFP30P05 Datasheet (Intersil)

RFG30P05, RFP30P05, RF1S30P05SM

Data Sheet July 1999

30A, 50V, 0.065 Ohm, P-Channel Power
MOSFETs

These are P-Channel power MOSFETs manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as s witching regulators, switching conv erters, motor
drivers, and relay drivers. These transistors can be
operated directly from integrated circuits.

Formerly developmental type TA09834.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG30P05 TO-247 RFG30P05
RFP30P05 TO-220AB RFP30P05
RF1S30P05SM TO-263AB F1S30P05

NOTE: When ordering,usethe entirepart number. Addthesuffix 9Ato
obtain the TO-263AB variant in tape and reel, i.e., RF1S30P05SM9A.

File Number

Features

• 30A, 50V

DS(ON)

= 0.065Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

2436.4

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

JEDEC TO-263AB

GATE

SOURCE

(FLANGE)

DRAIN

(FLANGE)

DRAIN

SOURCE

DRAIN

GATE

4-126

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG30P05, RFP30P05, RF1S30P05SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG30P05, RFP30P05

RF1S30P05SM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

D

Refer to Peak Current Curve

D

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Single Pulse Avalanche Rating (Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T

AS

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

-50 V

-50 V

±20 V

30

120

0.8

Refer to UIS Curve

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)VGS

Gate Charge at -10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance, Junction to Case R
Thermal Resistance, Junction to Ambient R

DSSID

DSS

GSS

(ON)

r

f

g(-10)
g(TH)

ISS
OSS
RSS

θJC

θJA

= 250µA, VGS = 0V -50 - - V

= VDS, ID = 250µA -2 - -4 V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - -1 µA

DSS

, TC = 150oC - - -25 µA

DSS

VGS = ±20V - - ±100 nA

= 30A, VGS = -10V (Figure 9) - - 0.065 Ω

VDD = -25V, ID = 15A,
RL = 1.67Ω, VGS = -10V,
RG = 6.25Ω
(Figure 13)

- - 80 ns

-15-ns

-23-ns

-28-ns

-18-ns

- - 100 ns

= 0 to -20V VDD = -40V,
VGS = 0 to -10V - 70 85 nC
VGS = 0 to -2V - 5.5 6.6 nC

ID = 30A, RL = 1.33Ω,
I

= 1.6mA

G(REF)

VDS = -25V, VGS = 0V
f = 1MHz
(Figure 12)

- 140 170 nC

- 3200 - pF

- 800 - pF

- 175 - pF

- - 1.25oC/W
TO-220, TO-263 - - 62
TO-247 - - 30

o

C/W

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Reverse Recovery Time t

SD

rr

NOTES:

2. Pulsed: pulse duration = 300µs max, duty cycle = 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4-127

ISD = -30A - - -1.5 V
ISD = -30A, dISD/dt = -100A/µs - - 150 ns

RFG30P05, RFP30P05, RF1S30P05SM

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

2

1

150

-40

-30

-20

, DRAIN CURRENT (A)

D

-10

I

0

25

50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENTvs

CASE TEMPERATURE

0.5

0.2

0.1

0.1

, NORMALIZED

θJC

Z

-200

-100

-10

, DRAIN CURRENT (A)

D

I

-1

-1

0.05

THERMAL IMPEDANCE

0.02

0.01

0.01

-5

10

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

V

SINGLE PULSE

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

DS(ON)

V

MAX = -50V

DSS

T

= 25oC

C

-10

, DRAIN TO SOURCE VOLTAGE (V)

DS

-3

10

t, RECTANGULAR PULSE DURATION (s)

100µs

1ms

10ms

100ms

DC

-100

-2

10

-500

-100

, PEAK CURRENT (A)

DM

I

-10
10

-1

10

VGS = -20V

VGS = -10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-5

-4

10

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

10

= 25oC

T

C

FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:

II

=

-3

10

t, PULSE WIDTH (s)

-2

10

2

x R

θJC

θJC

0

–

175 T

---------------------

150

-1

10

C



25



10

+ T

C

1

10

0

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-128

RFG30P05, RFP30P05, RF1S30P05SM

Typical Performance Curves

-100

STARTING TJ = 25oC

-10

STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

AS

I

= (L) (IAS) / (1.3 RATED BV

t

AV

If R ≠ 0
t

= (L/R) ln [(IAS*R) / (1.3 RATED BV

AV

-1

0.1 1 10 100
t

, TIME IN AVALANCHE (ms)

AV

DSS

Unless Otherwise Specified (Continued)

- VDD)

- VDD) + 1]

DSS

-75

-60

-45

-30

DRAIN CURRENT (A)

D,

I

-15

0

0 -2 -4 -6 -8 -10

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = -20V

VGS = -10V

VGS = -8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC

VGS = -4.5V

VGS = -7V

VGS = -6V

VGS = -5V

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS

-75

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= -15V

DD

-60

-45

-30

-15

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

0

I

0

-2
V

GS

-4

, GATE TO SOURCE VOLTAGE (V)

-6

-55oC

o

C

25

o

C

175

-8

-10

2

1.5

1

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS= -10V, ID = 30A

-40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

200

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAINTO SOURCE ON

2

VGS = VDS, ID =-250µA

1.5

1

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80
TJ, JUNCTION TEMPERATURE (oC)

160120 200

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

4-129

RESISTANCE vs JUNCTION TEMPERATURE

2

ID = 250µA

1.5

1

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 11. NORMALIZED DRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFG30P05, RFP30P05, RF1S30P05SM

Typical Performance Curves

Unless Otherwise Specified (Continued)

4000

C

ISS

3000

VGS = 0V, f = 1MHz

2000

C, CAPACITANCE (pF)

1000

0

0

ISS

C

= C

RSS

C

≈ C

OSS

C

OSS

C

RSS

-5 -10 -15 -20 -25

GD

DS

+ C

GD

GS

= CGS + C

C

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

-50

-37.5

-25

-12.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

VDD = BV

DSS

I

GATE

SOURCE

VOLTAGE

RL = 1.67Ω

= 1.6mA

G(REF)

VGS = -10V

0.75 BV

0.50 BV

0.25 BV

DSS
DSS
DSS

VDD = BV

DSS

DRAIN SOURCE VOLTAGE

0

20

I

G(REF)

I

G(ACT)

t, TIME (µs)

80

I

G(REF)

I

G(ACT)

-10

-7.5

-5

-2.5

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHINGWAVEFORMS FOR

CONSTANT GATE CURRENT

t

AV

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V
V

GS

t

P

AS

R

G

DUT

I

AS

0.01Ω

-

V

DD

+

V

DD

I

AS

t

P

BV

DSS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

d(ON)

10%

50%

t

r

90%

10%

V

DS

R

L

V

GS

-

V

DD

V

GS

R

GS

DUT

+

0

V

DS

V

GS

0

PULSE WIDTH

t

d(OFF)

V

90%

DS

t

OFF

50%

90%

t

f

10%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

4-130

RFG30P05, RFP30P05, RF1S30P05SM

Test Circuits and Waveforms

V

DS

V

GS

I

G(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

(Continued)

R

L

DUT

V

Q

GS

g(TH)

Q

g(-10)

Q

g(TOT)

0

VGS= -2V

-

V

DD

+

V

0

I

G(REF)

-V

DD

DS

VGS= -10V

VGS= -20V

4-131

PSPICE Electrical Model

.SUBCKT RFP30P05 2 1 3;
REV 8/21/94

RFG30P05, RFP30P05, RF1S30P05SM

CA 12 8 3.23e-9
CB 15 14 3.23e-9
CIN 6 8 3.08e-9

DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD

EBREAK 5 11 17 18 -77.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 4.92e-9
LSOURCE 3 7 4.60e-9

MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 39.85e-3
RGATE 9 20 2.34
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 2.56e-3
RVTO 18 19 RVTOMOD 1

GATE

1

9

LGATE RGATE

DPLCAP

EVTO

20

+

S1A

12

S1B

CA

18

8

EGS

10

-

RIN

13814

+

ESG

+

-

VTO

-

6

S2A

15

13

S2B

13

6

EDS

8

5

8
6

RSCL1RSCL2

+

CIN

CB

16

+

--

5

51

14

6
8

51

+

ESCL

50
RDRAIN

21

MOS1

8

EBREAK

MOS2

DBREAK

RSOURCE

11

17

+

17
18

-

7

RBREAK

IT

DRAIN

LDRAIN

DBODY

LSOURCE

SOURCE

18

RVTO

19

VBAT

+

2

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 -0.81

ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/114,5))}

.MODEL DBDMOD D (IS=4.7e-13 RS=1.31e-2 TRS1=1.39e-4 TRS2=-4.77e-6 CJO=2.85e-9 TT=8.81e-8)
.MODEL DBKMOD D (RS=2.23e-1 TRS1=1.97e-3 TRS2=-2.37e-5)
.MODEL DPLCAPMOD D (CJO=0.78e-9 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.75 KP=10.83 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=9.08e-4 TC2=-1.72e-6)
.MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.02e-5)
.MODEL RSCLMOD RES (TC1=2.09e-3 TC2=5.88e-7)
.MODEL RVTOMOD RES (TC1=-2.99e-3 TC2=1.40e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.4 VOFF=1.4)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.4 VOFF=3.4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.2 VOFF=-3.8)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.8 VOFF=1.2)

.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global

Temperature Options; authors, William J. Hepp and C. Frank Wheatley.

4-132

RFG30P05, RFP30P05, RF1S30P05SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductorproducts are sold by description only.Intersil Corporation reserv esthe right to make changes in circuit design and/or specifications at anytime with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor forany infringements of patents or other rights of thirdparties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

4-133

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]