The RFF70N06 N-Channel powerMOSFETismanufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Reliability screening is available as either commercial or
TX/TXV equivalent of MIL-S-19500. Contact Intersil
Corporation High-Reliability Marketing group for any desired
deviations from the data sheet.
Formerly developmental type TA49007.
Ordering Information
PART NUMBERPACKAGEBRAND
RFF70N06TO-254AARFF70N06
NOTE: When ordering, use the entire part number.
File Number
Features
• 25A†, 60V
DS(ON)
= 0.025Ω
•r
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
C Operating Temperature
• 150
• Reliability Screened
Current is limited by the package capability.
†
Symbol
D
G
S
4073.2
Commercial Version: RFG70N06.
Packaging
JEDEC TO-254AA
GATE
PACKAGE TAB
(ISOLATED)
CAUTION: Berylia Warning per MIL-S-19500.
Refer to package specifications.
SOURCE
DRAIN
4-442
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
60V
60V
±20V
25 (Note 2)
Refer to UIS Curve
100
0.80
-55 to 150
260
A
W
W/oC
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC.
2. Current is limited by the package capability.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 3)r
DS(ON)ID
Turn-On Timet
Turn-On Delay Timet
d(ON)
Rise Timet
Turn-Off Delay Timet
d(OFF)
Fall Timet
Turn-Off Timet
Total Gate ChargeQ
g(TOT)VGS
Gate Charge at 10VQ
Threshold Gate ChargeQ
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
Thermal Resistance Junction to CaseR
Thermal Resistance Junction to AmbientR
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),3))}
.MODEL DBDMOD D (IS = 1e-12 RS = 11.01e-3 TRS1 = 1.75e-3 TRS2 = -0.06e-6 CJO = 2.70e-9 TT = 7.82e-8 M = 0.45)
.MODEL DBREAKMOD D (RS = 88e-3 TRS1 = 1.50e-3 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 2.60e-9 IS = 1e-30 N = 10 M=0.7)
.MODEL MSTRONG NMOS (VTO = 3.85 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u)
.MODEL MWEAK NMOS (VTO = 3.09 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1.90e-5)
.MODEL RDSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSCLMOD RES (TC1 = 0 TC2 = 0)
.MODEL RTHRESHMOD RES (TC1 = -3.10e-3 TC2 = -1e-5)
.MODEL RZTEMPCOMOD RES (TC1 = -2.25e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.0 VOFF= -4.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -6.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 2.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.0 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring GlobalTemperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
4-448
Page 8
RFF70N06
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table)
.
Delta Tests and Limits (JANTX/JANTXV Equivalent)
PARAMETERSYMBOLTEST CONDITIONSMAXUNITS
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
On Resistance
Gate Threshold Voltage
I
GSS
I
DSS
r
DS(ON)
V
GS(TH)
NOTES:
5. Or 100% of Initial Reading (whichever is greater).
6. Of Initial Reading.
Screening Information
TESTJANTX/JANTXV EQUIVALENT
Gate StressVGS = 30V, t = 250µs
PindOptional
PDA10%
Pre Burn-In Test (Note 7)MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25
Steady State Gate Bias (Gate Stress)MIL-STD-750, Method 1042, Condition B
Interim Electrical Tests (Note 7)All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress)MIL-STD-750, Method 1042, Condition A
Final Electrical Tests (Note 7)MIL-S-19500, Group A, Subgroup 2
NOTE:
7. Test limits are identical pre and post burn-in.
VGS = ±20V, TC = 25oC
VDS = 80% Rated Value, TC = 25oC
TC = 125oC at Rated I
ID = 1.0mA, TC = 25oC
= 80% of Rated Value,
V
GS
= 150oC, Time = 48 hours
T
A
= 80% of Rated Value,
V
DS
= 150oC, Time = 168 hours
T
A
D
±20(Note 5)nA
±25(Note 5)µA
±20% (Note 6)Ω
±20% (Note 6)V
o
C)
Additional Screening Tests
PARAMETERSYMBOLTEST CONDITIONSMAXUNITS
Safe Operating Area
Unclamped Inductive Switching
Thermal Response
Thermal Impedance
SOA
I
∆V
∆V
AS
SD
SD
VDS = 48V, t = 10ms
V
GS(PEAK)
tH = 100ms; VH = 25V, IH = 4A
tH = 500ms; VH = 25V, IH = 4A
= 15V, L = 0.1mH
4.8A
75A
220mV
330mV
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-449
EUROPE
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100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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