Datasheet RFF60P06 Datasheet (Intersil)

Page 1
RFF60P06
Data Sheet September 1998
The RFF60P06 P-Channel power MOSFET is manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits gives optimum utilization of silicon, resulting in outstanding performance. It wasdesignedforusein applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits.
Reliability screening is available as either commercial or TX/TXV equivalent of MIL-S-19500. Contact Intersil Corporation High-Reliability Marketing group for any desired deviations from the data sheet.
Formerly developmental type TA09835. Commercial Version: RFG60P06E. † Current is limited by the package capability.
Ordering Information
File Number
Features
• 25A, 60V
DS(ON)
= 0.030
•r
• Temperature Compensating PSPICE
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
C Operating Temperature
• 150
• Reliability Screened
Symbol
D
G
S
®
Model
3975.2
PART NUMBER PACKAGE BRAND
RFF60P06 TO-254AA RFF60P06
NOTE: When ordering, use the entire part number.
Packaging
PACKAGE TAB
(ISOLATED)
CAUTION: Berylia Warning per MIL-S-19500.
JEDEC TO-254AA
GATE
SOURCE
DRAIN
Refer to package specifications.
4-181
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999.
Page 2
RFF60P06
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
RFF60P06 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (RGS = 20k) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
DSS
DGR
GS
DM
AS
D
Refer to Peak Current Curve
D
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
-60 V
-60 V
±20 V
25 (Note 5)
Refer to UIS Curve
125
1.0
-55 to 150
260
A
W
W/oC
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V
GS(TH)VGS
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r
DS(ON)ID
Turn-On Time t Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t Total Gate Charge Q
g(TOT)VGS
Gate Charge at -10V Q Threshold Gate Charge Q
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
DSSID
DSS
GSS
ON
r
f
OFF
g(-10)VGS g(TH)VGS
ISS OSS RSS
θJC
θJA
= 250µA, VGS = 0V -60 - - V
= VDS, ID = 250µA -2.0 -3.0 -4.5 V
VDS = Rated BV
DSS,VGS
VDS = 0.8 x Rated BV
= 0V - - -25 µA
, VGS = 0V, TC = 125oC - - -250 µA
DSS
VGS = ±20V, TC = 125oC--±100 µA
= 25A, VGS = -10V, (Figure 9) - - 0.030
VDD = -30V, ID = 25A, RL = 1.2, VGS = -10V RG = 2.35 (Figures 13, 16, 17)
- - 195 ns
-2570ns
- 50 125 ns
- 80 200 ns
-3075ns
- - 275 ns = 0 to -20V VDD = -30V, ID = 25A, = 0 to -10V - - 225 nC = 0 to -2V - - 15 nC
RL = 1.2 I
= -4.2mA
G(REF)
(Figures 18, 19)
VDS = -25V, VGS = 0V f = 1MHz
- - 450 nC
- 7200 - pF
- 1800 - pF
- 400 - pF
- - 1.0
o
C/W
--48oC/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) V Diode Reverse Recovery Time t
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3)
4. Current is limited by package capability.
4-182
ISD = -25A - -1.1 -1.5 V
SD
ISD = -25A, dISD/dt = -100A/µs - 130 200 ns
rr
Page 3
RFF60P06
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 125 150
TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
2
1
-30
-25
-20
-15
-10
, DRAIN CURRENT (A)
D
I
-5 0
100755025
125
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
150
0.5
0.2
0.1
0.1
, NORMALIZED
JC
θ
Z
-500
-100
-10
, DRAIN CURRENT (A)
D
I
-1
0.05
0.02
THERMAL IMPEDANCE
0.01
0.01
-5
10
OPERATION IN THIS AREA MAY BE LIMITED BY r
TC = 25oC
= MAX RATED
T
J
-1 V
SINGLE PULSE
-4
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
DS(ON)
V
MAX = -60V
DSS
-10 -100
, DRAIN-TO-SOURCE VOLTAGE (V)
DS
-3
10
t, RECTANGULAR PULSE DURATION (s)
100µs
1ms
10ms
100ms
DC
-2
10
3
-10
2
-10
, PEAK CURRENT (A)
DM
I
1
-10 10
NOTES: DUTY FACTOR: D = t PEAK TJ = PDM x Z
-1
10
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS:
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION V
-5
-4
10
10
t, PULSE WIDTH (s)
P
DM
t
1
t
2
1/t2
x R
125
+ T
JC
θ
C
TC = 25oC
0
10
C
1
10
1
10
JC
θ
0
10
150 T

II
= -10V
GS
-3
-2
10
--------------------- -
=

25

-1
10
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
4-183
Page 4
RFF60P06
Typical Performance Curves
-200
-100
-75
, AVALANCHE CURRENT (A)
AS
I
-10
If R = 0 t
= (L) (IAS) / (1.3 RATED BV
AV
If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV
STARTING TJ = 150oC
0.1 1 10 100 , TIME IN AVALANCHE (ms)
t
AV
Unless Otherwise Specified (Continued)
- VDD)
DSS
- VDD) + 1]
DSS
STARTING TJ = 25oC
-150 VGS = -10V
V
= -20V
GS
-125
-100
-75
-50
, DRAIN CURRENT (A)
D
I
-25
0
0 -2 -4 -6 -8 -10
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -8V
PULSE DURATION = 250µs T
= 25oC
C
VGS = -4.5V
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
-150 VDD = -15V
PULSE TEST
-125
PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX
-100
-75
-50
, DRAIN TO SOURCE CURRENT (A)
-25
0
DS(ON)
I
0 -2 -4 -6 -8 -10
, GATE TO SOURCE VOLTAGE (V)
V
GS
-55oC
25oC
150oC
2.5
PULSE DURATION = 250µs, VGS= -10V, ID = 25A
2.0
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 T
, JUNCTION TEMPERATURE (oC)
J
VGS = -7V
VGS = -6V
VGS = -5V
120
160
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
2.0 VGS = VDS, ID = 250µA
1.5
1.0
NORMALIZED GATE
0.5
THRESHOLD VOLTAGE
0
-80 -40 0 40 80 160120 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
4-184
RESISTANCE vs JUNCTION TEMPERATURE
2.0 ID = 250µA
1.5
1.0
0.5
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Page 5
RFF60P06
Typical Performance Curves
Unless Otherwise Specified (Continued)
8000
C
6000
ISS
VGS = 0V, f = 0.1MHz
= CGS + C
C C C
ISS RSS OSS
= C
GD
CDS + C
GD
GS
4000
C
OSS
2000
C, CAPACITANCE (pF)
C
RSS
0
0
-5 -10 -15 -20 -25
VDS, DRAIN TO SOURCE VOLTAGE(V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuit and Waveforms
V
DS
L
-60
-45
-30
-15
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
0
VDD = BV
I
G(REF)
20
I
G(ACT)
DSS
0.75 BV
0.50 BV
0.25 BV
RL = 1.0 I
G(REF)
V
= -10V
GS
DSS DSS DSS
t, TIME (µs)
= 4.2mA
0.75 BV
0.50 BV
0.25 BV
VDD = BV
DSS DSS DSS
I
G(REF)
80
I
G(ACT)
-10
DSS
-7.5
-5.0
-2.5
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMSFOR
CONSTANT GATE CURRENT
t
AV
0
, GATE TO SOURCE VOLTAGE (V)
GS
V
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V V
GS
t
P
AS
R
G
DUT
I
AS
0.01
-
V
DD
+
V
DD
I
AS
t
P
BV
DSS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
ON
t
d(ON)
10%
50%
t
r
90%
10%
V
DS
R
L
V
GS
-
V
DD
V
GS
R
GS
DUT
+
0
V
DS
V
GS
0
PULSE WIDTH
t
d(OFF)
V
DS
t
90%
OFF
90%
50%
t
f
10%
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
4-185
Page 6
RFF60P06
Test Circuit and Waveforms
V
GS
I
G(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
V
DS
(Continued)
R
L
DUT
­V
DD
+
Data Packages - Intersil Power Transistors
TX and TXV Equivalents
1. TX/TXV Equivalent - Standard Data Package A. Certificate of Compliance B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet
F. Group C - Attributes Data Sheet
2. TX/TXV Equivalent - Optional Data Package
A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet
- Precondition Lot Traveler
- Pre and Post Burn-In Read and Record Data
D. Group A - Attributes Data Sheet
- Group A Lot Traveler
E. Group B - Attributes Data Sheet
- Group B Lot Traveler
- Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6)
F. Group C - Attributes Data Sheet
- Group C Lot Traveler
- Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
0
VGS= -2V
V
DD
0
I
G(REF)
V
Q
g(TH)
-V
GS
Q
g(-10)
Q
g(TOT)
DS
VGS= -10V
VGS= -20V
4-186
Page 7
RFF60P06
PSPICE Electrical Model
.SUBCKT RFF60P06 2 1 3 REV 9/20/94
CA 12 8 1.01e-8 CB 15 14 1.05e-8 CIN 6 8 6.9e-9
DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 5 DPLCAPMOD
EBREAK 5 11 17 18 -76.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 8 6 1 EVTO 20 6 8 18 1
IT 8 17 1
LDRAIN 2 5 1e-9 LGATE 1 9 7.9e-9 LSOURCE 3 7 4.18e-9
MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01
RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 12.83e-3 RGATE 9 20 1.55 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.25e-3 RVTO 18 19 RVTOMOD 1
GATE
RGATE
LGATE
-
ESG
+
EVTO
+
-
18
8
2091
S1A S2A
12 15
13
8
10
DPLCAP
6 8
-
RIN CIN
14 13
S2BS1B
13
+
6 8
-
VTO
EDSEGS
5
RDRAIN
11
17 18
RBREAK
+
-
7
IT
8
EBREAK
MOS2
DBREAK
RSOURCE
16 +
21
MOS1
6
CBCA
14
+
5 8
-
DRAIN
LDRAIN
DBODY
LSOURCE
1817
RVTO
19
-
VBAT
+
2
3
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1 VTO 21 6 -0.83
.MODEL DBDMOD D (IS=1.24e-12 RS=4.72e-3 TRS1=1.43e-3 TRS2=-4.91e-7 CJO=6.98e-9 TT=1.5e-7) .MODEL DBKMOD D (RS=1.11e-1 TRS1=1.34e-3 TRS2=4.46e-12) .MODEL DPLCAPMOD D (CJO=15e-10 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.71 KP=31.5 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=9.42e-4 TC2=0) .MODEL RDSMOD RES (TC1=5.85e-3 TC2=7.69e-6) .MODEL RVTOMOD RES (TC1=-3.39e-3 TC2=1.07e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.6 VOFF=2.6) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.6 VOFF=4.6) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.16 VOFF=-3.84) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.84 VOFF=1.16)
.ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
4-187
Page 8
RFF60P06
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTX/JANTXV Equivalent)
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Gate to Source Leakage Current I Zero Gate Voltage Drain Current I On Resistance r Gate Threshold Voltage V
NOTES:
5. Or 100% of Initial Reading (whichever is greater).
6. Of Initial Reading.
GSS
DSS
DS(ON)
GS(TH)
Screening Information
TEST JANTX/JANTXV EQUIVALENT
Gate Stress VGS = -30V, t = 250µs Pind Optional PDA 10% Pre Burn-In Test (Note 1) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B
Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A
Final Electrical Tests (Note 6) MIL-S-19500, Group A, Subgroup 2
NOTE:
7. Test limits are identical pre and post burn-in.
VGS = ±20V, TC = 25oC ±20(Note 4) nA VDS = 80% Rated Value, TC = 25oC ±25 (Note 4) µA TC = 125oC at Rated I ID = 1.0mA, TC = 25oC ±20% (Note 5) V
VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
VDS = 80% of Rated Value, TA = 150oC, Time = 168 hours
D
±20% (Note 5)
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = -48V, t = 10ms 8.0 A Unclamped Inductive Switching I Thermal Response V Thermal Impedance V
AS
SD SD
V
GS(PEAK)
tH = 100ms; VH = 25V, IH = 4A 142 mV tH = 500ms; VH = 25V, IH = 4A 182 mV
= -15V, L = 0.1mH 75 A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240
4-188
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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