Datasheet RFD3055LE, RFD3055LESM, RFP3055LE Datasheet (Fairchild Semiconductor)

Page 1
D
G
S
SOURCE
DRAIN (FLANGE)
GATE
DRAIN
RFD3055LE, RFD3055LESM, RFP3055LE
Data Sheet January 2002
11A, 60V, 0.107 Ohm, Logic Level, N-Channel Power MOSFETs
Formerly developmental type TA49158.
Ordering Information
PART NUMBER PACKAGE BRAND
RFD3055LE TO-251AA F3055L
RFD3055LESM TO-252AA F3055L
RFP3055LE TO-220AB FP3055LE
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-252 variant in tape and reel, e.g. RFD3055LESM9A.
Features
• 11A, 60V
DS(ON)
= 0.107
®
Model
•r
• Temperature Compensating PSPICE
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
Packaging
DRAIN (FLANGE)
JEDEC TO-220AB JEDEC TO-251AA
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
Page 2
±
µ
µ
θ
θ
RFD3055LE, RFD3055LESM, RFP3055LE
Absolute Maximum Ratings
o
T
= 25
C, Unless Otherwise Specified
C
RFD3055LE, RFD3055LESM,
RFP3055LE UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
= 20k ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
DSS
DGR
GS
D
DM
AS
D
, T
J
STG
Refer to Peak Current Curve
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
60 V 60 V
16 V
11
Refer to UIS Curve
38
0.25
-55 to 175
300 260
W/
A
W
o
C
o
C
o
C
o
C
NOTE:
J
= 25
o
1. T
Electrical Specifications
C to 150
o
C.
o
T
= 25
C, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
GS(TH)
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r
DS(ON)
Turn-On Time t
Turn-On Delay Time t
d(ON)
Rise Time t
Turn-Off Delay Time t
d(OFF)
Fall Time t
Turn-Off Time t
Total Gate Charge Q
g(TOT)
Gate Charge at 5V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
DSS
DSS
GSS
ON
r
f
OFF
g(5)
g(TH)
ISS
OSS
RSS
JC
JA
I
= 250 µ A, V
D
V
= V
GS
DS
V
= 55V, V
DS
V
= 50V, V
DS
V
= ± 16V - - ± 100 nA
GS
I
= 8A, V
D
V
30V, I
DD
V
= 4.5V, R
GS
(Figures 10, 18, 19)
= 0V 60 - - V
GS
, I
= 250 µ A1-3V
D
= 0V - - 1
GS
= 0V, T
GS
= 5V (Figure 11) - - 0.107
GS
= 8A,
D
= 32
GS
= 150
C
o
C - - 250
- - 170 ns
-8 - ns
- 105 - ns
-22 - ns
-39 - ns
- - 92 ns
V
= 0V to 10V V
GS
V
= 0V to 5V - 5.2 6.2 nC
GS
V
= 0V to 1V - 0.36 0.43 nC
GS
V
= 25V, V
DS
= 0V, f = 1MHz
GS
(Figure 14)
= 30V, I
DD
I
g(REF)
D
= 1.0mA
(Figures 20, 21)
= 8A,
- 9.4 11.3 nC
- 350 - pF
- 105 - pF
-23 - pF
- - 3.94
TO-220AB - - 62
TO-251AA, TO-252AA - - 100
o
o
o
A
A
C/W
C/W
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
Diode Reverse Recovery Time t
SD
rr
NOTES:
2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5).
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
I
= 8A - 1.25 V
SD
I
= 8A, dI
SD
/dt = 100A/ µ s - 66 ns
SD
Page 3
5
10
15
25 50 75 100 125 150 175
0
I
D
, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
V
GS
= 10V
V
GS
= 4.5V
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
200
10
I
DM
, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
TC = 25oC
I = I
25
175 - T
C
150
FOR TEMPERATURES ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
RFD3055LE, RFD3055LESM, RFP3055LE
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
25 50 75 100
0
0
TC, CASE TEMPERATURE (oC)
Unless Otherwise Specified
125
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
θJC
Z
THERMAL IMPEDANCE
SINGLE PULSE
0.01
-5
10
-4
10
10
175
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
-3
t, RECTANGULAR PULSE DURATION (s)
-2
10
CASE TEMPERATURE
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-1
10
θJC
10
P
DM
1/t2
x R
0
θJC
t
1
+ T
t
2
C
1
10
FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE
100
10
OPERATION IN THIS
, DRAIN CURRENT (A)
D
I
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
AREA MAY BE
1
LIMITED BY r
SINGLE PULSE TJ = MAX RATED
0.1
1 10 100
DS(ON)
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
T
= 25oC
C
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
100µs
1ms
10ms
200
Page 4
I
D
, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 3V
VGS = 5V
V
GS
= 10V
VGS = 4V
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
3
6
9
12
15
01234
0
VGS = 3.5V
TC = 25oC
90
120
150
246810
60
ID = 3A
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
DS(ON)
, DRAIN TO SOURCE
ON RESISTANCE (m)
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
T
C
= 25oC
ID = 11A
I
D
= 5A
1.0
1.5
2.0
2.5
-80 -40 0 40 80 120 160 200
0.5
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 11A
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
RFD3055LE, RFD3055LESM, RFP3055LE
Typical Performance Curves Unless Otherwise Specified (Continued)
100
If R = 0 tAV = (L)(IAS)/(1.3*RATED BV
If R 0 t
= (L/R)ln[(IAS*R)/(1.3*RATED BV
AV
DSS
- VDD)
DSS
- VDD) +1]
10
STARTING TJ = 150oC
, AVALANCHE CURRENT (A)
AS
I
1
0.001 0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
15
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
V
= 15V
DD
12
9
6
TJ = 25oC
DRAIN CURRENT (A)
3
D,
I
TJ = 175oC
0
2345
VGS, GATE TO SOURCE VOLTAGE (V)
TJ = -55oC
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
150
VGS = 4.5V, VDD = 30V, ID = 8A
100
50
SWITCHING TIME (ns)
0
0 1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
t
r
t
t
d(OFF)
t
d(ON)
VOLTAGE AND DRAIN CURRENT
f
RESISTANCE vs JUNCTION TEMPERATURE
Page 5
1.0
1.1
1.2
-80 -40 0 40 80 120 160 200
0.9
T
J
, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
2
4
6
8
10
0246810
0
V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 30V
ID = 11A I
D
= 5A
WAVEFORMS IN DESCENDING ORDER:
I
D
= 3A
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
RFD3055LE, RFD3055LESM, RFP3055LE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.2
1.0
0.8
NORMALIZED GATE
THRESHOLD VOLTAGE
0.6
-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1000
C
= CGS + C
100
C
OSS
C
DS
+ C
ISS
GD
GD
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
C, CAPACITANCE (pF)
V
= 0V, f = 1MHz
GS
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
AS
V
GS
t
P
R
G
I
AS
C
RSS
DUT
0.01
= C
GD
60
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
L
+
V
DD
-
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
Page 6
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
OR Q
g(5)
V
GS
= 5V FOR
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
0
0
V
GS
= 1V FOR
L2 DEVICES
L
2
DEVICES
V
GS
= 10V
V
GS
= 10V FOR
L2 DEVICES
RFD3055LE, RFD3055LESM, RFP3055LE
Test Circuits and Waveforms (Continued)
V
DS
R
R
L
DUT
L
V
GS
R
GS
V
GS
FIGURE 18. SWITCHING TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
DS
+
V
DD
-
V
GS
+
V
DD
-
DUT
I
g(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
Page 7
RFD3055LE, RFD3055LESM, RFP3055LE
PSPICE Electrical Model
.SUBCKT RFD3055LE 2 1 3 ; rev 1/30/95
CA 12 8 3.9e-9 CB 15 14 4.9e-9 CIN 6 8 3.25e-10
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 67.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9 LGATE 1 9 5.42e-9 LSOURCE 3 7 2.57e-9
GATE
1
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.7e-2 RGATE 9 20 3.37 RLDRAIN 2 5 10 RLGATE 1 9 54.2 RLSOURCE 3 7 25.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.50e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD
LGATE
RLGATE
RGATE
9
CA
ESG
EVTEMP
+
18 22
20
S1A
12
13814
S1B
EGS EDS
DPLCAP
10
RSLC2
-
6 8
EVTHRES
+
+
6
-
S2A
13
S2B
13
+
+
6 8
-
-
5
RSLC1
51
+
5
ESLC
51
-
50
RDRAIN
16
21
-
19
8
MMED
MSTRO
CIN
15
CB
8
14
+
5 8
-
DBREAK
11
EBREAK
MWEAK
RSOURCE
RBREAK
17 18
IT
8
RVTHRES
+
17 18
-
7
RLSOURCE
RVTEMP
19
-
+
22
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))}
.MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6) .MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6) .MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81) .MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37) .MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5) .MODEL RSLCMOD RES (TC1 = 0 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -2.5) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -4) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5)
.ENDS
LDRAIN
RLDRAIN
DBODY
LSOURCE
VBAT
DRAIN
2
SOURCE
3
For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna
TM
TM
FACT™ FACT Quiet Series™
STAR*POWER is used under license
FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™
OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench
QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER
SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™
UltraFET
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Formative or In Design
First Production
Full Production
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4
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