Datasheet RFD20N03, RFD20N03SM Datasheet (Intersil)

RFD20N03, RFD20N03SM

Data Sheet July 1999 File Number

20A, 30V, 0.025 Ohm, N-Channel Power
MOSFETs

The RFD20N03 and RFD20N03SM N-Channel power
MOSFETs are manufactured using the MegaFET process.
This process which uses feature sizes approaching those of
LSI integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use in applications such as switching regulators,
switching converters, motor drivers, and relay drivers.These
transistors can be operated directly from integrated circuits.

Formerly developmental type TA49235.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD20N03 TO-251AA F20N03
RFD20N03SM TO-252AA F20N03

NOTE: When ordering,use theentire partnumber. Addthesuffix 9A to
obtain the TO-252AA variant in tape and reel, e.g., RFD20N03SM9A.

Features

• 20A, 30V

DS(ON)

= 0.025Ω

®

Model

•r

• Temperature Compensating PSPICE

• Thermal Impedance SPICE Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

4350.1

Packaging

(FLANGE)

DRAIN

S

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE
SOURCE

DRAIN

(FLANGE)

4-427

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD20N03, RFD20N03SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation (Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

D

DM

AS

D

Derate Above 25oC (Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

20

Figure 5
Figure 6

90

0.60

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V (Figure 11) 30 - - V

= VDS, ID = 250µA (Figure 10) 2 - 4 V
VDS = 30V, VGS = 0V - - 1 µA
VDS = 30V, VGS = 0V, TC = 150oC--50µA

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

ON

OFF

g(10)

g(TH)VGS

OSS

RSS

VGS = ±20V - - 100 nA

= 20A, VGS = 10V (Figure 9) - 0.022 0.025 Ω

VDD = 15V, ID≅ 20A,
RL =0.75Ω, VGS= 10V,
RGS = 9.1Ω

r

- - 60 ns

-10-ns

-30-ns

-12-ns

f

-32-ns

- - 66 ns

= 0V to 20V VDD = 15V, ID≅ 20A,
VGS = 0V to 10V - 28 40 nC

= 0V to 2V - 2.4 2.9 nC
VDS = 25V, VGS = 0V, f = 1MHz

ISS

RL = 0.75Ω
I

= 1.0mA

g(REF)

(Figure 13)

(Figure 12)

-6075nC

- 1150 - pF

- 550 - pF

- 110 - pF

(Figure 3) - - 1.66oC/W

θJC

TO-251, TO-252 - - 100

θJA

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

4-428

SD

rr

RR

ISD = 20A - - 1.25 V
ISD = 20A, dISD/dt = 100A/µs--70ns
ISD = 20A, dISD/dt = 100A/µs - - 145 nC

Typical Performance Curves

RFD20N03, RFD20N03SM

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125 175

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

JC

JC

θ

θ

0

10

175

2

+ T

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

V

DSS(MAX)

10

TJ = MAX RATED
T

C

= 30V

= 25oC

100µs

1ms

10ms
100ms
DC

100

500

VGS = 20V

100

, PEAK CURRENT (A)

DM

I

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

10

-5

10

-4

10

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

-3

10

-2

10

t, PULSE WIDTH (s)

o

25

-1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-429

C DERATE PEAK

175 - T

C

150

0

10

1

10

RFD20N03, RFD20N03SM

Typical Performance Curves

300

100

, AVALANCHE CURRENT (A)

AS

I

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

STARTING TJ = 150oC

0.001

0.01
tAV, TIME IN AVALANCHE (ms)

0.1

(Continued)

- VDD)

DSS

- VDD) + 1]

DSS

STARTING TJ = 25oC

1

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPEDINDUCTIVE SWITCHING

CAPABILITY

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

80

60

-55oC
25oC

175oC

100

80

60

40

, DRAIN CURRENT (A)

D

I

20

10

VGS = 20V

0

012345

V

= 10V

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T

= 25oC

C

VGS = 7V

VGS = 6V

VGS = 5V

FIGURE 7. SATURATION CHARACTERISTICS

2.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 10V, ID = 20A

GS

1.5

40

20

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

200

1.0

ON RESISTANCE

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

RESISTANCE vs JUNCTION TEMPERATURE

1.2

ID = 250µA

1.1

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

200

200

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

4-430

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFD20N03, RFD20N03SM

Typical Performance Curves

1800

1500

C

ISS

(Continued)

VGS = 0V, f = 1MHz
C

= CGS + C

ISS

C

= C

RSS
OSS

GD

≈ CDS + C

C

GD

10

VDD = 15V

8

GD

1200

6

900

C

OSS

600

C, CAPACITANCE (pF)

300

C

RSS

0

0102030

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

612

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 20A
ID = 15A
I

= 10A

D

= 5A

I

D

18 24 300

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. GATECHARGE WAVEFORMSFOR CONSTANT

GATE CURRENT

Test Circuits and Waveforms

V

DS

BV

DSS

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

L

R

G

+

V

DD

-

DUT

t

P

I

AS

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

I

g(REF)

Q

g(TOT)

V

DS

Q

g(10)

V

GS

Q

g(TH)

VGS = 10V

0

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

VGS= 20V

4-431

RFD20N03, RFD20N03SM

Test Circuits and Waveforms

V

V

GS

R

GS

V

GS

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

(Continued)

DS

R

L

DUT

t

ON

t

d(ON)

t

V

DS

+

V

DD

-

0

V

GS

0

90%

10%

r

10%

50%

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

4-432

RFD20N03, RFD20N03SM

PSPICE Electrical Model

SUBCKT RFD20N03, RFD20N03SM 2 1 3 ; rev 28 Jul 97

CA 12 8 1.3e-9
CB 15 14 1.3e-9
CIN 6 8 9.9e-10

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.15
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1.00e-9

GATE

1

LGATE 1 9 3.57e-9
LSOURCE 3 7 4.25e-9

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5e-4
RGATE 9 20 1.24
RLDRAIN 2 5 10
RLGATE 1 9 28.6
RLSOURCE 3 7 26.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.2e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP
+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

S2A

S2B

5

RSLC1

51

+

5

ESLC

51

-

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

+

8

14

5
8

-

MMED

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),3))}
.MODEL DBODYMOD D (IS = 9e-13 RS = 6.4e-3 IKF=7.4 TIKF=0.005 N=1.02 TRS1 = 3.5e-3 TRS2 =-1e-5 CJO = 1.78e-9 TT = 4.0e-8 M = 0.4053)

.MODEL DBREAKMOD D (RS = 0.1 N=3.5 IKF=-1e-3 TRS1 = -1e-3 TRS2 =1e-6)
.MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 0.62)
.MODEL MMEDMOD NMOS (VTO = 3.17 KP = 1.3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.24)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.009 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 8e-4 TC2 = 4.5e-7)
.MODEL RDRAINMOD RES (TC1 = 3.5e-2 TC2 = 4.5e-4)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -1.2e-3 TC2 = -2e-5)
.MODEL RVTEMPMOD RES (TC1 = -3.5e-3 TC2 = 1e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.60 VOFF= -2.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.50 VOFF= -8.60)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 0.30)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.30 VOFF= 0.00)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

4-433

SPICE Thermal Model

REV 28 July 97

RFD20N03, RFD20N03SM

CTHERM1 7 6 9.9e-7
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 2.2e-3
CTHERM4 4 3 5.7e-3
CTHERM5 3 2 7.5e-2
CTHERM6 2 1 5.4e-1

RTHERM1 7 6 8e-3
RTHERM2 6 5 2.3e-2
RTHERM3 5 4 9.0e-2
RTHERM4 4 3 6.9e-1
RTHERM5 3 2 6.1e-1
RTHERM6 2 1 8.0e-2

RFD20N03, RFD20N03SM

RTHERM1

RTHERM2

JUNCTION

7

CTHERM1

6

CTHERM2

5

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

CASE

1

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

4-434