Datasheet RFD16N06LESM Datasheet (Fairchild Semiconductor)

RFD16N06LESM

Data Sheet September 2002

16A, 60V, 0.047 Ohm, Logic Level,
N-Channel Power MOSFETs

These are N-Channel power MOSFETs manu factured using
a modern process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regu la tors, switching converters, motor drivers,
relay drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V to 5V range, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.

Formerly developmental type TA49027.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD16N06LESM* TO-252AA 16N06LE

NOTE: When ordering, use the entire part number. Add suffix 9A to
obtain the TO-25 2AA v arian t in the t ape and re el, i.e . ,
RFD16N06LESM9A.

*RFD16N06LESM is only av a ilabe in tape and re el.

Features

• 16A, 60V

•r

• Temperature Compensating PSPICE

• Can be Driven Directly from CMOS, NMOS, TTL
Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.047Ω

DS(ON)

Components to PC Boards”

®

Model

Symbol

D

G

S

Packaging

JEDEC TO-252AA

DRAIN (FLANGE)

GATE

SOURCE

©2002 Fairchild Semiconductor Corporation RFD16N06LESM Rev. B1

RFD16N06LESM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD16N06LESM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drai n C u rr e n t (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

DSS

DGR

GS

D

DM

AS

D

, T

J

STG

Refer to Peak Current Curve

Maximum Tem perature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

+10, -8 V

16

Refer to UIS Cu r ve

90

0.606

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)

Gate Charge at 5V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSS

DSS

GSS

ON

r

f

OFF

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

ID = 250µA, VGS = 0V, Figure 11 60 - - V
VGS = VDS, ID = 250µA, Figure 10 1 - 3 V
VDS = 55V, VGS = 0V - - 1 µA
V

= 50V, VGS = 0V, TC = 150oC - - 250 µA

DS

VGS = +10, -8V - - 10 µA

= 16A, VGS = 5V - - 0.047 Ω

VDD = 30V, ID = 16A, RL = 1.88Ω,
V

= 5V, RGS = 5Ω

GS

Figures 16, 17

- - 100 ns

-11- ns

-60- ns

-48- ns

-35- ns

- - 115 ns

VGS = 0V to 10V VDD = 48V,

I

= 16A, RL = 3Ω

VGS = 0V to 5V - 29 35 nC

D

Figures 18, 19

-5162nC

VGS = 0V to 1V - 1.8 2.6 nC
VDS = 25V, VGS = 0V,

f = 1MHz
Figure 12

- 1350 - pF

- 300 - pF

-90- pF

- - 1.65

TO-251AA, TO-252AA - - 80

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse Test: Pulse Width ≤ 300µs , Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature.

©2002 Fairchild Semiconductor Corporation RFD16N06LESM Rev. B1

ISD = 16A - - 1.5 V
ISD = 16A, dISD/dt = 100A/µs - - 125 ns

RFD16N06LESM

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100

0

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 1. NORMALIZED PO WER DISSIP ATION vs CASE

TEMPERATURE

200

100

TC = 25oC

T

= MAX RATED

J

100µs

20

15

10

, DRAIN CURRENT (A)

D

5

I

0

1750

25

50

75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

500

TC = 25oC

VGS = 10V

100

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

o

25

(

C DERATE PEAK

175 - T

C

150

)

10

DRAIN CURRENT (A)

D,

I

1

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

110

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

V

DSS

MAX = 60V

1ms

10ms

100

VGS = 5V

, PEAK CURRENT CAPABILITY (A)

DM

I

10

-6

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

-5

10

10

t, PULSE WIDTH (s)

-2

-3

10

10

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. PEAK CURRENT CAPABILITY

100

STAR TING T
STARTING TJ = 150oC

10

AVALANCHE CURRENT (A)

If R = 0

,

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

= 25oC

J

- VDD) +1]

100

T

=25oC

C

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

0 1.5 3.0 4.5 6.0 7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

10-110

VGS = 5V

V

V

V

0

GS

GS

GS

= 4.5V

= 4V

= 3V

1

10

FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING FIGURE 6. SATURATION CHARACTERISTICS

©2002 Fairchild Semiconductor Corporation RFD16N06LESM Rev. B1

RFD16N06LESM

Typical Performance Curves Unless Otherwise Specified (Continued)

100

V

= 15V

DD

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

80

60

40

-55oC

25oC

175oC

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = 5V, ID = 16A

2.0

1.5

1.0

ON RESISTANCE

20

, ON STATE DRAIN CURRENT (A)

D(ON)

I

0

0

V

GS

3.0

4.5

, GATE TO SOURCE VOLTAGE (V)

6.0

7.51.5

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40

04080

T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. NORMALIZ ED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0

1.5

1.0

I

V

= VDS,

GS

= 250µA

D

2.0

1.5

1.0

ID = 250µA

120

160

200

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80

-40

04080

T

, JUNCTION TEMPERATURE (oC)

J

160

120 200

FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs

TEMPERATURE

2000

C

1500

1000

500

C, CAPACITANCE (pF)

0

0 5 10 15 20 25

ISS

VGS = 0V, f = 1MHz

C

= CGS + C

ISS

C

= C

RSS

C

≈ CDS + C

C

OSS

C

RSS

OSS

GD

GD

GD

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED DRAIN T O SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

VDD = BV

DSS

VDD = BV

DSS

45

30

0.75 BV

0.50 BV

I

GREF()

--------------------- -

20

I

G ACT()

0.25 BV

15

DRAIN TO SOURCE VOLTAGE (V)

,

DS

V

0

0.75 BV

DSS

0.50 BV

DSS

0.25 BV

DSS

RL = 3.75Ω
I

= 0.65mA

G(REF)

V

= 5V

GS

t, TIME (µs)

DSS
DSS
DSS

80

I

GREF()

--------------------- -

I

GACT()

5.00

3.75

2.50

1.25

0

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 12. NORMALIZED SWITCHI NG W A VEF ORMS FOR

CONSTANT GATE CURRENT

GATE TO SOURCE VOLTAGE (V)

,

GS

V

©2002 Fairchild Semiconductor Corporation RFD16N06LESM Rev. B1

RFD16N06LESM

Test Circuits and Waveforms

V

DS

BV

DSS

t

AV

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

L

R

G

+

V

DD

-

t

P

I

AS

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

V

DS

V

DD

t

t

d(ON)

90%

ON

50%

10%

t

r

PULSE WIDTH

V

DS

R

DUT

L

+

V

DD

-

V

GS

R

GS

V

GS

V

DS

V

GS

10%

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

Q

g(10)

V

GS

V

= 2V

GS

0

= 1V FOR

V

GS
2

DEVICES

L

Q

g(TH)

V

DS

OR Q

Q

g(5)

g(TOT)

V

GS

V

GS
2

L

DEVICES

t

OFF

t

d(OFF)

90%

50%

= 10V
= 5V FOR

t

f

10%

V

V

= 10V FOR

GS
2

DEVICES

L

GS

90%

= 20V

I

g(REF)

0

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS

©2002 Fairchild Semiconductor Corporation RFD16N06LESM Rev. B1

PSPICE Electrical Model

SUBCKT RFD16N06LESM 2 1 3 ; rev 8/2/93

CA 12 8 1.46e-9
CB 15 14 1.46e-9
CIN 6 8 1.0e-9

RFD16N06LESM

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 66.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 5.5e-9
LSOURCE 3 7 4.4e-9

GATE

1

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 3.6
RLDRAIN 2 5 10
RLGATE 1 9 55
RLSOURCE 3 7 44
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.45e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

S2A

S2B

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

5

51

MSTRO

14

5
8

RSLC1

51

+

ESLC

-

50
RDRAIN

16

21

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

11

+

17
18

DBODY

DRAIN

2

-

LSOURCE

7

RLSOURCE

RVTEMP
19

SOURCE

3

-

VBAT

+

22

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR( V(5,51)/(1e-6*100),3.5 ))}
.MODEL DBODYMOD D (IS = 6.3e-13 RS = 6.8e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI = 4.3 CJO = 1.28e-9 TT = 5.1e-8 M = 0.5)

.MODEL DBREAKMOD D (RS = 2.9e-1 TRS1 = 1e-4 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 9.5e-10 IS = 1e-30 N = 10 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 2.10 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL MSTROMOD NMOS (VTO = 2.45 KP = 60.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.79 KP = 0.13 IS = 1e-30 N = 10 TO X = 1 L = 1u W = 1u RG = 36 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.2e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.3e-2 TC2 = 3.1e-5)
.MODEL RSLCMOD RES (TC1 = 5.5e-3 TC2 = 7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 8e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.8 VOFF= -2.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.8 VOFF= -4.8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.6 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.6)

.ENDS

For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2002 Fairchild Semiconductor Corporation RFD16N06LESM Rev. B1

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.

ACEx™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™

2

CMOS™

E
EnSigna™

FACT™
FACT Quiet Series™

®

FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™

2

C™

I
Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™

ImpliedDisconnect™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC

®

OPTOPLANAR™

PACMAN™
POP™
Power247™
PowerTrench

®

QFET™
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
SILENT SWITCHER
SMART START™

SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET

®

VCX™

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.

As used herein:

1. Life support devices or systems are devices or syst em s
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I1