Datasheet RFD16N06LE, RFD16N06LESM Datasheet (Intersil)

RFD16N06LE, RFD16N06LESM

Data Sheet October 1999

16A, 60V, 0.047 Ohm, Logic Level,
N-Channel Power MOSFETs

These are N-Channel power MOSFETs manufacturedusing
a modern process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
relaydriversand emitter switches forbipolar transistors.This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V to 5V range, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.

Formerly developmental type TA49027.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD16N06LE TO-251AA 16N06L
RFD16N06LESM TO-252AA 16N06LE

NOTE: When ordering, use the entire part number. Add suffix 9Ato
obtain the TO-252AA variant in the tape and reel, i.e.,
RFD16N06LESM9A.

File Number 3628.3

Features

• 16A, 60V

DS(ON)

= 0.047Ω

®

Model

•r

• Temperature Compensating PSPICE

• Can be Driven Directly from CMOS, NMOS, TTL
Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN (FLANGE)

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN (FLANGE)

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademgark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD16N06LE, RFD16N06LESM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD16N06LE, RFD16N06LESM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

+10, -8 V

16

Refer to UIS Curve

90

0.606

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSS

GS(TH)

DSS

ID = 250µA, VGS = 0V, Figure 11 60 - - V
VGS = VDS, ID = 250µA, Figure 10 1 - 3 V
VDS = 55V, VGS = 0V - - 1 µA

VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)

Gate Charge at 5V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSS

ON

r

f

OFF

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

VGS = +10, -8V - - 10 µA

= 16A, VGS = 5V - - 0.047 Ω

VDD = 30V, ID = 16A, RL = 1.88Ω,
VGS = 5V, RGS = 5Ω
Figures 16, 17

- - 100 ns

-11- ns

-60- ns

-48- ns

-35- ns

- - 115 ns
VGS = 0V to 10V VDD = 48V,
VGS = 0V to 5V - 29 35 nC

ID = 16A, RL = 3Ω
Figures 18, 19

-5162nC

VGS = 0V to 1V - 1.8 2.6 nC
VDS = 25V, VGS = 0V,

f = 1MHz
Figure 12

- 1350 - pF

- 300 - pF

-90- pF

- - 1.65
TO-251AA, TO-252AA - - 80

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse Test: Pulse Width ≤ 300µs, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature.

2

ISD = 16A - - 1.5 V
ISD = 16A, dISD/dt = 100A/µs - - 125 ns

RFD16N06LE, RFD16N06LESM

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100

0

0

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

200

100

TC = 25oC

T

= MAX RATED

J

100µs

175

20

15

10

, DRAIN CURRENT (A)

D

5

I

0

25

50

75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

500

TC = 25oC

VGS = 10V

100

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

25

o

C DERATE PEAK

175 - T

(

C

150

)

10

DRAIN CURRENT (A)

D,

I

1

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

110

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

V

DSS

MAX = 60V

1ms

10ms

100

VGS = 5V

, PEAK CURRENT CAPABILITY (A)

DM

I

10

10-610

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

-5

10

10

t, PULSE WIDTH (s)

-2

-3

10

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. PEAK CURRENT CAPABILITY

100

STARTING T
STARTING TJ = 150oC

10

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

= 25oC

J

- VDD) +1]

100

TC =25oC

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

0 1.5 3.0 4.5 6.0 7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

10-110

VGS = 5V

V

V

V

0

GS

GS

GS

= 4.5V

= 4V

= 3V

1

10

FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING FIGURE 6. SATURATION CHARACTERISTICS

3

RFD16N06LE, RFD16N06LESM

Typical Performance Curves Unless Otherwise Specified (Continued)

100

V

= 15V

DD

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

80

60

40

20

, ON STATE DRAIN CURRENT (A)

D(ON)

I

0

0

V

GS

-55oC

3.0

, GATE TO SOURCE VOLTAGE (V)

25oC

4.5

6.0

175oC

7.51.5

2.5

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = 5V, ID = 16A

04080

, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE8. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0

1.5

1.0

VGS= VDS,

I

= 250µA

D

2.0

1.5

1.0

ID = 250µA

120

160

200

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80

-40

04080

TJ, JUNCTION TEMPERATURE (oC)

160

120 200

FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGEvs

TEMPERATURE

2000

C

1500

1000

500

C, CAPACITANCE (pF)

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

ISS

VGS = 0V, f = 1MHz

C

= CGS + C

ISS

C

= C

RSS

C

≈ CDS + C

C

OSS

C

RSS

OSS

GD

GD

GD

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

45

30

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

I

GREF()

--------------------- -

20

I

GACT()

DSS

0.75 BV

0.50 BV

0.25 BV
RL = 3.75Ω

I
VGS = 5V

DSS
DSS
DSS

= 0.65mA

G(REF)

t, TIME (µs)

0.75 BV

0.50 BV

0.25 BV

VDD = BV

DSS
DSS
DSS

I

GREF()

--------------------- -

80

I

GACT()

DSS

5.00

3.75

2.50

1.25

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 12. NORMALIZED SWITCHING WAVEFORMSFOR

CONSTANT GATE CURRENT

, GATE TO SOURCE VOLTAGE (V)

GS

V

4

RFD16N06LE, RFD16N06LESM

Test Circuits and Waveforms

V

DS

BV

DSS

t

AV

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

L

R

G

+

V

DD

-

t

P

I

AS

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

V

DS

V

DD

t

t

d(ON)

90%

ON

50%

10%

t

r

PULSE WIDTH

V

DS

R

DUT

L

+

V

DD

-

V

GS

R

GS

V

GS

V

DS

V

GS

10%

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

Q

g(TOT)

V

DS

Q

OR Q

g(10)

V

GS

= 1V FOR

V

GS

g(5)

V

GS

VGS= 5V FOR

2

L

DEVICES

L2 DEVICES

Q

g(TH)

t

d(OFF)

90%

= 10V

t

OFF

t

f

10%

50%

VGS= 20V
= 10V FOR

V

GS

L2 DEVICES

90%

I

g(REF)

0

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS

5

RFD16N06LE, RFD16N06LESM

PSPICE Electrical Model

SUBCKT RFD16N06LE 2 1 3 ; rev 8/2/93

CA 12 8 1.46e-9
CB 15 14 1.46e-9
CIN 6 8 1.0e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 66.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 5.5e-9
LSOURCE 3 7 4.4e-9

GATE

1

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 3.6
RLDRAIN 2 5 10
RLGATE 1 9 55
RLSOURCE 3 7 44
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.45e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP

+

18
22

20

S1A

12

13

8

S1B

EGS EDS

-

+

-

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CIN

CB

-

+

-

5

51

5

51

MSTRO

14

5
8

RSLC1

+

ESLC

-

50
RDRAIN

16

21

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17
18

-

7

S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),3.5))}
.MODEL DBODYMOD D (IS = 6.3e-13 RS = 6.8e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI = 4.3 CJO = 1.28e-9 TT = 5.1e-8 M = 0.5)

.MODEL DBREAKMOD D (RS = 2.9e-1 TRS1 = 1e-4 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 9.5e-10 IS = 1e-30 N = 10 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 2.10 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL MSTROMOD NMOS (VTO = 2.45 KP = 60.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.79 KP = 0.13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.2e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.3e-2 TC2 = 3.1e-5)
.MODEL RSLCMOD RES (TC1 = 5.5e-3 TC2 = 7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 8e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.8 VOFF= -2.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.8 VOFF= -4.8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.6 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.6)

.ENDS

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP
19

-

VBAT

+

22

DRAIN

2

SOURCE

3

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

NOTE:

6

RFD16N06LE, RFD16N06LESM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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