Datasheet RFD16N06, RFD16N06SM Datasheet (Intersil)

Page 1
Semiconductor
/ j
/
/
/
September 1998
RFD16N06,
RFD16N06SM
16A, 60V, 0.047 Ohm,
N-Channel Power MOSFET
[ /Title (RFD16 N06, RFD16 N06SM)
Sub-
ect (16A, 60V,
0.047 Ohm, N-Chan­nel Power MOS­FET)
Author ()
Key­words (Harris Semi­conduc­tor, N­Chan­nel Power MOS­FET, TO­251AA, TO­252AA)
Cre-
Features
• 16A, 60V
•r
Temperature Compensating
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.047
DS(ON)
o
C Operating Temperature
Components to PC Boards”
PSPICE Model
Ordering Information
P AR T NUMBER P ACKAGE BRAND
RFD16N06 TO-251AA F16N06 RFD16N06SM TO-252AA F16N06
NOTE: When ordering, use the entire part number. Add suffix 9A to ob­tain the TO-252AA variant in tape and reel, i.e., RFD16N06SM9A.
Packaging
JEDEC TO-251AA JEDEC TO-252AA
SOURCE
DRAIN
DRAIN
(FLANGE)
GATE
Description
These N-Channel power MOSFETs are manufactured using the MegaFET process. This process which uses feature sizes approaching those of LSI integrated circuits, gives opti­mum utilization of silicon, resulting in outstanding perfor­mance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits.
Formerly developmental type TA09771.
Symbol
DRAIN
GATE
SOURCE
DRAIN (FLANGE)
GATE
SOURCE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright
© Harris Corporation 1998
5-1
File Number 4087.1
Page 2
RFD16N06, RFD16N06SM
Absolute Maximum Ratings T
= 25oC
C
RFD16N06, RFD16N06SM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (RGS = 20k) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
DSS
DGR
DM
GS
AS
D
Refer to Peak Current Curve
D
Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maxim um Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
60 V 60 V 16
±20 V
Refer to UIS Curve
72
0.48
-55 to 175
300 260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. TJ= 25oC to 150oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V Zero Gate Voltage Drain Current I
DSSID
GS(TH)VGS
DSS
= 250µA, VGS = 0V 60 - - V
= VDS, ID = 250µA2-4V VDS = Rated BV VDS = 0.8 x Rated BV
, VGS = 0V - - 1 µA
DSS
DSS
,
--25µA
TC = 150oC
Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r
DS(ON)ID
Turn-On Time t Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t Total Gate Charge Q
g(TOT)VGS
Gate Charge at 10V Q Threshold Gate Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
GSS
ON
OFF
g(10)
g(TH)VGS
OSS
RSS
VGS = ±20V - - ±100 nA
= 16A, VGS = 10V (Figure 9) - - 0.047
VDD = 30V, I VGS = 10V, RG = 25 (Figures 13, 16, 17)
r
8A, R
D
= 3.75,
L
- - 65 ns
-14- ns
-30- ns
-55- ns
f
-30- ns
- - 125 ns
= 0V to 20V VDD = 48V, ID = 16A, VGS = 0V to 10V - - 45 nC
RL = 3Ω, I (Figures 18, 19)
G(REF)
= 0.8mA
- - 80 nC
= 0V to 2V - - 2.2 nC VDS = 25V, VGS = 0V, f = 1MHz - 900 - pF
ISS
- 325 - pF
- 100 - pF
θJC
TO-251 and TO-252 - - 100oC/W
θJA
- - 2.083oC/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V Diode Reverse Recovery Time t
NOTES:
2. Pulse test: pulse width 300ms, duty cycle 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
ISD = 16A - - 1.5 V
SD
ISD = 16A, dISD/dt = 100A/µs - - 125 ns
rr
5-2
Page 3
Typical Performance Curves
RFD16N06, RFD16N06SM
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
TC, CASE TEMPERATURE (oC)
125
150
FIGURE 1. NORMALIZED POWER DISSIP A TION vs CASE
TEMPERA TURE
2
1
0.5
0.2
0.1
0.1
, NORMALIZED
Z
JC
θ
THERMAL IMPEDANCE
0.01 10
0.05
0.02
0.01
-5
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
20
16
16
12
8
, DRAIN CURRENT (A)
D
I
4
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
P
DM
t
1
t
2
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-2
10
-1
10
1/t2
x R
JC
JC
θ
θ
0
10
+ T
175
C
1
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300
200
100
, PEAK CURRENT (A)
DM
TRANSCONDUCTANCE
I
MAY LIMIT CURRENT IN THIS REGION
10
-5
10
VGS = 20V
-4
10
FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:
VGS = 10V
-3
10
t, PULSE WIDTH (s)
I = I
-2
10
o
C DERATE PEAK
175 - T
25
150
-1
10
100
10
, DRAIN CURRENT (A)
D
I
OPERATION IN THIS AREA MAY BE LIMITED BY r
1
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
DS(ON)
TC = 25oC
TJ = MAX RATED
100µs
1ms
10ms 100ms
DC
10
100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
5-3
C
TC = 25oC
0
10
1
10
Page 4
RFD16N06, RFD16N06SM
Typical Performance Curves
100
Idm
10
STARTING TJ = 150oC
If R = 0
, AVALANCHE CURRENT (A)
tAV = (L)(IAS)/(1.3 RATED BV
AS
I
If R 0
= (L/R)ln[(IAS*R)/(1.3 RATED BV
t
AV
1
tAV, TIME IN AVALANCHE (ms)
DSS
(Continued)
STARTING TJ = 25oC
- VDD)
- VDD) +1]
DSS
1100.01 0.1
NOTE: Refer to Harris Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
50
VDD= 15V
PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX
40
30
-55oC
175oC
25oC
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
0
= 20V
V
GS
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
= 10V
V
GS
PULSE DURATION = 250µs, TC = 25oC
VGS = 8V
2
FIGURE 7. SATURATION CHARACTERISTICS
2.5
PULSE DURATION = 250µs, VGS = 10V, ID = 16A
2.0
1.5
= 7V
V
GS
= 6V
V
GS
V
= 5V
GS
= 4.5V
V
GS
3
4
20
10
, DRAIN TO SOURCE CURRENT (A)
DS(ON)
I
0
0468102
VGS, GATE TO SOURCE VOLTAGE (V)
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0 ID = 250µA
1.5
1.0
0.5
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 , JUNCTION TEMPERATURE (oC)
T
J
200
2.0 VGS = VDS, ID = 250µA
1.5
1.0
NORMALIZED GATE
0.5
THRESHOLD VOLTAGE
0
-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
200
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
5-4
Page 5
RFD16N06, RFD16N06SM
Typical Performance Curves
1600
1200
C
C
C
ISS
OSS
RSS
800
C, CAPACITANCE (pF)
400
0
0 5 10 15 20 25
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
(Continued)
VGS = 0V, f = 1MHz C
= CGS + C C C
ISS RSS OSS
= C
C
GD
DS
GD
+ C
GS
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
DUT
+
V
-
60
45
30
15
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
0
VDD = BV
I
G REF()
--------------------- -
20
I
GACT()
DSS
0.75 BV
0.50 BV
0.25 BV
RL = 3.75 I
= 0.8mA
G(REF)
= 10V
V
GS
t, TIME (µs)
DSS DSS DSS
80
V
DD
NOTE: Refer to Harris Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
BV
DSS
t
P
I
AS
DD
= BV
DSS
I
G REF()
--------------------- -
I
GACT()
V
DS
10
7.5
5.0
2.5 , GATE TO SOURCE VOLTAGE (V)
GS
V
0
V
DD
0V
P
I
AS
0.01
0
t
AV
t
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
d(ON)
90%
t
ON
50%
t
10%
r
PULSE WIDTH
t
d(OFF)
90%
V
DS
R
DUT
L
+
V
DD
-
V
DS
0
V
GS
10%
0
V
GS
R
GS
V
GS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
t
OFF
50%
t
f
90%
10%
5-5
Page 6
RFD16N06, RFD16N06SM
Test Circuits and Waveforms
V
DS
V
GS
I
g(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORM
(Continued)
R
L
DUT
V
DD
+
V
DD
­VGS= 2V
0
I
g(REF)
0
V
GS
Q
Q
g(TH)
V
DS
g(10)
Q
g(TOT)
VGS= 20V
VGS = 10V
5-6
Page 7
PSPICE Electrical Model
.SUBCKT RFD16N06 2 1 3 ; rev 10/31/94 CA 12 8 1.788e-10 CB 15 14 1.875e-10 CIN 6 8 8.33e-10
DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 64.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1
IT 8 17 1
GATE
LDRAIN 2 5 1e-9 LGATE 1 9 4.56e-9 LSOURCE 3 7 4.13e-9
MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 0.4e-3 RGATE 9 20 3.0 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 21.5e-3 RVTO 18 19 RVTOMOD 1
1
LGATE
RFD16N06, RFD16N06SM
DPLCAP
RSCL2
51
6 8
+
6
RIN
S2A
13
S2B
13
+
6 8
VTO
15
EDS
CIN
CB
16
+
+
5 8
9
RGATE
10
ESG
EVTO
20
+
18
8
S1A
12
13814
S1B
CA
EGS
5
+
5
50 RDRAIN
MOS1
14
RSCL1 51
ESCL
21
8
DBREAK
EBREAK
MOS2
RSOURCE
17
11
+
17 18
RBREAK
7
IT
LDRAIN
DBODY
LSOURCE
18
RVTO
19
VBAT
+
DRAIN
2
3 SOURCE
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1 VTO 21 6 0.82
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/94,7))}
.MODEL DBDMOD D (IS = 2.5e-13 RS = 7.1e-3 TRS1 = 3.04e-3 TRS2 = -10e-6 CJO = 1.12e-9 TT = 5.6e-8) .MODEL DBKMOD D (RS = 2.51e-1 TRS1 = -6.57e-4 TRS2 = 1.66e-6) .MODEL DPLCAPMOD D (CJO = 6.1e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.96 KP = 16.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -7.19e-7) .MODEL RDSMOD RES (TC1 = 5.45e-3 TC2 = 1.66e-5) .MODEL RSCLMOD RES (TC1 = 1.25e-3 TC2 = 17e-6) .MODEL RVTOMOD RES (TC1 = -5.15e-3 TC2 = -4.83e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.25 VOFF= -3.25) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.25 VOFF= -5.25) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.56 VOFF= 5.56) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.56 VOFF= 0.56)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
5-7
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