Datasheet RFD16N05LSM9A Specification

Is Now Part of

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RFD16N05LSM

Data Sheet

N-Channel Logic Level Power MOSFET

50V, 16A, 47 mΩ

These are N- Channel logic level power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic level (5V) driving sources in applications
such as programmable controllers, switching regulators,
switching co n verters, motor relay drivers and emitter
switches for bipolar transistors. This performance is
accomplished through a special gate oxide design which
provides full rated conductance at gate biases in the 3V to
5V range, thereby facilitating true on-off power control
directly from logic circuit supply voltages.

Formerly developmental type TA09871.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD16N05LSM9A TO-252AA RFD16N05LSM

September 2013

Features

• 16A, 50V

•r

• UIS SOA Rating Curve (Single Pulse)

• Design Optimized for 5V Gate Drives

• Can be Driven Directly from CMOS, NMOS, TTL Circuits

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Majority Carrier Device

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.047Ω

DS

(ON)

Components to PC Boards”

Symbol

Packaging

D

G

S

JEDEC TO-252AA

DRAIN (FLANGE)

GATE

SOURCE

©2003 Fairchil

d Semiconductor Corporation

RFD16N05LSM Rev. C1

RFD16N05LSM

Absolu

te Maximum Ratings

TC = 25oC, Unless

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

lsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pu

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Otherwise Specified

RFD16N05LSM9A

DS

DGR

D

DM

GS

D

50 V
50 V
16

45

±10 V

60

0.48

, T

J

STG

L

pkg

-55 to 150

300
260

UNITS

A
A

W

W/oC

o

C

o

C

o

C

NOTE:

1. T

= 25oC to 125oC.

J

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)

Gate Charge at 5V Q
Threshold Gate Charge Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

(ON)

r

f

g(5)

g(TH)

θJC
θJA

= 250mA, VGS = 0V, Figure 10 50 - - V

= VDS, ID = 250mA, Figure 9 1 - 2 V

VDS = 40V, VGS = 0V - - 1 µA

T

= 150oC --50µA

C

V

= ±10V, VDS = 0V - - 100 nA

GS

= 16A, VGS = 5V - - 0.047 Ω

I

=

16A, V

D

VDD = 25V, ID = 8A,
V

GS =

Figures 15, 16

=

4V - - 0.056 Ω

GS

5V, RGS = 12.5Ω

--60ns

-14 - ns

-30 - ns

-4

2 - ns

-14 - ns

--100ns

VGS = 0V to 10V VDD = 40V,

= 16A,

I

VGS = 0V to 5V - - 45 nC
VGS = 0V to 1V - - 3 nC

D

= 2.5Ω

R

L

Figures 17, 18

--80nC

- - 2.083

o

C/W

--100oC/W

e to Drain Diode Specifications

Sourc

AMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

PAR

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

SD
rr

ISD = 16A - -

NOTES:

2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature.

©2003 Fai

rchild Semiconductor Corporation

ISD = 16A,

dI

/dt =

100A/µs - - 125 ns

SD

1.5 V

RFD16N05LSM Rev. C1

Typical Performance Curves

s Otherwise Specified

Unles

RFD16N05LSM

1.2

1.0

0.8

0.6

0.4

ER DISSIPATION MULTIPLIER

0.2

POW

0

0 25

50 75 100 150

TC, CASE TE

MPERATURE (

125

o

C)

FIGURE 1. NORMALIZED POWER DISSIPA TION vs CASE

TEMPERATURE

2

10

TC = 25oC

X RATED

TJ = MA

INUOUS

10

NT (A)

ID MAX CONT

20

15

A)

10

, DRAIN CURRENT (

5

D

I

0

25 50

75 100 150

T

, CASE TE

C

MPERATURE (

o

C)

125

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

2

10

Idm

STAR T

ING T

= 25oC

J

ATION IN THIS AREA

1

, DRAIN CURRE

D

I

0.1

OPER
LIMITED BY r

1

DS(ON)

VDS, DRAIN TO

10

SOURCE VOLTAGE (V)

DC

10

ALANCHE CURRENT (A)

If

R = 0

, AV

tAV = (L

AS

I

R ≠ 0

If
t

AV

2

10

1

START

= (L

ING T

)(I

AS

/R)ln[(I

)/(

= 150oC

J

1.3 RATED BV

*R)

/(1.3 RATED BV

AS

E IN AVALANCHE (ms)

tAV, TIM

DSS

- VDD)

DSS

- VDD) +1]

1100.01 0.10

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA

(SINGLE PULSE UIS SOA)

SOURCE CURRENT (A)

, DRAIN TO

DS

I

45

30

15

0

0

VGS = 10V

VGS = 5V

1.5
VDS, DRAIN TO

VGS = 4V

3.0 4.5 7.5

PULSE DURAT
DUTY CYCLE = 0

SOURCE VOLTAGE (V)

TC = 25oC

ION = 80µs

.5% MAX.

VGS = 3V

VGS = 2V

6.0

45

V

= 15V

DS

PULSE DURA T
DUTY CYCLE = 0.5% MAX

30

SOURCE ON CURRENT (A)

15

, DRAIN TO

0

DS(ON)

I

0 3.0 4.5 6.01.5

ION = 80µs

VGS, GAT

E TO S OURCE VOLTAGE (V)

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

©2003 Fai

rchild Semiconductor Corporation

RFD16N05LSM Rev. C1

RFD16N05LSM

Typical Performance Curves

1.4
ID = 16V

1.3

VDS = 15V

2

1.

Unles

PULSE DURA

CYCLE = 0.5% M AX.

DUTY

s Otherwise Specified (Continued)

TION = 80

1.1

ANCE

1.0

0.9

0.8

ON RESIST

ALIZED DRAIN TO SOURCE

0.7

0.6

NORM

0.5

547

VGS, GA

TE TO SOURCE VOLTAGE (V)

6

FIGURE 7. DRAIN TO SOURCE ON RESIST ANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.4
ID = 250µA

VGS = V

1.3

1.

2

1

1.

ED GATE

1.0

DS

OLD VOLTAGE

0.

9

NORMALIZ

0.8

THRESH

7

0.

0.6

-50

0 200

T

J

50 100 150

, JUNCTIO

N TEMPERA TURE (

o

C)

FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION

TEMPERATURE

2.5

µ

s

ID = 16A

PULSE DURAT
DUTY CYCLE = 0.5% MAX.

2.0

1.5

ANCE

ION = 80µs

1.0

ZED DRAIN TO SOURCE

ON RESIST

5

0.

NORMALI

0

-50

0

T

J

50

, JUNCT

ION TEMPERATURE (

100 200

0

15

o

C)

FIGURE 8. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.4
ID = 250µA

1.2

LTAGE

1.0

0.8

ED DRAIN TO SOURCE

BREAKDOWN VO

0.6

NORMALIZ

0

0150

T

J

50-50

, JUNCTION

100 200

TEMPERATURE (

o

C)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

2000

V

= 0V

GS

f = 1MHz

1600

C

C

C

ISS

OSS

RSS

1200

ITANCE (pF)

800

C, CAPAC

400

0

0 10

5

V

DRAIN TO SOURCE V

DS,

C

= CGS + C
C
C

ISS
RSS
OSS

= C
≈ CDS + C

GD

GD

GD

152025

OLTAGE (V)

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

©2003 Fai

rchild Semiconductor Corporation

10

8

6

4

2

0

SOURCE VOLTAGE (V)

, DRAIN TO
V

12

DS

37.5

50

VDD = BV

25

RL = 3.

125Ω, V

I

REF)

G(

PLATEAU VOLTAGES IN

CENDI

DES

VDD = BV
VDD = 0.7

DSS

VDD = 0.5
VDD = 0.2

GATE

SOURCE

VOL

GS

= 0.60m

NG ORD

DSS

5 BV
0 BV
5 BV

TAGE

= 5V

A

ER:

DSS
DSS
DSS

VDD = BV

DSS

.5

0

I

GREF()

20

------------------- ----- ­I

GACT()

DRAIN SOURCE

VOLTAGE

t, TIME (µs)

I

GREF()

80

------------------ ------ ­I

GACT()

FIGURE 12. NORMALIZED SWITCHING W A V EFORMS FOR

CONSTANT GATE CURRENT

RFD16N05LSM Rev. C1

E TO SOURCE VOLTAGE (V)

, GAT

GS

V

Test Circuits and Waveforms

VARY

t

OBTAIN

TO

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

RFD16N05LSM

V

DS

BV

DSS

L

+

V

DD

-

DUT

I

AS

0.01Ω

0

t

P

I

AS

t

AV

V

DS

V

DD

FIGURE 13

. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

)

d(ON

t

R

L

+

V

R

G

DD

-

V

DS

90%

0

r

10%

DUT

V

GS

V

GS

10%

0

%

50

PULSE WIDTH

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS

V

DS

ATED

(ISOL
SUPPLY)

SAME TYPE
AS DUT

V

DD

Q

g(TO

T)

Q

gd

Q

gs

BAT

12V

TERY

0.2µF

50kΩ

CURRENT

REGULA

0.3µF

TOR

t

d(OFF)

90

V

GS

t

OFF

%

50%

t

f

90%

10%

0

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS

©2003 Fai

rchild Semiconductor Corporation

I

G(RE

F)

G

I

CURRENT

G

SAMPLI

RESISTO

D

DUT

S

I

CURRENT

D

NG

R RESISTOR

SAM

PLING

V

DS

0

V

DS

I

G(REF)

0

RFD16N05LSM Rev. C1

PSPICE Electrical Model

.S

UBCKT RFD16N05L 2 1 3 ; REV 4/8/92

Ca 12 8 3.33e-9
Cb 15 14 3.11e-9
Cin 6 8 1.21e-9

Dbody 7 5 DBDMOD
Dbreak 5 11 DBKMOD
Dplcap 10 5 DPLCAPMOD

Ebreak 11 7 17 18 70.9
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evto 20 6 18 8 1

IT 8 17 1

Lgate 1 9 1.38e-9
Ldrain 2 5 1.0e-12
Lsource 3 7 1.0e-9

Mos1 16 6 8 8 MOSMOD M=0.99
Mos2 16 21 8 8 MOSMOD M=0.01

Rin 6 8 1e9
Rbreak 17 18 RBKMOD 1
Rdrain 5 16 RDSMOD 27.38e-3
Rgate 9 20 2.98
Rsource 8 7 RDSMOD 0.614e-3
Rvto 18 19 RVTOMOD 1

S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

GATE

1

LGATE

RFD16N05LSM

10

-

ESG

+

EVTO

+

-

18

8

S1A

12

13

8

CA

EG

S EDS

RGA

209

TE

6
8

RIN

+

-

DPLCAP

RSCL2

6

S2A

14
13

S2BS1B
13

6
8

VTO

15

CIN

CB

5

LDRAIN

RSCL1
51

+

5

51

50
RD

16

+

MOS1

14

+

5
8

-

ES

21

CL

RAIN

8

DBREAK

11

EBREAK

MOS2

RSOURCE

17 18

+

17
18

-

7

RBREAK

DBODY

LSOURCE

IT

RVTO

19

VBAT

+

DRAIN
2

3

SOURCE

Vbat 8 19 DC 1
Vto 21 6 0.448

.MODEL DBDMOD D (IS=1.34e-13 RS=1.21e-2 TRS1=1.64e-3 TRS2=2.59e-6
+CJO=1.13e-9 TT=4.14e-8)
.MODEL DBKMOD D (RS=8.82e-2 TRS1=-2.01e-3 TRS2=7.32e-10)
.MODEL DPLCAPMOD D (CJO=0.522e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=2.054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.01e-3 TC2=5.21e-8)
.MODEL RDSMOD RES (TC1=3.66e-3 TC2=1.46e-5)
.MODEL RVTOMOD RES (TC1=-1.81e-3 TC2=1.41e-6)
.MODEL S1AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25)
.MODEL S1BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25)
.MODEL S2AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35)
.MODEL S2BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=4.35 VOFF=-0.65)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

©2003

Fairchild Semiconductor Corporation

RFD16N05LSM Rev. C1

RFD16N05LSM

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intended to be an exhaustive list of all such trademarks.

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®

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®

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®

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Solutions for Your Success™

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STEALTH™
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SuperSOT™-3
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Sync-Lock™

®*

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®

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.

2. A critical component in any component of a life support, device, or
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the failure of the life support device or system, or to affect its safety or
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Datasheet Identification Product Status Definition

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Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.

Rev. I66

©2003 Fairchild Semiconductor Corporation

FD16N05LSM Rev. C1

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