Datasheet RFD16N05 Datasheet (Intersil)

RFD16N05, RFD16N05SM

Data Sheet July 1999 File Number

16A, 50V, 0.047 Ohm, N-Channel Power
MOSFETs

The RFD16N05 and RFD16N05SM N-channel power
MOSFETs are manufactured using the MegaFET process.
This process, which uses featuresizesapproachingthoseof
LSI integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use in applications such as switching regulators,
switching converters,motordrivers,andrelay drivers. These
transistors can be operated directly from integrated circuits.

Formerly developmental type TA09771.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD16N05 TO-251AA F16N05
RFD16N05SM TO-252AA F16N05

NOTE: When ordering,usetheentire part number.Add thesuffix 9Ato
obtainthe TO-252AAvariant inthe tapeand reel,i.e., RFD16N05SM9A.

Features

• 16A, 50V

DS(ON)

= 0.047Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

2267.5

Packaging

DRAIN (FLANGE)

S

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN (FLANGE)

4-420

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD16N05, RFD16N05SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD16N05, RFD16N05SM, UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

DM

GS

AS

D

Refer to Peak Current Curve

D

Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

50 V
50 V
16

±20 V

Refer to Figure 5

72

0.48

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V (Figure 11) 50 - - V

= VDS, ID = 250µA2-4V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

, VGS = 0V,

DSS

--25µA

TC = 150oC

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

GSSVGS

(ON)VDD

r

f

g(10)VGS

(TH)VGS

ISSVDS

OSS

RSS

θJC
θJA

= ±20V - - ±100 nA

= 16A, VGS = 10V (Figure 9) - - 0.047 Ω

= 25V, ID = 8A, RL = 3.125Ω,
VGS = 10V, RGS = 25Ω
(Figure 13)

- - 65 ns

-14- ns

-30- ns

-55- ns

-30- ns

- - 125 ns
= 0V to 20V VDD = 40V, I
= 0V to 10V - - 45 nC
= 0V to 2V - - 2.2 nC

RL = 2.5Ω
I

g(REF)

(Figure 13)

= 25V, VGS = 0V, f = 1MHz

(Figure 12)

D

= 0.8mA

≈ 16A,

- - 80 nC

- 900 - pF

- 325 - pF

- 100 - pF

- - 2.083oC/W

TO-251 and TO-252 - - 100

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

NOTES:

2. Pulse test: pulse width ≤ 250µs, duty cycle ≤ 2%.

3. Repetitive rating: pulsewidth limited by maximum junction temperature. See TransientThermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

4-421

ISD = 16A - - 1.5 V

SD

ISD = 16A, dISD/dt = 100A/µs - - 125 ns

rr

RFD16N05, RFD16N05SM

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TENPERATURE

2

1

150

20

16

12

8

, DRAIN CURRENT (A)

D

I

4

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 2. MAXIMUM CONTINUOUS DRAINCURRENT vs

CASE TEMPERATURE

175

0.5

0.2

0.1

0.1

, NORMALIZED

0.05

JC

θ

Z

0.02

THERMAL IMPEDANCE

0.01

0.01

-5

10

100

10

OPERATION IN THIS
AREA MAY BE

, DRAIN CURRENT (A)

D

I

LIMITED BY r

1

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

DS(ON)

10

V

DSS(MAX)

-3

10

t, RECTANGULAR PULSE DURATION (s)

SINGLE PULSE

T

= MAX RATED

J

TC = 25oC

= 50V

100µs

1ms

10ms
100ms

DC

100

-2

10

200

100

, PEAK CURRENT (A)

DM

I

10

-5

10

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

VGS = 20V

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

10

-3

10

t, PULSE WIDTH (s)

P

DM

t

1

t

2

1/t2

x R

JA

θ

0

10

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

10

I = I

-2

o

25

10

+ T

JA

θ

C DERATE PEAK

175 - T

C

150

TC = 25oC

-1

10

A

1

10

0

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-422

RFD16N05, RFD16N05SM

Typical Performance Curves

100

10

STARTING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

1

0.01

0.1

tAV, TIME IN AVALANCHE (ms)

DSS

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

- VDD)
) +1]

DSS-VDD

110

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

50

40

30

= 15V

V

DD

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

-55oC

175oC

25oC

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

VGS = 20V

0

0

VGS = 10V

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC

= 4.5V

V

GS

234

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 10V, ID = 16A

GS

2.0

1.5

V

= 7V

GS

VGS = 6V

V

= 5V

GS

20

10

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCEON

2.0
VGS = VDS,

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120

= 250µA

I

D

TJ, JUNCTION TEMPERATURE (oC)

160

200

FIGURE 10. NORMALIZED GATE THRESHOLDVOLTAGE vs

JUNCTION TEMPERATURE

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

200

RESIST ANCE vs JUNCTION TEMPERATURE

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
, JUNCTION TEMPERATURE (oC)

T

J

200

FIGURE 11. NORMALIZED DRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

4-423

RFD16N05, RFD16N05SM

Typical Performance Curves

Unless Otherwise Specified (Continued)

1600

VGS = 0V, f = 1MHz
C

= CGS + C

1200

ISS

C

= C

RSS

C

C

ISS

OSS

GD

≈ CDS + C

GD

GS

800

C

OSS

C, CAPACITANCE (pF)

400

C

RSS

0

0 5 10 15 20 25

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

V

DD

-

50

37.5

25

12.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

I

G REF()

20

------------------------ ­I

GACT()

DSS

0.75 BV

0.50 BV

0.25 BV

RL = 3.125Ω

= 0.8mA

I

G(REF)

V

= 10V

GS

t, TIME (ms)

DSS
DSS
DSS

= BV

V

DD

I

G REF()

--------------------- -

80

I

G ACT()

10

DSS

7.5

5

2.5

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

BV

DSS

t

P

I

AS

V

DS

V

DD

, GATE TO SOURCE VOLTAGE (V)

GS

V

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

DS

GS

10%

d(ON)

90%

50%

10%

t

r

PULSE WIDTH

V

DS

V

R

DUT

L

+

V

DD

-

0

V

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

4-424

RFD16N05, RFD16N05SM

Test Circuits and Waveforms

V

DS

V

GS

I

G(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORM

(Continued)

R

L

DUT

V

DD

+

V

DD

-

VGS= 2V

0

I

G(REF)

0

V

GS

Q

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

4-425

PSPICE Electrical Model

.SUBCKT RFD16N05 2 1 3 ; rev 10/31/94

CA 12 8 1.788e-10
CB 15 14 1.875e-10
CIN 6 8 8.33e-10

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 64.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 4.56e-9
LSOURCE 3 7 4.13e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.4e-3
RGATE 9 20 3.0
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 21.5e-3
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

GATE

1

LGATE

RFD16N05, RFD16N05SM

DPLCAP

RSCL2

­6

8

+

6

RIN

14
13

S2BS1B
13

+

6
8

-

VTO

15

16

+

CIN

CB

+

-

RGATE

EVTO

+

209

S1A S2A

12

CA

10

ESG

-

18

8

13

8

EGS EDS

5

5

51

5
8

RSCL1
51

+

50
RDRAIN

21

MOS1

14

ESCL

8

DBREAK

11

EBREAK

MOS2

RSOURCE

LDRAIN

+

-

LSOURCE

7

RBREAK

IT

DBODY

17
18

17 18

RVTO

19

VBAT

+

DRAIN
2

3

SOURCE

VBAT 8 19 DC 1
VTO 21 6 0.82

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/94,7))}

.MODEL DBDMOD D (IS = 2.5e-13 RS = 7.1e-3 TRS1 = 3.04e-3 TRS2 = -10e-6 CJO = 1.12e-9 TT = 5.6e-8)
.MODEL DBKMOD D (RS = 2.51e-1 TRS1 = -6.57e-4 TRS2 = 1.66e-6)
.MODEL DPLCAPMOD D (CJO = 6.1e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.96 KP = 16.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -7.19e-7)
.MODEL RDSMOD RES (TC1 = 5.45e-3 TC2 = 1.66e-5)
.MODEL RSCLMOD RES (TC1 = 1.25e-3 TC2 = 17e-6)
.MODEL RVTOMOD RES (TC1 = -5.15e-3 TC2 = -4.83e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.25 VOFF= -3.25)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.25 VOFF= -5.25)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.56 VOFF= 5.56)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.56 VOFF= 0.56)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

4-426

RFD16N05, RFD16N05SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit designand/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which mayresult
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4-427

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