Datasheet RFD15N06LE, RFD15N06LESM Datasheet (Intersil)

RFD15N06LE, RFD15N06LESM

Data Sheet April 1999

15A, 60V, 0.065 Ohm, ESD Rated, Logic
Level, N-Channel Power MOSFETs

These are N-Channel power MOSFETs manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.

Formerly developmental type TA49165.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD15N06LE TO-251AA F15N6L
RFD15N06LESM TO-252AA F15N6L

NOTE: When ordering,usethe entire part number.For ordering intape
and reel,add the suffix 9A to the partnumber, i.e. RFD15N06LESM9A.

File Number

Features

• 15A, 60V

DS(ON)

= 0.065Ω

•r

• 2kV ESD Protected

• Temperature Compensating PSPICE™ Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

4079.1

Packaging

DRAIN (FLANGE)

S

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN (FLANGE)

6-149

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE™ is a trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD15N06LE, RFD15N06LESM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD15N06LE, RFD15N06LESM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, T

STG

GS

DM

AS

D

Refer to Peak Current Curve

D

60 V
60 V

±10 V

15

Refer to UIS Curve

72

0.48

-55 to 175

A

W

W/oC

o

C

Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . ESD 2 kV

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)

Gate Charge at 5V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSS

DSS

GSS

ON

r

f

OFF

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

ID = 250µA, VGS = 0V, Figure 13 60 - - V
VGS= VDS, ID = 250µA, Figure 12 1 - 2 V
VDS = 48V,

VGS = 0V

TC = 25oC--1µA
TC = 150oC--50µA

VGS = ±10V - - 10 µA

= 15A, VGS = 5V - - 0.065 Ω

VDD = 30V, ID = 15A, RL = 2.0Ω,
VGS = 5V, RGS = 2.5Ω
Figures 10, 18, 19

- - 77 ns

-11- ns

-40- ns

-30- ns

-18- ns

- - 75 ns
VGS = 0V to 10V VDD = 48V,
VGS = 0V to 5V - 21 26 nC
VGS = 0V to 1V - 0.95 1.20 nC

ID = 15A,
RL = 3.20Ω
Figures 20, 21

VDS = 25V, VGS = 0V,
f = 1MHz
Figure 14

-3949nC

- 855 - pF

- 240 - pF

-75- pF

- - 2.08
TO-251 and TO-252 - - 100

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

6-150

ISD = 15A - - 1.5 V
ISD = 15A, dISD/dt = 100A/µs--80ns

RFD15N06LE, RFD15N06LESM

Typical Performance Curves

Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

2

1

0.5

150

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.2

0.1

0.1

, NORMALIZED
Z

θJC

THERMAL IMPEDANCE

0.05

0.02

0.01
SINGLE PULSE

0.01

-5

10

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

200

TC = 25oC, TJ = MAX RATED

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

110

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

200

100

100µs

1ms

10ms

100ms

DC

10060

, PEAK CURRENT CAPABILITY (A)

DM

I

10

10

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

TC = 25oC

VGS = 10V

VGS = 5V

THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION

-5

-4

10

10

P

DM

1/t2

θJC
0

10

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

25

-3

-2

10

t, PULSE WIDTH (s)

t

1

t

2

x R

+ T

θJC

C

o

C DERATE PEAK

175 - T

C

150

-1

10

10

1

10

0

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

6-151

RFD15N06LE, RFD15N06LESM

Typical Performance Curves

50

STARTING TJ = 150oC

10

, AVALANCHE CURRENT (A)

If R = 0

AS

I

tAV = (L)(IAS)/(1.3*RATED BV
If R ≠ 0

t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

tAV, TIME IN AVALANCHE (ms)

DSS

0.1 1 100.001 0.01

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

- VDD)

- VDD) +1]

DSS

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

30

25

20

15

= 15V

V

DD

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

-55oC

25oC

175oC

30

VGS = 10V

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

0 1.5 3.0 4.5 6.0

VGS = 5V

VGS = 4V

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oC
PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX.

VGS = 3.5V

VGS = 3V

VGS = 2.5V

FIGURE 7. SATURATION CHARACTERISTICS

200

150

ID = 15A

ID = 7.5A

100

ID = 30A

10

, DRAIN TO SOURCE CURRENT (A)

5

DS(ON)

I

0

0 3 4.5 61.5

VGS, GATE TO SOURCE VOLTAGE (V)

, DRAIN TO SOURCE

50

ON RESISTANCE (mΩ)

DS(ON)

r

0

ID = 3.75A

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0 3.5 4.5 5.04.02.5

3.0

, GATE TO SOURCE VOLTAGE (V)

V

GS

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

250

VDD = 30 V, ID =15A, RL= 2.00Ω

200

150

100

SWITCHING TIME (ns)

50

0

10

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

r

t

f

t

d(ON)

20 30 40 500

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160

ID = 15AVGS = 5V,

TJ, JUNCTION TEMPERATURE (oC)

200

FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

6-152

RFD15N06LE, RFD15N06LESM

Typical Performance Curves

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

Unless Otherwise Specified (Continued)

VGS = VDS,

I

= 250µA

D

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

1200

1000

C

ISS

800

600

400

C, CAPACITANCE (pF)

200

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

= CGS + C

C
C
C

ISS
RSS
OSS

= C

GD

≈ CDS + C

GD

GD

C

C

OSS

RSS

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

200

1.2
ID = 250µA

1.1

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

45

30

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

VDD = BV

I

20

------------------------ ­I

DSS

RL =4.00Ω

= 0.44mA

I

G(REF)

V

= 5V

GS

PLATEAU VOLTAGES IN
DESCENDING ORDER:

VDD = BV
VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25 BV

G REF()
GACT()

t, TIME (ms)

DSS

DSS
DSS
DSS

VDD = BV

I

GREF()

80

------------------------ ­I

GACT()

5.00

DSS

3.75

2.50

1.25

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 15. NORMALIZED SWITCHINGWAVEFORMS FOR

CONSTANT GATE CURRENT

200

, GATE TO SOURCE VOLTAGE (V)

GS

V

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

6-153

t

P

I

AS

t

AV

V

DS

V

DD

RFD15N06LE, RFD15N06LESM

Test Circuits and Waveforms

V

GS

0V

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

V

GS

I

G(REF)

V

GS

R

GS

V

DS

(Continued)

R

L

V

DS

DUT

R

L

DUT

t

ON

t

d(ON)

t

V

DS

+

­0

90%

r

10%

t

d(OFF)

t

OFF

t

f

90%

10%

90%

V

GS

10%

0

V

DD

50%

PULSE WIDTH

Q

g(TOT)

V

DS

50%

VGS= 10V

Q

+

V

DD

-

V

GS

g(5)

VGS= 5V

VGS= 1V

0

Q

g(TH)

I

G(REF)

0

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

6-154

RFD15N06LE, RFD15N06LESM

PSPICE Electrical Model

SUBCKT RFD15N06LE 2 1 3 ; rev 5/13/95

CA 12 8 2.50e-9
CB 15 14 2.4e-9
CIN 6 8 7.70e-10

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 65.18
EDS 14 8 5 8 1

EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1

ESG

EVTEMP 20 6 18 22 1
IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 2.77e-9
LSOURCE 3 7 2.98e-9

MMED 16 6 8 8 MMEDMOD

GATE

1

LGATE

RLGATE

RGATE
9

DESD1

91

DESD2

EVTEMP

+

20

18

22

MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 14.52e-3

S1A

12

13

RGATE 9 20 2.6
RLDRAIN 2 5 10
RLGATE 1 9 27.7
RLSOURCE 3 7 29.8
RSLC1 5 51 RSLCMOD 1e-6

S1B

CA

RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 20.05e-3
RVTHRES 22 8 RVTHRESMOD 1

EGS

RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*72),5))}
.MODEL DBODYMOD D (IS = 6.5e-13 RS = 1.20e-2 TRS1 = 1.75e-3 TRS2 = 5.08e-6 CJO = 7.45e-10 TT = 4.61e-8 M = 0.46)

.MODEL DBREAKMOD D (RS = 1.28e-1 TRS1 = -2.15e-3 TRS2 = 1.05e-5)
.MODEL DESD1MOD D (BV = 12.7 TBV1 = 0 TBV2 = 0 RS = 35 TRS1 = 1.2e-6 TRS2 = 0)
.MODEL DESD2MOD D (BV = 12.7 TBV1 = 0 TBV2 = 0 RS = 0 TRS1 =0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 4.32e-10 IS = 1e-30 N = 10 M = 0.54)
.MODEL MMEDMOD NMOS (VTO = 1.60 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.60)
.MODEL MSTROMOD NMOS (VTO = 1.93 KP = 26.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.39 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.76e-4 TC2 = 5.11e-7)
.MODEL RDRAINMOD RES (TC1 = 1.30e-2 TC2 = 4.49e-5)
.MODEL RSLCMOD RES (TC1 =3.00e-3 TC2 = 6.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.43e-3 TC2 = -6.72e-6)
.MODEL RVTEMPMOD RES (TC1 = -9.91e-4 TC2 = 1.02e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.85 VOFF = -1.85)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.85 VOFF = -4.85)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.35 VOFF = 1.65)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF = -1.35

DPLCAP

10

RSLC2

6
8

+

EVTHRES

+

6

S2A

14

8

13

S2B

13

+

6
8

19

8

15

EDS

CIN

CB

+

5
8

5

RSLC1

51
+

5

51

50
RDRAIN

MSTRO

14

ESLC

16

21

8

MMED

8

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17

IT

RVTHRES

RLDRAIN

11

+

17
18

7

RLSOURCE

18

RVTEMP

19

VBAT

+

22

LDRAIN

DBODY

LSOURCE

DRAIN

2

SOURCE

3

.ENDS

NOTE: For further discussion of the PSPICEmodel, consult A New PSPICE Sub-Circuit forthe Power MOSFET Featuring Global Temperature
Options; IEEE Power Electronics Specialist Conference Records, 1991.

6-155

RFD15N06LE, RFD15N06LESM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserv esthe right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believedto be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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