Datasheet NTMS7N03R2 Datasheet (ON Semiconductor)

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NTMS7N03R2

Power MOSFET
7 Amps, 30 Volts

N-Channel SO-8

Features

• Ultra Low R

• Higher Efficiency Extending Battery Life

• Logic Level Gate Drive

• Miniature SO-8 Surface Mount Package

• Avalanche Energy Specified

• I

Specified at Elevated Temperature

DSS

T ypical Applications

• DC-DC Converters

• Power Management

• Motor Controls

• Inductive Loads

• Replaces MMSF7N03HD, MMSF7N03Z, and MMSF5N03HD in

Many Applications

DS(on)

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7 AMPERES

30 VOLTS

= 23 m

N-Channel

D

G

R

DS(on)

MAXIMUM RATINGS (T

Rating Symbol Value Unit

Drain-to-Source Voltage V
Drain-to-Gate Voltage (RGS = 1.0 MΩ) V
Gate-to-Source Voltage - Continuous V
Thermal Resistance - Junction to Ambient

(Note 1)
Total Power Dissipation @ TA = 25°C P
Drain Current - Continuous @ TA = 25°C

Drain Current - Continuous @ T
Drain Current - Pulsed (Note 4)

Thermal Resistance - Junction to Ambient

(Note 2)
Total Power Dissipation @ TA = 25°C P
Drain Current - Continuous @ TA = 25°C

Drain Current - Continuous @ T
Drain Current - Pulsed (Note 4)

Thermal Resistance - Junction to Ambient

(Note 3)
Total Power Dissipation @ TA = 25°C P
Drain Current - Continuous @ TA = 25°C

Drain Current - Continuous @ T
Drain Current - Pulsed (Note 4)

Operating and Storage Temperature Range TJ, T

Single Pulse Drain-to-Source Avalanche

Energy - Starting T

(V

= 30 Vdc, VGS = 10 Vdc, Peak

DD

I

= 12 Apk, L = 4.0 mH, RG = 25 Ω)

L

1. 2″ SQ. FR-4 PCB mounting, (2 oz. Cu 0.06″ thick single sided), 10 Sec. Max.

2. 2″ SQ. FR-4 PCB mounting, (2 oz. Cu 0.06″ thick single sided),
t = steady state.

3. Minimum FR4 or G10 PCB, t = steady state.

4. Pulse test: Pulse Width = 300 µs, Duty Cycle = 2%.

= 25°C unless otherwise noted)

C

= 70°C

A

= 70°C

A

= 70°C

A

= 25°C

J

R

R

R

E

DSS
DGR

GS

θ

I
I

I

DM

θ

I
I

I

DM

θ

I
I

I

DM

AS

30 Vdc
30 Vdc

± 20 Vdc

JA

D

D
D

JA

D

D
D

JA

D

D
D

stg

50 °C/W

2.5 Watts

8.5

6.8
25

85 °C/W

1.47 Watts

6.5

5.2
18

156 °C/W

0.8 Watts

4.8

3.8
14

- 55 to
+150

288 mJ

Adc

Apk

Adc

Apk

Adc

Apk

°C

S

MARKING
DIAGRAM

SO-8

8

1

CASE 751
STYLE 13

E7N03 = Device Code
A = Assembly Location
Y = Year
WW = Work Week

E7N03
AYWW

PIN ASSIGNMENT

N-C
Source
Source

Gate

1
2
3
4

Top View

Drain

8

Drain

7

Drain

6
5

Drain

ORDERING INFORMATION

Device Package Shipping

NTMS7N03R2 SO-8 2500/Tape & Reel

 Semiconductor Components Industries, LLC, 2002

November, 2002 - Rev. 3

1

Publication Order Number:

NTMS7N03R2/D

NTMS7N03R2

)

f = 1.0 MHz)

R

G

9.1 Ω) (Note 5)

R

G

9.1 Ω) (Note 5)

(V

DS

Vdc, I

D

Adc

(I

S

Adc, V

GS

Vdc

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

C

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain-to-Source Breakdown Voltage (Notes 5 and 7)

= 0 Vdc, ID = 0.25 mAdc)

(V

GS

Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

(V

= 30 Vdc, VGS = 0 Vdc)

DS

= 30 Vdc, VGS = 0 Vdc, TJ = 125°C)

(V

DS

Gate-Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS

Gate Threshold Voltage (Note 5)

= VGS, ID = 0.25 mAdc)

(V

DS

Threshold Temperature Coefficient (Negative)

Static Drain-to-Source On-Resistance (Notes 5 and 7)

(V

= 10 Vdc, ID = 7.0 Adc)

GS

(V

= 4.5 Vdc, ID = 3.5 Adc)

GS

Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 5.0 Adc) (Notes 5 and 7) V
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) (Note 5) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 6)

Turn-On Delay Time

(V

= 10 Vdc, ID = 5.0 Adc,

Rise Time
Turn-Off Delay Time

DD

VGS = 4.5 Vdc,

= 9.1 Ω) (Note 5)

R

G

Fall Time
Turn-On Delay Time t

(V

= 10 Vdc, ID = 5.0 Adc,

Rise Time
Turn-Off Delay Time

DD

VGS = 10 Vdc,
= 9.1 Ω) (Note 5)

R

G

Fall Time
Gate Charge

(VDS = 16 Vdc, ID = 5.0 Adc,

16

V

= 10 Vdc) (Note 5)

GS

5.0

,

SOURCE-DRAIN DIODE CHARACTERISTICS

Forward On-Voltage (Note 5)

(IS = 7.0 Adc, VGS = 0 Vdc) (Note 5)

= 7.0 Adc, VGS = 0 Vdc,

(I

S

= 125°C)

T

J

Reverse Recovery Time

(IS = 7.0 Adc, VGS = 0 Vdc,

7.0

dI

/dt = 100 A/µs) (Note 5)

S

0

,

Reverse Recovery Stored Charge Q

5. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

6. Switching characteristics are independent of operating junction temperature.

7. Reflects Typical Values.

Max limit  Typ

Cpk 



3  



V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

DS(on)

C
C
C

t

d(on)

t

d(off)

d(on)

t

d(off)

Q

Q
Q
Q

V

t
t
t

FS

iss
oss
rss

t

r

t

f

t

r

t

f

SD

rr

a

b
RR

30

-

41

-

-

-

mV/°C

µAdc

Vdc

-

-

0.02

-

1.0
10

- - 100 nAdc

Vdc

1.0

-

1.6

4.0

3.0

-

mV/°C

m

-

-

18.6

23.5

23
28

- 93 115 mV

3.0 13 - Mhos

- 1064 1190 pF

- 300 490

- 94 120

- 15 30

ns

- 71 185

- 27 70

- 38 80

- 8.0 -

- 38 -

- 33 -

- 49

T
1
2
3

- 26 43

- 3.1 -

- 6.0 -

- 5.5 -

-

-

0.82

0.67

1.1

-

- 27 -

nC

Vdc

ns

- 15 -

- 11.5 -

- 0.02 - µC

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2

NTMS7N03R2

ATTRIBUTES

Characteristics Value

ESD Protection Human Body Model

Machine Model
Charged Device Model

TYPICAL ELECTRICAL CHARACTERISTICS

Class 1E

Class A
Class 0

20
18
16
14
12
10

, DRAIN CURRENT (AMPS)

D

I

VGS = 10 V

8 V

7 V

6 V

5 V

8
6
4
2

0

0 0.1 0.2 0.3 1

V

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

DS

0.4 0.5

3.6 V

3.8 V

4 V

4.6 V

TJ = 25°C

2.4 V

0.8 0.9

Figure 1. On-Region Characteristics

3.4 V

3.2 V

3 V

2.8 V

10

9

VDS = 10 V
8
7

6
5
4
3

, DRAIN CURRENT (AMPS)

2

D

I

1
0

0 0.5 1 3.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

TJ = 100°C

1.50.6 0.7 2

-55°C

2.5 3

Figure 2. Transfer Characteristics

25°C

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NTMS7N03R2

TYPICAL ELECTRICAL CHARACTERISTICS

0.6

0.5

0.4

0.3

0.2

0.1

0

, DRAIN-TO-SOURCE RESISTANCE (OHMS)

13 957

DS(on)

R

24 10

, GATE-TO-SOURCE VOLTAGE (VOLTS)

V

GS

Figure 3. On-Resistance versus

68

Gate-T o-Source Voltage

2

VGS = 10 V

= 3.5 A

I

D

1.5

ID = 3.5 A
T

= 25°C

J

0.05
TJ = 25°C

0.04

0.03

VGS = 4.5 V

0.02

0.01

0

, DRAIN-TO-SOURCE RESISTANCE (OHMS)

0 5 10 15

DS(on)

R

Figure 4. On-Resistance versus Drain Current

ID, DRAIN CURRENT (AMPS)

10 V

and Gate Voltage

1000

VGS = 0 V

TJ = 125°C

100

1

(NORMALIZED)

0.5

, DRAIN-TO-SOURCE RESISTANCE

DS(on)

0

R

-50-250 25 50 75 100 125 150
, JUNCTION TEMPERATURE (°C)

T

J

Figure 5. On-Resistance Variation with

Temperature

TJ = 100°C

, LEAKAGE (nA)

10

DSS

I

1

0102030

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. Drain-To-Source Leakage

Current versus Voltage

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NTMS7N03R2

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain-gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:
tr = Q2 x RG/(VGG - V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn-on and turn-off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

- V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off-state condition when
calculating t
on-state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

V

2800
2400
2000
1600
1200

C, CAPACITANCE (pF)

GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS = 0 V

C

iss

C

rss

800
400

0

10 0 10 15 20

55

Figure 7. Capacitance Variation

= 0 V

GS

C

rss

V

V

GS

DS

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5

TJ = 25°C

C

iss

C

oss

NTMS7N03R2

10

QT

8

V

GS

6

4

, GATE-TO-SOURCE VOLTAGE (VOLTS)

GS

V

Q1

2

0

0

Q2

510 30

, TOTAL GATE CHARGE (nC)

Q

G

15

ID = 3.5 A
T

= 25°C

J

20 25

Figure 8. Gate-To-Source and Drain-To-Source

Voltage versus Total Charge

DRAIN-T O-SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
to the storage of minority carrier charge, Q

, as shown in

RR

, due

rr

the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t

and low QRR specifications to

rr

minimize these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by

V

1000

DS

1.2
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1.0

0.8

0.6

0.4

0

VDD = 24 V
I

= 7 A

D

= 10 V

V

GS

100

t, TIME (ns)

10

1

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

high di/dts. The diode’s negative di/dt during t
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t

serves as a good indicator of recovery

b/ta

abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t

), have less stored charge and a softer

rr

reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.

t

d(off)

t

f

t

r

t

d(on)

is directly

a

8
7
6
5
4
3
2

, SOURCE CURRENT (AMPS)

S

1

I

0

0.40 1.00

VGS = 0 V
T

= 25°C

J

0.50 0.70

V

SD

0.60 0.80 0.90

, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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NTMS7N03R2

di/dt = 300 A/µs

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain-to-source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T

) of 25°C.

C

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance ­General Data and Its Use.”

Switching between the off-state and the on-state may
traverse any load line provided neither rated peak current
(I

) nor rated voltage (V

DM

) is exceeded, and that the

DSS

transition time (tr, tf) does not exceed 10 µs. In addition the
total power averaged over a complete switching cycle must
not exceed (T

J(MAX)

- TC)/(R

).

JC

θ

A power MOSFET designated E-FET can be safely used
in switching circuits with unclamped inductive loads. For

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

t, TIME

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non-linearly with an increase of peak current in avalanche
and peak junction temperature.

Although many E-FETs can withstand the stress of
drain-to-source avalanche at currents up to rated pulsed
current (I
continuous current (I

), the energy rating is specified at rated

DM

), in accordance with industry

D

custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I

can safely be

D

assumed to equal the values indicated.

100

10

VGS = 20 V
SINGLE PULSE

1

T

= 25°C

C

R

LIMIT

DS(on)

0.1

, DRAIN CURRENT (AMPS)

D

I

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.

0.01

0.1
V

THERMAL LIMIT
PACKAGE LIMIT

1

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

DS

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

10

400
350

300

10 µs
100 µs

1 ms

10 ms

dc

100

250
200
150
100

50

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN-TO-SOURCE

AS

E

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7

ID = 12 A

0

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

150

10

NTMS7N03R2

TYPICAL ELECTRICAL CHARACTERISTICS

1

0.1

0.01

THERMAL RESISTANCE

Rthja(t), EFFECTIVE TRANSIENT

0.001

1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

Normalized to θja at 10s.

0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω

Chip

72.416 F1.9437 F0.5541 F0.1668 F0.0307 F

Ambient

1.0E+02 1.0E+03

t, TIME (s)

Figure 14. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 15. Diode Reverse Recovery Waveform

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NTMS7N03R2

INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a c ritical p ortion o f t he total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection

0.275

7.0

0.024

0.6

SO-8 POWER DISSIPATION

The power dissipation of the SO-8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by T
temperature of the die, R

, the maximum rated junction

J(max)

, the thermal resistance from

JA

θ

the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet for the SO-8 package, PD can be calculated as
follows:

PD =

J(max)

A

R

θ

JA

- T

T

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values

interface between the board and the package. With the
correct pad geometry, the packages will self-align when
subjected to a solder reflow process.

0.060

1.52

0.155

4.0

0.050

1.270

into the equation for an ambient temperature T

inches

mm

of 25°C,

A

one can calculate the power dissipation of the device which
in this case is 2.5 Watts.

PD =

150°C - 25°C

50°C/W

= 2.5 Watts

The 50°C/W for the SO- 8 package assumes the

recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Clad. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.

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• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.

• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied
during cooling.

* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.

9

NTMS7N03R2

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows

200°C

150°C

100°C

STEP 1

PREHEAT

ZONE 1
“RAMP”

DESIRED CURVE FOR HIGH

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

HEATING

ZONES 2 & 5

STEP 3

“RAMP”

temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177 -189 °C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160°C

140°C

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT
SOLDER

JOINT

5°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL) T

Figure 16. Typical Solder Heating Profile

MAX

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-Z-

-Y-

NTMS7N03R2

PACKAGE DIMENSIONS

SO-8

CASE 751-07

ISSUE AA

NOTES:

-X­A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

N

X 45



M

J

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8



N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

INCHES

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NTMS7N03R2

Thermal Clad is a registered trademark of the Bergquist Company.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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Phone: [phone] or 800-344-3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative.

NTMS7N03R2/D

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