• Optimized Gate Charge to Minimize Switching Losses
• These are Pb−Free Devices
Applications
• Refer to Application Note AND8195/D
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
to Minimize Conduction Losses
DS(on)
V
(BR)DSS
30 V
http://onsemi.com
R
MAXID MAX
DS(ON)
3.5 mW @ 10 V
5.0 mW @ 4.5 V
D (5,6)
104 A
MAXIMUM RATINGS (T
ParameterSymbolValueUnit
Drain−to−Source VoltageV
Gate−to−Source VoltageV
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Continuous Drain
Current R
(Note 2)
Power Dissipation
R
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Pulsed Drain
Current
Operating Junction and Storage
Temperature
Source Current (Body Diode)I
Drain to Source DV/DTdV/d
Single Pulse Drain−to−Source Avalanche
Energy T
I
L
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
q
JA
(Note 1)
q
JA
q
JA
(Note 2)
q
JA
q
JC
(Note 1)
q
JC
= 25°C, VDD = 50 V, VGS = 10 V,
J
= 28 Apk, L = 1.0 mH, RG = 25 W
= 25°C unless otherwise stated)
J
TA = 25°C
TA = 85°C14
TA = 25°CP
TA = 25°C
Steady
State
TA = 85°C9.0
TA = 25°CP
TC = 25°C
TC = 85°C75
TC = 25°CP
TA = 25°C,
= 10 ms
t
p
T
I
TJ,
E
DSS
GS
I
D
D
I
D
D
I
D
D
DM
STG
S
AS
T
L
t
30V
±20V
20
2.27W
12
0.89W
104
62.5W
208A
−55 to
+150
52A
6V/ns
392mJ
260°C
A
A
A
°C
G (4)
S (1,2,3)
N−CHANNEL MOSFET
MARKING
DIAGRAM
D
S
4835N
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A= Assembly Location
Y= Year
W= Work Week
ZZ= Lot Traceability
S
AYWZZ
S
G
D
ORDERING INFORMATION
DevicePackageShipping
NTMFS4835NT1GSO−8FL
(Pb−Free)
NTMFS4835NT3GSO−8FL
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
R
q
JC
R
q
JA
R
q
JA
2.0
55.1
140.1
°C/W
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
SymbolTest ConditionMinTypMaxUnit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain CurrentI
Gate−to−Source Leakage CurrentI
V
(BR)DSS
V
(BR)DSS
T
DSS
GSS
VGS = 0 V, ID = 250 mA
/
J
VGS = 0 V,
V
= 24 V
DS
VDS = 0 V, VGS = ±20 V±100nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature CoefficientV
Drain−to−Source On ResistanceR
V
GS(TH)
GS(TH)/TJ
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V to
11.5 V
VGS = 4.5 V
Forward Transconductanceg
FS
VDS = 15 V, ID = 15 A21S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output CapacitanceC
Reverse Transfer CapacitanceC
Total Gate ChargeQ
Threshold Gate ChargeQ
Gate−to−Source ChargeQ
Gate−to−Drain ChargeQ
Total Gate ChargeQ
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
G(TOT)
VGS = 0 V, f = 1 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
VGS = 11.5 V, VDS = 15 V;
I
= 30 A
D
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Timet
Turn−Off Delay Timet
Fall Timet
Turn−On Delay Timet
Rise Timet
Turn−Off Delay Timet
Fall Timet
t
d(ON)
r
d(OFF)
f
d(ON)
r
d(OFF)
f
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
= 3.0 W
R
G
VGS = 11.5 V, VDS = 15 V,
= 15 A, RG = 3.0 W
I
D
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
30V
22.4
TJ = 25 °C1.0
TJ = 125°C10
1.51.92.5V
5.3mV/°C
ID = 30 A2.93.5
ID = 15 A2.5
ID = 30 A4.35.0
ID = 15 A3.9
3100
670
360
2239
4.7
8.3
8.8
52
16
31
22
13
10
23
30
10
mV/°C
mA
mW
pF
nC
nC
ns
ns
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2
Page 3
NTMFS4835N
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise specified)
J
ParameterUnitMaxTypMinTest ConditionSymbol
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Timet
Charge Timet
Discharge Timet
Reverse Recovery ChargeQ
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 30 A
S
VGS = 0 V, dIS/dt = 100 A/ms,
I
= 30 A
S
PACKAGE PARASITIC VALUES
Source Inductance
Drain InductanceL
Gate InductanceL
Gate ResistanceR
L
S
D
G
G
TA = 25°C
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
TJ = 25°C0.771.0
TJ = 125°C0.70
2750
15
12
18nC
0.65nH
0.005nH
1.84nH
1.35.0
V
ns
W
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3
Page 4
NTMFS4835N
TYPICAL PERFORMANCE CURVES
170
150
VGS = 5.0 to 10 V
130
110
90
70
50
, DRAIN CURRENT (AMPS)
30
D
I
10
0
021
V
DS
3
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region CharacteristicsFigure 2. Transfer Characteristics
0.030
0.025
0.020
0.015
170
4.0 V
150
VDS ≥ 10 V
130
TJ = 25°C
3.5 V
110
90
3.2 V
70
3.0 V
2.8 V
2.6 V
40
5
768910
50
, DRAIN CURRENT (AMPS)
30
D
I
10
0
TJ = 25°C
TJ = −55°CTJ = 125°C
1
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
23
46
0.008
ID = 30 A
T
= 25°C
J
0.007
0.006
0.005
TJ = 25°C
VGS = 4.5 V
0.004
5
0.010
0.005
, DRAIN−TO−SOURCE RESISTANCE (W)
0
DS(on)
2
R
4
615
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
2.0
ID = 30 A
V
= 10 V
GS
1.5
1.0
(NORMALIZED)
0.5
, DRAIN−TO−SOURCE RESISTANCE
0
DS(on)
−50250−255075
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Voltage
0.003
VGS = 11.5 V
0.002
0.001
, DRAIN−TO−SOURCE RESISTANCE (W)
0
8
1012
DS(on)
R
10
20
253055
35
405045
60
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
VGS = 0 V
10,000
TJ = 150°C
1,000
, LEAKAGE (nA)
DSS
I
100
TJ = 125°C
10
100
125
150
8
1612304
20
24
28
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
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NTMFS4835N
TYPICAL PERFORMANCE CURVES
5000
4500
C
iss
TJ = 25°C
4000
3500
3000
C
iss
2500
2000
C
rss
1500
C, CAPACITANCE (pF)
1000
500
C
oss
0
1025
1501015
55
V
GS
V
DS
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
VDS = 15 V
I
= 15 A
D
= 11.5 V
V
100
t, TIME (ns)
GS
10
t
d(off)
t
f
t
r
t
d(on)
30
12
Q
T
10
V
DS
V
GS
8
6
Q
4
Q
gs
gd
2
0
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
GS
0
155
201025504540
Q
, TOTAL GATE CHARGE (nC)
G
30
35
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
30
VGS = 0 V
25
TJ = 25°C
20
15
10
ID = 30 A
T
= 25°C
J
55
20
18
16
14
12
10
8
6
4
2
0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
110100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1000
100
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1
, DRAIN CURRENT (AMPS)
D
I
0.1
0.11100
V
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
100 ms
1 ms
10 ms
dc
, SOURCE CURRENT (AMPS)
5
S
I
0
0.50.6
0.41.1
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
V
SD
0.70.8
Figure 10. Diode Forward Voltage vs. Current
400
360
320
280
240
200
160
120
80
AVALANCHE ENERGY (mJ)
40
, SINGLE PULSE DRAIN−TO−SOURCE
0
AS
25
E
5075
, STARTING JUNCTION TEMPERATURE (°C)
T
J
100125
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
0.91.0
ID = 28 A
150
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5
Page 6
1000
100
10
, DRAIN CURRENT (AMPS)
D
I
NTMFS4835N
TYPICAL PERFORMANCE CURVES
25°C
100°C
125°C
1
10
PULSE WIDTH (ms)
1000
100001100
Figure 13. Avalanche Characteristics
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6
Page 7
0.10 C
0.10 C
0.05
c
PIN 5
(EXPOSED PAD)
D
2
D1
1234
TOP VIEW
SIDE VIEW
b
8X
A0.10BC
L
14
E2
2 X
e/2
0.20
A
E1
E
2
A
DETAIL A
K
M
L1
NTMFS4835N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
C
B
2 X
0.20 C
c
DETAIL A
SOLDERING FOOTPRINT*
3X4X
1.270
0.965
1.330
2X
0.495
3.200
3 X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
DIM MINNOM
4 X
q
A1
C
e
SEATING
PLANE
0.750
2X
0.905
4X
1.000
STYLE 1:
PIN 1. SOURCE
MILLIMETERS
A0.901.00
A10.00−−−
b0.330.41
c0.230.28
D5.15 BSC
D14.504.90
D23.50−−−
E6.15 BSC
E15.505.80
E23.45−−−
e1.27 BSC
G0.510.61
K1.201.35
L0.510.61
L10.050.17
M3.003.40
q0 −−−
_
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
MAX
1.10
0.05
0.51
0.33
5.10
4.22
6.10
4.30
0.71
1.50
0.71
0.20
3.80
12
_
4.530
0.475
G
D2
BOTTOM VIEW
2X
1.530
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Europe, Middle East and Africa Technical Support:
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTMFS4835N/D
7
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