The NTE874 is a monolithic bipolar/I2L integrated circuit digital sync system designed for use in consumer TV applications for color/monochrome receivers or monitors. This device takes the composite
video input signal in combination with the on–chip master–scan oscillator to provide both horizontal
drive and vertical deflection output signals.
Other on–chip functions include sync separator, horizontal APC, horizontal/vertical count–down circuitry, vertical ramp generator, and horizontal drive circuit (Pulse–Width Modulator).
The NTE874 features dual–mode operation and accepts either standard or non–standard video signals. An automatic mode–recognition system forces the operation into the asynchronous mode for
non–standard sync signals.
Intended for use with 525–line systems, the NTE874 is supplied in the 28–lead dual–in–line plastic
package.
Features:
DSync Separator
DMaster Scan Oscillator (at 64 X f
DAutomatic Phase Control (APC) of Oscillator
DHorizontal/Vertical Count–down
DVertical Output
DHorizontal Drive Output (Pulse–Width Modulator)
)
H
Absolute Maximum Ratings
POWER SUPPLY:
Power Supply Voltage, V
Power Supply Current, I
Injector Supply Voltage, V
Injector Supply Current, I
Analog Supply VoltageV
Analog Supply CurrentI
Injector Supply VoltageV
Total Dissipation, no external loadsP
Force Asynchronous Low (“0”)V
Force AsynchronousV
Integrated Vertical, LowV
Integrated Vertical, HighV
CC
CC
INJ
D
FAL
FAH
IVL
IVH
710.912.012.9V
7304560mA
101.31.61.9V
––580–mW
2–0.50+0.25V
20.70.81.5V
1––1.9V
12.8––V
Electrical Characteristics: (TA = +25°C, VCC = 12VDC, V25 = 12VDC, Pin 2, 15, 22 to GND;, 1µF
from Pin 4 to GND., 10K ohms from Pin 28 to GND., F
4V, V
Power Supply Section
Supply CurrentPin 10 Open7204560mA
1.9V to 2.8V, VFA 0.2V to 0.7V)
IV
ParameterTest ConditionsPIN #MinTypMaxUnits
= 1MHz, (AC Coupled), V
CLK
Sync
1.2V to
Injector Voltage101.31.61.9V
Sync Separator/Diff. Section
Video Inverter, High VoltageV27 = 4V, I26 = –500µA264.25.15.8V
Sync Processor, Low VoltageV27 = 4V, I26 = 0µA28––.1V
OSC/Count–Down/APC Section
APC BiasV27 = 4V, I26 = 0µA,
216.56.87.5V
V21 = Open
Page 3
Electrical Characteristics (Cont’d): (TA = +25°C, VCC = 12VDC, V25 = 12VDC, Pin 2, 15, 22 to
GND;, 1µF from Pin 4 to GND., 10K ohms from Pin 28 to GND., F
100 ohm (Pin 14 to GND)
V13 = 2V
Set V11 thru 1K ohm for
V14 = 2V
Apply 1kHz, 1V
RMS
to Pin 11
Thru 99 K ohm and 1µF
Avol = 20 LOG|V14 (AC)/V11
(AC))
Mode Change
Non–Standard IV Field
Sync = 9, Within IV Window
(See Note 6)
Count STD/NON–STD
Mode Change
Sync = Less than 911,165–7–
Non–Standard Vertical
Sync Field
Count STD/NON–STD
11,13––50mV
141.4––V
14––2µA
11,14243339dB
11,165–7–
Mode Change
Field Confidence Count,
NON–STD/STD
Number of New Timing
IV/Sync Periods to Return to
STD Mode
Standard Mode Divide RatioIV = 16800
Clock Ratio Sync = 9 )
Serrations within 384 Clock
Window (After 8 Fields, i.e: On
9th Field)
Standard Mode Vertical
Pulse Width
(See Note 7)
Number of Clock Cycles
Output is On
Non–Standard ModeIV Ratio Range Can Be and
Cause Proper Syncronization,
Except for IV Ratio Range of
(16748–16832), Sync = Don’t
Care (After 7 Fields, i.e.: on
8th Field)
Non–Standard Vertical
Pulse Width
Number of Clock Cycles
Output is On
11,167–14–
–––16800
11383384387–
–16160–17405
11362364367–
Page 6
Electrical Characteristics (Cont’d): (TA = +25°C, VCC = 12VDC, V25 = 12VDC, Pin 2, 15, 22 to
GND;, 1µF from Pin 4 to GND., 10K ohms from Pin 28 to GND., F
1.2V to 4V, VIV 1.9V to 2.8V, VFA 0.2V to 0.7V)
V
Sync
ParameterTest ConditionsPIN #MinTypMaxUnits
Vertical Drive Section (Cont’d)
= 1MHz, (AC Coupled),
CLK
Non–Standard Vertical
Pulse Width
Non–Standard Mode Asynchronous Divide Ratio
Blanking Pulse Width–16120012161220–
Noise Mode ChangeIV Outside the Range of
Force Non–Standard ModeIV = 16800 Sync = 9 Serra-
Sync 9 Serrations Within 384
Clock Window, Number of
Clock Cycles Output is On
No IV or Sync Applied (After 7
Fields, i.e., on 8th Field)
(16784–16832) Sync = 9
Serrations in 384 Clock Window Pulse Applied 2432 to
11520 After an IV, Pulse is 8
to 32 Clocks Wide. Resync
results in next field and is
maintained for Mode Change
Confidence Count
tions Within 384 Clock Window. VFA Open Circuit Vertical Pulse Width M Measured
in Next Field.
11362364367–
11, 16––21888–
11,16––16800–
11362364367µs
Note 1 All timing measurements are with reference to the leading edge of the fly–back pulse input
to Pin 18. Fly–back pulse width is 12.00 µs and it is from 0 to 5V . Fly–back pulse train should
start about 500 µs after the start of vertical drive pulse.
Note 2 Start of fly–back pulse is 90 degrees leading with clock.
Note 3 Start of fly–back pulse is 90 degrees lagging with clock.
Note 4 Threshold for measuring AGC gate and horizontal blanking is 3V and burst gate is at 9V.
Note 5. Timing measurements referenced to trailing edge of negative sync pulse input to Pin 26. Th e
negative sync pulse width is is 4.5µs and is from 0 to 500µA, with negative leading edge
delayed 0.5µs from the positive leading edge of the fly–back pulse. The input to Pin 27 is
DC
.
+4V
Note 6 IV Ratio same as in Non–Standard Mode Ratio Range Test.
Note 7 IV Ratio same as in Standard Mode Ratio Test.
Note 8 Burst Gate Start is with reference to trailing edge of sync pulse at Pin 26. Sync Pulse is a