Datasheet NE5205AN, NE5205AD, SA5205AN Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
SA5205A
Wide-band high-frequency amplifier
Product specification Replaces data of February 24, 1992
IC17 Data Handbook
Philips Semiconductors
1997 Nov 07
Page 2
SA5205AWide-band high-frequency amplifier
DESCRIPTION
The SA5205A family of wideband amplifiers replace the SA5205 family. The ‘A’ parts are fabricated on a rugged 2µm bipolar process featuring excellent statistical process control. Electrical performance is nominally identical to the original parts.
The SA5205A is a high-frequency amplifier with a fixed insertion gain of 20dB. The SA5205A operates with a single supply of 6V , and only draws 24mA of supply current, which is much less than comparable hybrid parts. The noise figure is 4.8dB in a 75 system and 6dB in a 50 system.
Until now, most RF or high-frequency designers had to settle for discrete or hybrid solutions to their amplification problems. Most of these solutions required trade-offs that the designer had to accept in order to use high-frequency gain stages. These include high-power consumption, large component count, transformers, large packages with heat sinks, and high part cost. The SA5205A solves these problems by incorporating a wide-band amplifier on a single monolithic chip.
The part is well matched to 50 or 75 input and output impedances. The Standing Wave Ratios in 50 and 75 systems do not exceed
1.5 on either the input or output from DC to the -3dB bandwidth limit. Since the part is a small monolithic IC die, problems such as stray
capacitance are minimized. The die size is small enough to fit into a very cost-effective 8-pin small-outline (SO) package to further reduce parasitic effects.
No external components are needed other than AC coupling capacitors because the SA5205A is internally compensated and matched to 50 and 75. The amplifier has very good distortion specifications, with second and third-order intermodulation intercepts of +24dBm and +17dBm respectively at 100MHz.
The device is ideally suited for 75 cable television applications such as decoder boxes, satellite receiver/decoders, and front-end amplifiers for TV receivers. It is also useful for amplified splitters and antenna amplifiers.
The part is matched well for 50 test equipment such as signal generators, oscilloscopes, frequency counters and all kinds of signal analyzers. Other applications at 50 include mobile radio, CB radio and data/video transmission in fiber optics, as well as broad-band LANs and telecom systems. A gain greater than 20dB can be achieved by cascading additional SA5205As in series as required, without any degradation in amplifier stability.
PIN CONFIGURATIONS
D Packages
1
V
CC
2
V
IN
3
GND
GND
TOP VIEW
Figure 1. Pin Configuration
20dB
8
V
CC
7
V
OUT
6
GND
54
GND
FEATURES
600MHz bandwidth
20dB insertion gain
4.8dB (6dB) noise figure ZO=75 (ZO=50)
No external components required
Input and output impedances matched to 50/75 systems
2000V ESD protection
APPLICATIONS
75 cable TV decoder boxes
Antenna amplifiers
Amplified splitters
Signal generators
Frequency counters
Oscilloscopes
Signal analyzers
Broad-band LANs
Fiber-optics
Modems
Mobile radio
Security systems
Telecommunications
SR00215
ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
8-Pin Plastic Small Outline (SO) package -40 to +85°C SA5205AD SOT96-1
1997 Nov 07 853-1598 18662
2
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SA5205AWide-band high-frequency amplifier
EQUIVALENT SCHEMATIC
V
CC
R1
Q3
Q6
R3
V
IN
Q1 Q4
RF1
RE1
RF2
Q5
Q2
R2
RE2
V
OUT
Figure 2. Equivalent Schematic
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNIT
V
CC
V
AC
T
A
P
DMAX
NOTES:
1. Derate above 25°C, at the following rates: D package at 6.2mW/°C
2. See “Power Dissipation Considerations” section.
Supply voltage 9 V AC input voltage 5 V Operating ambient temperature range
SA grade -40 to +85 °C
Maximum power dissipation, T
=25°C (still-air)
A
1, 2
D package 780 mW
SR00216
P-P
1997 Nov 07
3
Page 4
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
S11
Input return loss
dB
S22
Output return loss
dB
S12
Isolation
dB
SA5205AWide-band high-frequency amplifier
DC ELECTRICAL CHARACTERISTICS
VCC=6V, ZS=ZL=ZO=50 and TA=25°C in all packages, unless otherwise specified.
SA5205A
Min Typ Max
V
CC
I
CC
Operating supply voltage range
Supply current
Over temperature
Over temperature
S21 Insertion gain f=100MHz
Over temperature
p
p
f=100MHz 25
DC - f
MAX
f=100MHz 27
DC - f
MAX
5 5
20
19 17
16.5
12
12
25 25
19 21
f=100MHz -25
DC - f
MAX
t
R
t
P
Rise time 500 ps Propagation delay 500 ps
-18
BW Bandwidth ±0.5dB 450 MHz f
MAX
Bandwidth -3dB 550 MHz Noise figure (75) f=100MHz 4.8 dB Noise figure (50) f=100MHz 6.0 dB Saturated output power f=100MHz +7.0 dBm 1dB gain compression f=100MHz +4.0 dBm Third-order intermodulation
intercept (output) Second-order intermodulation
intercept (output)
f=100MHz +17 dBm
f=100MHz +24 dBm
8 8
32 33
21.5
V V
mA mA
dB
1997 Nov 07
4
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SA5205AWide-band high-frequency amplifier
35 34
32 30
TA = 25oC
28 26
24 22
SUPPLY CURRENT—mA
20 18
16
5 5.5 6 6.5 7 7.5 8
SUPPLY VOLTAGE—V
Figure 3. Supply Current vs Supply Voltage
9
8
7
NOISE FIGURE—dBm
6
5
10
vcc = 8v vcc = 7v vcc = 6v vcc = 5v
12 468 2 468
ZO = 50
= 25oC
T
A
2
10
FREQUENCY—MHz
Figure 4. Noise Figure vs Frequency
25
20
vcc = 7v
vcc = 8v
SR00217
3
10
SR00219
11 10
9 8
7 6 5 4
VCC = 7V
3 2
VCC = 6V
1
VCC = 5V
0 –1 –2 –3
OUTPUT LEVEL—dBm
ZO = 50
–4 –5 –6
= 25oC
T
A
12 468 2 468
10
VCC = 8V
2
FREQUENCY—MHz
10
Figure 7. Saturated Output Power vs Frequency
10
9 8 7 6
V
6V
CC =
5 4 3
V
CC =
2 1
0 –1 –2
OUTPUT LEVEL—dBm
–3 –4 –5 –6
ZO = 50
T
A
12 468 2 468
10
5V
= 25oC
V
7V
CC =
2
10
FREQUENCY—MHz
V
CC =
8V
Figure 8. 1dB Gain Compression vs Frequency
40
35
30
3
10
SR00218
3
10
SR00220
15
INSERTION GAIN—dB
INSERTION GAIN—dB
1997 Nov 07
vcc = 6v
vcc = 5v
ZO = 50
= 25oC
T
A
10
12 468 2 468
10
FREQUENCY—MHz
2
10
Figure 5. Insertion Gain vs Frequency (S21)
25
TA = 55oC
TA = 85oC
TA = 125oC
2
10
TA = 25oC
20
15
VCC = 8V
= 50
Z
O
10
12 468 2 468
10
FREQUENCY—MHz
Figure 6. Insertion Gain vs Frequency (S21)
3
10
SR00221
3
10
SR00223
25
20
15
SECOND–ORDER INTERCEPT—dBM
10
45678910
POWER SUPPLY VOLTAGE—V
ZO = 50
= 25oC
T
A
Figure 9. Second-Order Output Intercept vs Supply Voltage
30
25
20
15
10
THIRD–ORDER INTERCEPT—dBm
5
4 5678910
POWER SUPPLY VOLTAGE—V
ZO = 50
= 25oC
T
A
Figure 10. Third-Order Intercept vs Supply Voltage
5
SR00222
SR00224
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SA5205AWide-band high-frequency amplifier
2.0
1.9
1.8
1.7
1.6
1.5
1.4
INPUT VSWR
1.3
1.2
1.1
1.0
TA = 25oC
= 6V
V
CC
.
ZO = 75
ZO = 50
1
10
2468102246810
FREQUENCY—MHz
Figure 11. Input VSWR vs Frequency
2.0
1.9
1.8
1.7
1.6
1.5
1.4
INPUT VSWR
1.3
1.2
1.1
1.0
T
= 25oC
amb
= 6V
V
CC
ZO = 75
ZO = 50
1
10
2468102246810
FREQUENCY—MHz
Figure 12. Output VSWR vs Frequency
3
SR00225
3
SR00227
10
–15
–20
ISOLATION—dB
–25
–30
12 4681022 468103
10
VCC = 6V
= 50
Z
O
TA = 25oC
FREQUENCY—MHz
Figure 14. Isolation vs Frequency (S12)
25
20
vcc = 6v
10
vcc = 5v
2
15
ISOLATION GAIN—dB
ZO = 75
= 25oC
T
A
10
12 468 2 468
10
FREQUENCY—MHz
vcc = 8v
vcc = 7v
Figure 15. Insertion Gain vs Frequency (S21)
SR00226
3
10
SR00228
40
35
30
25
VCC = 6V
20
INPUT RETURN LOSS—dB
15
OUTPUT RETURN LOSS—dB
10
= 50
Z
O
TA = 25oC
12 4681022 468103
10
FREQUENCY—MHz
OUTPUT
INPUT
Figure 13. Input (S11) and Output (S22) Return Loss vs
Frequency
1997 Nov 07
SR00229
25
TA = –55oC
TA = 25oC
20
TA = 85oC
15
INSERTION GAIN—dB
10
10
ZO = 75
= 6V
V
CC
1 2 468 2 468
TA = 125oC
2
10
FREQUENCY—MHz
3
10
SR00230
Figure 16. Insertion Gain vs Frequency (S21)
6
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SA5205AWide-band high-frequency amplifier
THEORY OF OPERATION
The design is based on the use of multiple feedback loops to provide wide-band gain together with good noise figure and terminal impedance matches. Referring to the circuit schematic in Figure 17, the gain is set primarily by the equation:
V
OUT
V
IN
which is series-shunt feedback. There is also shunt-series feedback due to R impedances without the need for low value input shunting resistors that would degrade the noise figure. For optimum noise performance, R possible while R
The noise figure is given by the following equation: NF =
10log
where IC1=5.5mA, RE1=12, rb=130, KT/q=26mV at 25°C and R
=50 for a 50 system and 75 for a 75 system.
0
The DC input voltage level VIN can be determined by the equation:
V
RF1 R
and RE2 which aids in producing wideband terminal
F2
1
 
+(IC1+IC3) R
IN=VBE1
E1
R
E1
and the base resistance of Q1 are kept as low as
E1
is maximized.
F2
rb R
KT
E1
R
O
E1
2ql
C1
dB
 
(1)
(2)
where RE1=12, VBE=0.8V, IC1=5mA and IC3=7mA (currents rated at V
=6V).
CC
Under the above conditions, V Level shifting is achieved by emitter-follower Q
provide shunt feedback to the emitter of Q emitter-follower buffer in this feedback loop essentially eliminates problems of shunt feedback loading on the output. The value of R
=140 is chosen to give the desired nominal gain. The DC
F1
output voltage V
V
OUT=VCC
where V From here it can be seen that the output voltage is approximately
3.1V to give relatively equal positive and negative output swings. Diode Q R
F2
operating point of the amplifier. The output stage is a Darlington pair (Q
the DC bias voltage on the input stage (Q value, and also increases the feedback loop gain. Resistor R optimizes the output VSWR (Voltage Standing Wave Ratio). Inductors L roughly 3nH. These improve the high-frequency impedance matches at input and output by partially resonating with 0.5pF of pad and package capacitance.
=6V, R2=225, IC2=8mA and IC6=5mA.
CC
is included for bias purposes to allow direct coupling of
5
to the base of Q1. The dual feedback loops stabilize the DC
1
can be determined by:
OUT
-(IC2+IC6)R2,(4)
and L2 are bondwire and lead inductances which are
is approximately equal to 1V .
IN
and diode Q4 which
3
via RF1. The use of an
1
and Q2) which increases
6
) to a more desirable
1
0
V
CC
Q6
225
R3 140
R2
R0
10 3nH
Q2
RE2 12
Q5
L2
V
OUT
SR00231
R1
650
Q3
L2
V
IN
3nH
Q1
RE1
12
Figure 17. Schematic Diagram
Q4
RF1
140
RF2
200
1997 Nov 07
7
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SA5205AWide-band high-frequency amplifier
POWER DISSIPATION CONSIDERATIONS
When using the part at elevated temperature, the engineer should con­sider the power dissipation capabilities.
At the nominal supply voltage of 6V , the typical supply current is 25mA (32mA Max). For operation at supply voltages other than 6V , see Figure 3 for I
versus VCC curves. The supply current is
CC
inversely proportional to temperature and varies no more than 1mA between 25°C and either temperature extreme. The change is 0.1% per over the range.
The recommended operating temperature ranges are air-mount specifications. Better heat sinking benefits can be realized by mounting the D package body against the PC board plane.
PC BOARD MOUNTING
In order to realize satisfactory mounting of the SA5205A to a PC board, certain techniques need to be utilized. The board must be double-sided with copper and all pins must be soldered to their respective areas (i.e., all GND and V The power supply should be decoupled with a capacitor as close to the V
pins as possible and an RF choke should be inserted
CC
between the supply and the device. Caution should be exercised in the connection of input and output pins. Standard microstrip should be observed wherever possible. There should be no solder bumps or burrs or any obstructions in the signal path to cause launching problems. The path should be as straight as possible and lead lengths as short as possible from the part to the cable connection. Another important consideration is that the input and output should be AC coupled. This is because at V approximately at 1V while the output is at 3.1V . The output must be decoupled into a low impedance system or the DC bias on the output of the amplifier will be loaded down causing loss of output power. The easiest way to decouple the entire amplifier is by soldering a high frequency chip capacitor directly to the input and
pins on the SO package).
CC
=6V, the input is
CC
output pins of the device. This circuit is shown in Figure 18. Follow these recommendations to get the best frequency response and noise immunity . The board design is as important as the integrated circuit design itself.
SCATTERING PARAMETERS
The primary specifications for the SA5205A are listed as S-parameters. S-parameters are measurements of incident and reflected currents and voltages between the source, amplifier and load as well as transmission losses. The parameters for a two-port network are defined in Figure 19.
Actual S-parameter measurements using an HP network analyzer (model 8505A) and an HP S-parameter tester (models 8503A/B) are shown in Figure 20.
Values for the figures below are measured and specified in the data sheet to ease adaptation and comparison of the SA5205A to other high-frequency amplifiers.
V
CC
RF CHOKE
DECOUPLING CAPACITOR
V
IN
AC
COUPLING
CAPACITOR
Figure 18. Circuit Schematic for Coupling and Power Supply
5205A
CAPACITOR
Decoupling
AC
COUPLING
V
OUT
SR00232
S
11
1997 Nov 07
S
21
S
12
a. Two-Port Network Defined
POWER REFLECTED FROM INPUT PORT
— INPUT RETURN LOSS
S
11
S
— REVERSE TRANSMISSION LOSS
12
S
22
OSOLATION
— FORWARD TRANSMISSION LOSS
S
21
OR INSERTION GAIN
— OUTPUT RETURN LOSS
S
22
=
S
11
POWER AVAILABLE FROM GENERATOR AT INPUT PORT
REVERSE TRANSDUCER
=
S
12
S
= TRANSDUCER POWER GAIN
21
S
=
22
POWER GAIN
POWER REFLECTED FROM OUTPUT PORT
POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT
b.
SR00233
Figure 19.
8
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SA5205AWide-band high-frequency amplifier
50 System 75 System
25
vcc = 8v
20
vcc = 7v
25
vcc = 8v
vcc = 7v
20
15
INSERTION GAIN—dB
ZO = 50
= 25oC
T
10
A
12 468 2 468
10
FREQUENCY—MHz
vcc = 6v
2
10
vcc = 5v
a. Insertion Gain vs Frequency (S
10
–15
–20
ISOLATION—dB
–25
–30
12 4681022 468103
10
VCC = 6V
= 50
Z
O
TA = 25oC
FREQUENCY—MHz
c. Isolation vs Frequency (S
40
35
30
25
VCC = 6V
20
INPUT RETURN LOSS—dB
15
OUTPUT RETURN LOSS—dB
10
e. Input (S
= 50
Z
O
TA = 25oC
12 4681022 468103
10
FREQUENCY—MHz
) and Output (S22) Return Loss
11
vs Frequency
OUTPUT
INPUT
vcc = 6v
15
ISOLATION GAIN—dB
3
10
) b. Insertion Gain vs Frequency (S21)
21
) d. S12 Isolation vs Frequency
12
INPUT RETURN LOSS—dB
ZO = 75
= 25oC
T
10
OUTPUT RETURN LOSS—dB
A
12 468 2 468
10
FREQUENCY—MHz
10
–15
–20
ISOLATION—dB
–25
–30
12 461022 468103
10
40
35
30
25
20
15
10
12 4681022 468103
10
OUTPUT
INPUT
FREQUENCY—MHz
vcc = 5v
2
10
ZO = 75
= 25oC
T
A
VCC = 6V
8
FREQUENCY—MHz
VCC = 6V
= 75
Z
O
TA = 25oC
f. Input (S11) and Output (S22) Return Loss
vs Frequency
Figure 20.
10
3
SR00234
1997 Nov 07
9
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SA5205AWide-band high-frequency amplifier
The most important parameter is S
. It is defined as the square root
21
of the power gain, and, in decibels, is equal to voltage gain as shown below:
Z
D=ZIN=ZOUT
P
IN
P
OUT
P
IN
PI=V
for the SA5205A
2
V
IN
Z
D
V
OUT
Z
V
Z
2
I
SA5205
2
D
2
IN
D
2
V
A
Z
D
P
OUT
2
V
OUT
P
2
V
IN
OUT
Z
D
I
PI=Insertion Power Gain VI=Insertion Voltage Gain Measured value for the
SA5205A = |S
P
P
I
P
andV
I
2
|
= 100
21
OUT
|S21|2 100
IN
V
OUT
V
P
IN
S21 10
I
In decibels:
= S
21
2
= 20dB
= 20dB
21(dB)
= 20dB
P
=10 Log | S21|
I(dB)
V
= 20 Log S
I(dB)
P
I(dB)
= V
I(dB)
Also measured on the same system are the respective voltage standing wave ratios. These are shown in Figure 21. The VSWR can be seen to be below 1.5 across the entire operational frequency range.
Relationships exist between the input and output return losses and the voltage standing wave ratios. These relationships are as follows:
INPUT RETURN LOSS=S S
dB=20 Log | S11|
11
dB
11
OUTPUT RETURN LOSS=S22dB S
dB=20 Log | S22|
22
INPUT VSWR=1.5 OUTPUT VSWR=1.5
1dB GAIN COMPRESSION AND SA TURATED OUTPUT POWER
The 1dB gain compression is a measurement of the output power level where the small-signal insertion gain magnitude decreases
1dB from its low power value. The decrease is due to nonlinearities in the amplifier, an indication of the point of transition between small-signal operation and the large signal mode.
The saturated output power is a measure of the amplifier’s ability to deliver power into an external load. It is the value of the amplifier’s output power when the input is heavily overdriven. This includes the sum of the power in all harmonics.
INTERMODULATION INTERCEPT TESTS
The intermodulation intercept is an expression of the low level linearity of the amplifier. The intermodulation ratio is the difference in dB between the fundamental output signal level and the generated distortion product level. The relationship between intercept and intermodulation ratio is illustrated in Figure 22, which shows product output levels plotted versus the level of the fundamental output for two equal strength output signals at different frequencies. The upper line shows the fundamental output plotted against itself with a 1dB to 1dB slope. The second and third order products lie below the fundamentals and exhibit a 2:1 and 3:1 slope, respectively.
The intercept point for either product is the intersection of the extensions of the product curve with the fundamental output.
The intercept point is determined by measuring the intermodulation ratio at a single output level and projecting along the appropriate product slope to the point of intersection with the fundamental. When the intercept point is known, the intermodulation ratio can be determined by the reverse process. The second order IMR is equal to the difference between the second order intercept and the fundamental output level. The third order IMR is equal to twice the difference between the third order intercept and the fundamental output level. These are expressed as:
IP IP3=P
where P level fundamental output signals, IP third order output intercepts in dBm, and IMR second and third order intermodulation ratios in dB. The intermodulation intercept is an indicator of intermodulation performance only in the small signal operating range of the amplifier. Above some output level which is below the 1dB compression point, the active device moves into large-signal operation. At this point the intermodulation products no longer follow the straight line output slopes, and the intercept description is no longer valid. It is therefore important to measure IP compression. One must be careful, however, not to select too low levels because the test equipment may not be able to recover the signal from the noise. For the SA5205A we have chosen an output level of -10.5dBm with fundamental frequencies of 100.000 and
100.01MHz, respectively.
+IMR
2=POUT
OUT OUT
2
+IMR3/2
is the power level in dBm of each of a pair of equal
and IP3 are the second and
2
2
and IP3 at output levels well below 1dB
2
and IMR3 are the
1997 Nov 07
10
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SA5205AWide-band high-frequency amplifier
2.0
1.9
1.8
1.7
1.6
1.5
1.4
INPUT VSWR
1.3
1.2
1.1
1.0
TA = 25oC
= 6V
V
CC
.
ZO = 75
ZO = 50
6
12 41022 46810368
10
8
FREQUENCY—MHz
a. Input VSWR vs Frequency b. Output VSWR vs Frequency
Figure 21. Input/Output VSWR vs Frequency
ADDITIONAL READING ON SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers by Ralph S. Carson of the University of Missouri, Rolla, Copyright 1985; published by John Wiley & Sons, Inc.
+30
THIRD ORDER
+20
+10
INTERCEPT POINT
1dB
COMPRESSION POINT
2.0
1.9
1.8
1.7
1.6
1.5
1.4
OUTPUT VSWR
1.3
1.2
1.1
1.0
T
= 25oC
amb
= 6V
V
CC
ZO = 75
ZO = 50
12 41022 468103
10
FREQUENCY—MHz
SR00235
“S-Parameter T echniques for Faster , More Accurate Network Design”, HP App Note 95-1, Richard W. Anderson, 1967, HP Journal.
“S-Parameter Design”, HP App Note 154, 1972.
2ND ORDER
INTERCEPT
POINT
FUNDAMENTAL
0
dBm
-10
OUTPUT LEVEL
-20
-30
-40
RESPONSE
2ND ORDER
RESPONSE
3RD ORDER
RESPONSE
-60 -50 -40 -30 -20 -10 0 +10 +20 +30 +40 INPUT LEVEL dBm
Figure 22.
SR00236
1997 Nov 07
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SA5205AWide-band high-frequency amplifier
SO8: plastic small outline package; 8 leads; body width 3.9mm SOT96-1
1997 Nov 07
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SA5205AWide-band high-frequency amplifier
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
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to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
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1997 Nov 07
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