Page 1
INTEGRATED CIRCUITS
74F598
8-bit shift register with input storage
registers (3-State)
Product specification
IC15 Data Handbook
1991 Oct 21
Page 2
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
FEA TURES
• High impedance PNP base input for reduced loading (20µA in
High and Low states)
• 8–bit parallel storage register
The shift register load function has been modified to load when both
SHLD
and SHCP are Low. When SHCP is High the shift register
load operation is not performed. Data will be properly shifted on the
rising edge of SHCP when SHLD
is High.
• Shift register has asynchronous direct overriding reset
• Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High.
• Guaranteed shift frequency DC to 105MHz
• Parallel 3–State I/O storage register inputs and shift register
parallel outputs
DESCRIPTION
The 74F598 consists of an 8–bit storage register feeding a
parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both
the storage register and shift register have positive edge–triggered
clocks. The shift register has asynchronous reset and when SHCP
is Low, it has asynchronous load.
TYPE
TYPICAL SHCP f
max
TYPICAL SUPPL Y
CURRENT (TOTAL)
74F598 100MHz 75mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
= 5V ±10%,
V
CC
T
= 0°C to +70°C
amb
20–pin plastic DIP N74F598N SOT146-1
20–pin plastic SOL N74F598D SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) High/
Low
I/On Parallel data input 1.0/0.033 20µA/20µA
Ds0, Ds1 Serial data inputs 1.0/0.033 20µA/20µA
SHCP Shift register clock pulse input 1.0/0.033 20µA/20µA
STCP Storage register clock pulse input 1.0/0.033 20µA/20µA
SHCPEN Shift register clock pulse enable input 1.0/0.033 20µA/20µA
SHLD Shift register load input (active Low) 1.0/0.033 20µA/20µA
SHRST Shift register reset input (active Low) 1.0/0.033 20µA/20µA
S Serial data select input 1.0/0.033 20µA/20µA
OE Output enable input 1.0/0.033 20µA/20µA
Qs Serial data output 50/33 1.0mA/20mA
I/On Parallel data outputs 150/40 3.0mA/24mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
High/Low
PKG DWG #
PIN CONFIGURATION
I/O0
1
I/O1
2
I/O2
3
I/O3
4
I/O4
5
I/O5
6
I/O6
7
I/O7
8
SHLD
9
GND
10 11
1991 Oct 21 853–1583 04407
20
19
18
17
16
15
14
13
12
SF00375
V
CC
S
DS0
DS1
OE
STCP
SHCPEN
SHCP
SHRST
Qs
LOGIC SYMBOL
19
16
15
14
13
12
= Pin 20
V
CC
GND = Pin 10
2
Ds018Ds117I/O01I/O12I/O23I/O34I/O45I/O56I/O67I/O7
S
OE
STCP
SHCPEN
SHCP
SHRST
SHLD
9
Qs
11
8
SF00376
Page 3
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
IEC/IEEE SYMBOL
16
12
14
13
9
15
19
18
17
1
2
3
4
5
6
7
8
EN14
R
G4
4C5/4→
C2
C1
G1
, 5D
1
1, 5D
2D
6, 14
2D
7, 14
2D
13, 14
SRG8
Z6
3D
3D
Z7
3D
Z13
11
SF00377
FUNCTION TABLE
INPUTS INPUTS/OUTPUTS OPERATING MODE
SHRST STCP SHCP SHLD S OE* I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
L X L H X L L L L L L L L L L Clear shift register
Invalid, state of shift register in-
L X L L X L
X ↑ X X X H I0 I1 I2 I3 I4 I5 I6 I7 O7 Load data to storage register
H X ↑ H L L Ds0 O0 O1 O2 O3 O4 O5 O6 O6 Shift right
H X ↑ H H L Ds1 O0 O1 O2 O3 O4 O5 O6 O6
H ↑ L L X H I0 I1 I2 I3 I4 I5 I6 I7 O7
H ↑ L L X X O0 O1 O2 O3 O4 O5 O6 O7 O7
X X X X X H Z Z Z Z Z Z Z Z NC 3–State
H ↑ X H X X NC NC NC NC NC NC NC NC NC Hold
H ↑ H X X X NC NC NC NC NC NC NC NC NC
Notes to function table
D0 – D7 = The level of the steady state inputs to the serial multiplexer.
H = High voltage level
I0 – I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip–flop while the flip–flop outputs ( except Q7) are isolated
from the I/O terminal.
L = Low voltage level
NC= No change
O0 – O7 = The level of the respective Qn flip–flop prior to the last clock Low–to–High transition
X = Don’t care
Z = High impedance ”off” state
* = When the OE
input is High, all I/O terminals are at the High impedance state, sequential operation or cleaning of the register is not affected.
↑ = Low–to–High clock transition
↑
= Not Low–to–High clock transition
determinate when signal is removed
Load data directly to shift register
Data transferred from storage
register to shift register
Hold (no storage or shift register
load
1991 Oct 21
3
Page 4
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
LOGIC DIAGRAM
16
OE
12
SHRST
14
SHCPEN
13
SHCP
9
SHLD
19
S
18
Ds0
17
Ds1
15
STCP
I/O0
I/O1
1
2
1D
C1
1D
2D
C2
S
R
C2
3S
S
3R
VCC = Pin 20
GND = Pin 10
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
C1
3
4
5
6
7
8
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
R
C2
3S
S
3R
R
C2
3S
S
3R
R
C2
3S
S
3R
R
C2
3S
S
3R
R
C2
3S
3R
S
R
C2
3S
S
3R
R
9
SF00378
Qs
1991 Oct 21
4
Page 5
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
V
I
T
V
I
OUT
OUT
amb
T
Supply voltage –0.5 to +7.0 V
CC
Input voltage –0.5 to +7.0 V
IN
Input current –30 to +5 mA
IN
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state Qs
Operating free air temperature range 0 to +70
Storage temperature range –65 to +150
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
T
V
V
V
I
I
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
CC
High–level input voltage 2.0 V
IH
Low–level input voltage 0.8 V
IL
I
Input clamp current –18 mA
Ik
High–level output current Qs –1 mA
Low–level output current Qs 20 mA
Operating free air temperature range 0 +70
PARAMETER RATING UNIT
CC
I/O0 – I/O7
40 mA
48 mA
V
°C
°C
MIN NOM MAX
I/O0 – I/O7 –3 mA
I/O0 – I/O7 24 mA
°C
1991 Oct 21
5
Page 6
Philips Semiconductors Product specification
3
74F5988-bit shift register with input storage registers (3-State)
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
I
OZH
I
OZL
V
V
V
I
I
I
OS
I
CC
High-level output voltage
OH
Low-level output voltage VCC = MIN, VIL = MAX, ±10%V
OL
Input clamp voltage VCC = MIN, II = I
IK
I
Input current at maximum input voltage others VCC = MAX, VI = 7.0V 100 µA
I
High–level input current VCC = MAX, VI = 2.7V 20 µA
IH
Low–level input current VCC = MAX, VI = 0.5V –20 µA
IL
Off–state output current,
+ I
IH
High–level voltage applied
Off–state output current,
+ I
IL
Low–level voltage applied
Short–circuit output current
Supply current (total) I
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
PARAMETER TEST LIMITS UNIT
CONDITIONS
Qs VCC = MIN,
IOH = –1mA
VIL = MAX,
VIL = MAX,
I/On VIH = MIN,
IOH = –3mA
VIL = MAX,
VIH = MIN, IOL = MAX ±5%V
IK
1
±10%V
±5%V
±10%V
±5%V
MIN TYP2MAX
2.5 V
CC
2.7 3.4 V
CC
2.4 V
CC
2.7 3.3 V
CC
CC
CC
0.30 0.50 V
0.30 0.50 V
–0.73 -1.2 V
I/On VCC = MAX, VI = 5.5V 1 mA
= 2.7V 70
O
= 0.5V –70
O
68 100 mA
73 105 mA
= 5V, T
CC
OS
= 25°C.
amb
tests should be performed last.
I/On VCC = MAX, V
only VCC = MAX, V
VCC = MAX -60 -150 mA
I
CCH
CCLVCC
I
CCZ
OS
= MAX 80 110 mA
, the use of High-speed test apparatus and/or sample-and-hold
µA
µA
1991 Oct 21
6
Page 7
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
max
Maximum clock frequency SHCP Waveform 1 85 100 70 MHz
STCP 140 160 130
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
SHCP to Qs
Propagation delay
STCP to Qs (SHLD = Low)
Propagation delay
SHLD to Qs
Propagation delay
SHCP to I/On
Propagation delay
SHLD to I/On
Waveform 1
Waveform 1
Waveform 1
Waveform 1
Waveform 1
9.5
6.5
10.0
7.0
9.0
6.0
8.5
5.0
7.5
6.0
11.5
8.5
11.5
8.5
11.0
8.0
10.5
7.0
9.5
8.0
Propagation delay, SHRST to I/On Waveform 2 6.5 9.0 12.0 6.0 12.5 ns
Propagation delay, SHRST to Qs Waveform 2 6.0 7.5 10.5 5.0 11.0 ns
Output enable time to
High or Low
Output disable time to
High or Low
Waveform 5
Waveform 6
Waveform 5
Waveform 6
3.5
3.0
1.5
4.0
5.5
5.0
3.5
6.0
14.0
11.5
14.5
11.5
13.5
10.5
13.5
9.5
12.5
11.0
8.5
7.5
6.5
9.0
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
8.5
6.0
9.0
6.5
8.0
5.5
7.0
4.5
6.5
6.0
3.0
2.5
1.5
4.0
16.0
12.0
16.0
12.5
15.5
11.5
15.5
10.5
14.5
11.5
9.5
8.5
7.5
9.5
UNIT
ns
ns
ns
ns
ns
ns
ns
1991 Oct 21
7
Page 8
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF, RL = 500Ω CL= 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
(H)
s
t
(L)
s
t
(H)
h
t
(L)
h
t
(H)
s
t
(L)
s
t
(H)
h
t
(L)
h
t
(H)
s
t
(L)
s
t
(H)
h
t
(L)
h
t
(H) Setup time, High, STCP to SHLD W aveform 4 7.0 8.0 ns
s
t
(L) Hold time, Low, STCP to SHLD (hold mode) Waveform 4 0.0 0.0 ns
h
ts (H)
t
(L)
s
t
(H)
h
t
(L)
h
t
(H) Setup time, High, SHLD to SHCP↑ Waveform 3 7.5 8.5 ns
s
t
(H)
w
t
(L)
w
t
(H)
w
t
(L)
w
t
(L) SHRST Pulse width, Low Waveform 1 4.0 4.0 ns
w
t
(L) SHLD Pulse width, Low Waveform 1 4.0 5.0 ns
w
t
rec
Setup time, High or Low
Dsn to SHCP
Hold time, High or Low
DSn to SHCP
Setup time, High or Low
I/On to STCP
Hold time, High or Low
I/On to STCP
Setup time, High or Low
S to SHCP
Hold time, High or Low
S to SHCP
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Setup time, High or Low, SHCPENto SHCP Waveform 3
Hold time, High or Low, SHCPENto SHCP Waveform 3
SHCP Pulse width,
High or Low
STCP Pulse width,
High or Low
Waveform 1
Waveform 1
0.0
3.5
0.0
2.5
2.5
2.5
0.0
0.0
3.5
3.0
2.5
3.0
0.0
2.0
0.0
4.5
5.5
4.0
4.5
4.0
Recovery time, SHRST to SHCP Waveform 2 0.0 0.0 ns
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
1.5
4.5
0.0
3.0
2.5
3.0
1.5
2.0
4.0
3.5
3.0
3.0
0.0
2.0
0.0
5.5
6.5
4.0
5.5
4.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1991 Oct 21
8
Page 9
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
TYPICAL TIMING DIAGRAM
OE
SHRST
SHLD
SHCP
SHCPEN
STCP
Ds0
Ds1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S
Don’t careDon’t care
Don’t careDon’t care
Don’t careDon’t care
1991 Oct 21
Qs
output Hi–Z input Hi–Z shift and output
SF00379
9
Page 10
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
AC WAVEFORMS
STCP,
SHCP,
SHLD
SHRST
I/On,
Qs
,
V
M
PHL
tw(H)
1/f
max
V
M
tw(L)t
V
M
V
M
t
PLH
V
M
SF00380
Waveform 1. Propagation delay for clock input to output, clock
pulse widths, and maximum clock frequency, shift register
reset and load inputs to serial data output
SHRST
SHCP
I/On,
Qs
V
M
t
PHL
V
M
V
M
t
rec
V
M
SF00381
Waveform 2. Propagation delay for shift register reset to serial
data output, shift register reset to shift register, shift register
input recovery time
Dsn, I/On,
SHCP ,
SHLD
SHCPEN
SHCP,
STCP
SHLD
,
V
M
t
(H) th(H)
s
V
M
V
M
V
V
M
ts(L) th(L)
V
M
M
SF00382
Waveform 3. Setup time and hold times
V
th(L)
V
M
M
SF00383
STCP
SHLD
V
M
ts(H)
Waveform 4. Setup time and hold time
OE
I/On
V
M
t
PZH
10%
90%
V
V
M
t
PHZ
M
VOH -0.3V
0V
SF00384
Waveform 5. 3-State output enable time to High level, output
disable time from High level and transition time to High level
OE
I/On
V
t
PZL
M
90%
V
M
t
PLZ
V
M
10%
3.5V
VOL +0.3V
SF00385
Waveform 6. 3-State output enable time to Low level, output
disable time from Low level and transition time to Low level
Notes to AC waveforms
1. For all waveforms, V
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
1991 Oct 21
= 1.5V.
M
10
Page 11
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for Open Collector Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
7.0V
R
L
C
R
L
L
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
t
w
V
M
10%
)
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
= Load resistor;
R
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
family
74F
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00128
1991 Oct 21
11
Page 12
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
1991 Oct 21
12
Page 13
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1991 Oct 21
13
Page 14
Philips Semiconductors Product specification
74F5988-bit shift register with input storage registers (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05145
yyyy mmm dd
14
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