Page 1
INTEGRATED CIRCUITS
74F573
Octal transparent latch (3-State)
74F574
Octal transparent latch (3-State)
Product specification
IC15 Data Handbook
1989 Oct 16
Page 2
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
FEA TURES
•74F573 is broadside pinout version of 74F373
•74F574 is broadside pinout version of 74F374
•Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
•Useful as an Input or Output port for Microprocessors
•3-State Outputs for Bus interfacing
•Common Output Enable
•74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
•3-State Outputs glitch free during power-up and power-down
•These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE
independent to the latch operation. When OE
transparent data appears at the outputs. When OE
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
) controls all eight 3-State buffers
) control gates.
is Low, the latched or
is High, the
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE
independently of the latch operation. When OE
or transparent data appears at the outputs. When OE
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE
74F573 5.0ns 35mA
TYPE TYPICAL f
74F574 180MHz 50mA
PROPAGATION DELAY
) controls all eight 3-State buffers
TYPICAL
MAX
) control gates.
is Low, the latched
is High, the
TYPICAL SUPPL Y
CURRENT
(TOTAL)
TYPICAL SUPPL Y
CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
V
DESCRIPTION
20-Pin Plastic DIP N74F573N, N74F574N SOT146-1
20-Pin Plastic SOL N74F573D, N74F574D SOT163-1
20-Pin Plastic SSOP N74F573DB SOT339-1
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
E (74F573) Latch Enable input (active falling edge) 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP (74F574) Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1989 Oct 16 853-0083 97897
2
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Page 3
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
PIN CONFIGURATION – 74F573
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
SF01073
LOGIC SYMBOL – 74F573
345678
2
D0 D1Q1D2
11 E
1
OE
Q0
Q2 Q3D3Q4D4Q5
PIN CONFIGURATION – 74F574
20
V
CC
Q0
19
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
E
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
20
19
18
17
16
15
14
13
12
SF01074
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
CC
LOGIC SYMBOL – 74F574
D5
D7
Q6D6Q7
9
11 CP
1
OE
345678
2
D0 D1Q1D2
Q0
Q2 Q3D3Q4D4Q5
D5
9
D7
Q6D6Q7
141516171819
VCC=Pin 20
GND=Pin 10
LOGIC SYMBOL (IEEE/IEC) – 74F573
1
11
2
3
4
5
6
7
8
9
EN1
EN2
2D
1
SF01077
19
18
17
16
15
14
13
12
1213
SF01075
141516171819
VCC=Pin 20
GND=Pin 10
LOGIC SYMBOL (IEEE/IEC) – 74F574
1
11
2
3
4
5
6
7
8
9
EN1
C2
2D
1
SF01078
1213
SF01076
19
18
17
16
15
14
13
12
1989 Oct 16
3
Page 4
Philips Semiconductors Product specification
OPERATING MODES
74F573/74F574Latch/flip-flop
LOGIC DIAGRAM – 74F573
D0 D1 D2 D3 D4 D5 D6 D7
23456789
EDQ EDQ EQDEDQ EDQ EDQ EDQ EDQ
11
E
1
OE
VCC=Pin 20
GND=Pin 10
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1213141516171819
SF01079
FUNCTION TABLE – 74F573
INPUTS
OE E Dn
L
L
L
L
H
H
H
↓
↓
L
l
h
INTERNAL
REGISTER
L
H
L
H
L L X NC NC Hold
H
H
L
H
X
Dn
NC
Dn
H = High voltage level
h = High voltage level one setup time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one setup time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low E transition
OUTPUTS
Q0 – Q7
L
H
L
H
Z
Z
LOGIC DIAGRAM – 74F574
D0 D1 D2 D3 D4 D5 D6 D7
23456789
D
Load and read register
Latch and read register
Disable outputs
11
CP
1
OE
VCC=Pin 20
GND=Pin 10
1989 Oct 16
CPDQ CPDQ CP Q
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CPDQ CPDQ CPDQ CPDQ CPDQ
4
1213141516171819
SF01080
Page 5
Philips Semiconductors Product specification
OPERATING MODES
SYMBOL
PARAMETER
UNIT
74F573/74F574Latch/flip-flop
FUNCTION TABLE – 74F574
INPUTS
OE CP Dn
L
L
↑
↑
l
h
INTERNAL
REGISTER
L
H
L ↑ X NC NC Hold
H ↑ Dn Dn Z Disable outputs
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
= Not a Low-to-High clock transition
↑
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5.0 mA
Voltage applied to output in High output state –0.5 to +V
Current applied to output in Low output state 48 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature –65 to +150 °C
PARAMETER RATING UNIT
OUTPUTS
Q0 – Q7
L
H
Load and read register
CC
V
RECOMMENDED OPERATING CONDITIONS
V
V
V
I
I
I
T
CC
IH
IL
IK
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –3 mA
Low-level output current 24 mA
Operating free-air temperature range 0 70 °C
LIMITS
MIN NOM MAX
1989 Oct 16
5
Page 6
Philips Semiconductors Product specification
NO TAG
VOHHigh-level output voltage
V
CC
MIN, V
IL
MAX,
VOLLow-level output voltage
V
CC
MIN, V
IL
MAX,
I
t
()
74F573/74F574Latch/flip-flop
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
V
V
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
CC
= MIN, V
p
p
IK
Input clamp voltage VCC = MIN, II = I
VIH = MIN, IOH = MAX
V
= MIN, V
VIH = MIN, IOL = MAX
Input current at
maximum input voltage
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.5V –0.6 mA
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short-circuit output current
I
CCH
I
CCL
Supply
curren
(total)
I
CCZ
I
CCH
I
CCL
I
CCZ
NO TAG
74F573 VCC = MAX
74F574 VCC = MAX
= MAX,
= MAX,
VCC = MAX, VI = 7.0V 100 µA
VCC = MAX, VO = 2.7V 50 µA
VCC = MAX, VO = 0.5V –50 µA
VCC = MAX –60 –150 mA
±10%V
±5%V
±10%V
±5%V
IK
CC
CC
CC
CC
MIN TYP
NO TAG
MAX
2.4 V
2.7 3.4 V
0.35 0.50 V
0.35 0.50 V
–0.73 –1.2 V
30 40 mA
35 50 mA
40 60 mA
45 65 mA
50 70 mA
55 85 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
tests should be performed last.
OS
UNIT
1989 Oct 16
6
Page 7
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL P ARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
Maximum Clock frequency
Propagation delay
CP to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
74F573
74F574
TEST
CONDITIONS
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
Waveform
NO TAG
T
= +25°C
amb
VCC = +5V
CL = 50pF, RL = 500Ω
T
= 0°C to +70°C
amb
VCC = +5V ± 10%
CL = 50pF, RL = 500Ω
UNIT
MIN TYP MAX MIN MAX
3.0
1.0
4.5
3.0
2.5
2.5
1.0
1.0
5.5
3.5
8.5
5.0
5.5
5.5
3.0
2.5
8.0
6.0
11.5
7.0
9.5
8.0
6.0
5.5
2.5
1.0
4.0
2.5
2.0
2.0
1.0
1.0
9.0
7.0
12.5
8.0
10.5
8.5
6.5
5.5
ns
ns
ns
ns
160 180 150 MHz
3.5
3.5
2.5
3.0
1.0
1.0
5.0
5.0
4.5
5.0
3.0
2.5
7.5
7.5
7.5
8.0
5.5
5.5
3.0
3.0
2.0
3.0
1.0
1.0
8.0
8.0
7.5
8.5
6.0
6.0
ns
ns
ns
AC SETUP REQUIREMENTS
SYMBOL PARAMETER
ts(H)
ts(L)
th(H)
th(L)
tw(H)
ts(H)
t
(L)
s
th(H)
t
(L)
h
tw(H)
tw(L)
Setup time,
Dn to E
Hold time,
Dn to E
E pulse width,
High
Setup time,
Dn to CP
Hold time,
Dn to CP
CP Pulse width,
High or Low
74F573
74F574
LIMITS
TEST
CONDITIONS
= +25°C
amb
VCC = +5V
C
= 50pF, RL = 500Ω
L
T
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
C
= 50pF, RL = 500Ω
L
UNIT
T
MIN TYP MAX MIN MAX
Waveform 4
Waveform 4
0.0
1.5
2.5
4.0
0.0
2.0
2.5
4.0
ns
ns
Waveform NO TAG 3.0 3.5 ns
Waveform NO TAG
Waveform NO TAG
Waveform NO TAG
2.5
2.5
0
0
3.0
3.5
3.0
3.0
0
0
3.0
4.0
ns
ns
ns
1989 Oct 16
7
Page 8
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
AC WAVEFORMS
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
E, CP
Q
n
V
M
tW(H)
t
PHL
V
M
tW(L)
V
M
V
M
t
PLH
V
M
SF01081
Waveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
and Maximum Clock Frequency
CP
Dn
V
V
M
M
th(H)ts(H)
V
M
V
V
M
M
th(L)ts(L)
V
M
SF00191
Waveform 3. Data Setup and Hold Times
OE
Qn
V
t
PZH
M
V
V
M
t
PHZ
VOH -0.3V
M
SF00343
Dn
Qn
V
M
t
PLH
V
M
t
PHL
V
M
V
M
SF01082
Waveform 2. Propagation Delay for Data to Outputs
Dn
E
V
V
M
M
V
M
VMV
ts(L)ts(H)
M
V
M
SF00992
th(L)th(H)
Waveform 4. Data Setup and Hold Times
V
t
PZL
M
V
OE
Qn
0V
V
M
t
PLZ
M
VOL +0.3V
SF00344
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
1989 Oct 16
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
8
Page 9
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
TEST CIRCUIT AND WAVEFORM
V
V
PULSE
GENERATOR
IN
R
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
T
D.U.T.
CC
V
OUT
7.0V
R
L
C
R
L
L
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
t
w
V
M
10%
)
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
= Load resistor;
R
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
family
74F
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00777
1989 Oct 16
9
Page 10
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
1989 Oct 16
10
Page 11
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1989 Oct 16
11
Page 12
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
1989 Oct 16
12
Page 13
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
NOTES
1989 Oct 16
13
Page 14
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05141
yyyy mmm dd
14
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