Datasheet MTV130P, MTV130P20 Datasheet (MYSON)

ut notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

TECHNOLOGY

GENERAL DESCRIPTION

Character bordering, shadowing and blinking effect.

4-channel/8-bit PWM D/A converter output.

ing on window and full-screen self-test pattern generator.

menu is formed by 15 rows x 30 columns, which can be

On-Screen Display for LCD Monitor

FEATURES

• Horizontal SYNC input up to 150 KHz.

• Acceptable wide-range pixel clock up to 150 MHz.

• Full screen self-test pattern generator.

• Full-screen display consists of 15 (rows) by 30 (columns)
characters.

• Two font size 12x16 or 12x18 dot matrix per character.

• True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.

• 8 color selection maximum per display character.

• Double character height and/or width control.

• Programmable positioning for display screen center.

•

• Programmable character height (18 to 71 lines) control.

• Row to row spacing control to avoid expansion distortion.

• 4 programmable windows with multi-level operation.

• Shadowing on windows with programmable shadow
width/height/color.

• Software clears bit for full-screen erasing.

• Intensity and fast blanking output.

• Fade-in/fade-out or blending-in/blending-out effects.

•

• Compatible with SPI bus or I2C interface with slave
address 7AH (slave address is mask option).

• 16-pin or 20-pin PDIP/SOP package.

MTV130MYSON

MTV130 is designed for LCD monitor applications to
display built-in characters or fonts onto an LCD monitor
screens. The display operation occurs by transferring data
and control information from the micro-controller to RAM
through a serial data interface. It can execute full-screen
display automatically, as well as specific functions such as
character background, bordering, shadowing, blinking,
double height and width, font by font color control, frame
positioning, frame size control by character height and row­to-row spacing, horizontal display resolution, full-screen
erasing, fade-in/fade-out effect, windowing effect, shadow-

MTV130 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD

positioned anywhere on the monitor screen by changing
vertical or horizontal delay.

BL OCK DIAGRAM

SSB

SCK

SDA

ARWDB
HDREN

VDREN

NROW

VFLB

VSP

VERTD

HFLB

HORD

HSP

NC

XIN

PWM0
PWM1
PWM2
PWM3

SERIAL DATA

ADDRESS BUS

ADMINISTRATOR

7

CH

CHS

8

8

DISPLAY CONTROL

CONVERTER

INTERFACE

VERTICAL

DISPLAY

CONTROL

HORIZONTAL

CLOCK

GENERATOR

PWM D/A

8

DATA

9

ROW, COL
ACK

5

RCADDR

9

DADDR

9

FONTADDR

5

WINADDR

5

PWMADDR

5

LPN
NROW
VDREN

ARWDB
HDREN

VCLKX

8

DATA

8 LUMAR

DATA

DISPLAY & ROW

CWS

DATA

LPN

CWS

VCLKS

8

VERTD

8

HORD

7

LUMAR
LUMAG
LUMAB

BLINK

VCLKX

CHS

DATA

CH

CONTROL

REGISTERS

8

CHARACTER ROM

USER FONT RAM

5

LUMINANCE &

BORDGER

GENERATOR

8

WINDOWS &

FRAME

CONTROL

WRWGWB

FBKGC

COLOR

ENCODER

BLANK

POWER ON

RESET

LUMAG
LUMAB
BLINK

8

CRADDR

LUMA
BORDER

BSEN
SHADOW
OSDENB
HSP
VSP

PRB

VDD

VSS

VDDA

VSSA

ROUT
GOUT
BOUT
FBKG
HTONE

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification witho

Revision 1.0 1/18 28/April/2000

TECHNOLOGY

This ground pin is used to internal circuitry.

This is a clock input pin. MTV130 is driven by an

external pixel clock source for all the logics inside. The frequency of XIN

must be the integral time of pin HFLB.

Positive 5 V DC supply for internal circuitry. And a 0.1uF

This pin is used to input the horizontal synchronizing

signal. It is a leading edge triggered and has an internal pull-up resistor.

Open-Drain PWM D/A conv er t er 0.

The output pulse width is program-

mable by the register of Row 15, Column 23.

Open-Drain PWM D/A conv er t er 1.

The output pulse width is program-

mable by the register of Row 15, Column 24.

Open-Drain PWM D/A conv er t er 2.

The output pulse width is program-

mable by the register of Row 15, Column 25.

Open-Drain PWM D/A conv er t er 3.

The output pulse width is program-

mable by the register of Row 15, Column 26.

1.0 PIN CONNECTION

MTV130MYSON

VSS

XIN

NC

VDD

HFLB

SSB
SDA
SCK

1
2
3
4
5
6
7
8

16

VSS

15

ROUT

14

GOUT

13

BOUT

12

FBKG

MTV130P-xx

11

INT
VFLB

10

VDD

9

2.0 PIN DESCRIPTIONS

Name I/O

VSS - 1 1 Ground .

XIN I 2 2 Pixel clock input .

Pin No.

P16 P20

1

VSS

2

XIN

3

NC

4

VDD

SSB
SDA
SCK

5
6
7
8
9
10

HFLB

PWM0
PWM1

Des cripti ons

20

VSS

19

ROUT

18

GOUT

17

BOUT

16

FBKG

15

INT
VFLB

14

MTV130P20-xx

VDD

13

PWM3

12

PWM2

11

NC I 3 3 No connection .

VDD - 4 4 Pow er supp ly.

decoupling capacitor should be connected across to VDD and VSS.

HFLB I 5 5 Horizont al input.

SSB I 6 6 Serial in t erf ace enable. It is used to enable the serial data and is also

used to select the operation of I2C or SPI bus. If this pin is left floating,
I2C bus is enabled, otherwise the SPI bus is enabled.

SDA I 7 7 Serial data input . The external data transfer through this pin to internal

display registers and control registers. It has an internal pull-up resistor.

SCK I 8 8 Serial clo ck in put . The clock-input pin is used to synchronize the data

transfer. It has an internal pull-up resistor.

PWM0 O - 9

PWM1 O - 10

PWM2 O - 11

PWM3 O - 12

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3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission

should be starting from pulling SSB to "low" level, enabling MTV130 to receiving mode, and retain "low" level

until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

Format (a) R - C - D

Format (b) R - C - D

Format (c) R - C - D

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting

Vert i cal inpu t .

It is leading triggered and has an internal pull-up resistor.

16-color selection is achievable by combining

this intensity pin with R/G/B output pins.

This ground pin is used to internal circuitry.

MTV130MYSON

Name I/O

VDD - 9 13 Power supp ly. Positive 5 V DC supply for internal circuitry and a 0.1uF

VFLB I 10 14

INT O 11 15 Intensity color output.

FBKG O 12 16 Fast Blanking outpu t. It is used to cut off external R, G, B signals of

BOUT O 13 17 Blu e color output. It is a blue color video signal output.

GOUT O 14 18 Green c ol o r outp ut . It is a green color video signal output.

ROUT O 15 19 Red color outp ut . It is a red color video signal output.

VSS - 16 20 Groun d.

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

Pin No.

Des cripti ons

P16 P20

decoupling capacitor should be connected across to VDD and VSS.

This pin is used to input the vertical synchronizing signal.

VGA while this chip is displaying characters or windows.

3.1.1 SPI bus

SSB

SCK

SDA

There are three transmission formats shown as below:

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where R=Row address, C=Column address, D=Display data

3.1.2 I2C bus

2

I
from writing the slave address 7AH to MTV130. The protocol is shown in Figure 2.

MS
B

first byte last byte

FIGURE 1. Data Tran s m issio n Prot ocol (SPI)

LSB

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Format (a) S - R - C - D

Format (b) S - R - C - D

Format (c) S - R - C - D

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and

increase transmission efficiency. The row and column address will be incremented automatically when the for-

mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy

There are 2 types of data should be accessed through the serial data interface, one is

ADDRESS

bytes of dis-

play registers, and other is

of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column

addresses when transferring data from external controller. The bit6 of column address is used to differentiate

the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is

addres s byt es, bit 5 of col u m n addr ess is th e MSB (bit8) and data bytes are the 8 LSB (bit7~bi t 0) of dis-

play fonts address

played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of

column address of address bytes again.

(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is

configured as the state diagram shown in Figure 3.

The configuration of transmission formats.

Addr ess Bytes

Attr ibut e Bytes

FIGURE 2. Dat a Trans m i ssion Pro t o c ol (I

SCK

MTV130MYSON

SDA

START ACK

B7 B6 B0 B7 B0

First byte

second byte last byte

2

ACK STOP

C)

There are three transmission formats shown as below:

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where S=Slave address, R=Row address, C=Column address, D=Display data

Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to

data.

TABLE 1.

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Row 1 0 0 x R3 R2 R1 R0 a,b,c

of Displ ay Reg.

Column

Column

0 0 D8 C4 C3 C2 C1 C0 a,b

ab

0 1 D8 C4 C3 C2 C1 C0 c

c

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 0 1 R4 R3 R2 R1 R0 a,b,c

of Displ ay Reg.

Column

Column

0 0 x C4 C3 C2 C1 C0 a,b

ab

0 1 x C4 C3 C2 C1 C0 c

c

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c

ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5

used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at

to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis­address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format

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3.2 Address bus adminis tr ator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external

data write in. The external data write through serial data interface to registers must be synchronized by inter-

nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-

nal write using format (c).

3.3 Verti cal di sp l ay cont r ol

The vertical display control can generates different vertical display sizes for most display standards in current

cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as

The vertical display center for full screen display could be figured out according to the information of vertical

Repeat Li n e Weigh t

FIGURE 3. Transmi s s i on State Diagram

0, X

MTV130MYSON

X, X

DA

format (c)

COL

X, X

c

1, X

c

0, 1

Initiate

1, X

ROW

0, 1

0, 0

Input = b7, b6

format (a)

format (b)

COL

ab

0, 0

X, X

DA

1, X

ab

monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti­Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time

TA B L E 2. Repeat lin e weig h t of ch aract er

CH6 - CH0

CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18

CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1

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character would not be repeated.

3.4 Hori zontal dis pl ay contr o l

The horizontal display control is used to generate control timing for horizontal display based on double char-

3.5 Disp l ay & Row contr ol regist ers

are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-

play register has its corresponding character address on ADDRESS byte, its corresponding background color,

30

of DISPLAY REGISTERS

A TTRIBUTE

CRTL REG

TA B L E 3. Repeat line nu m ber of ch arac ter

MTV130MYSON

Repeat Line

Weight

+1 - - - - - - - - v - - - - - - - - ­+2 - - - - v - - - - - - - v - - - - ­+4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - ­+16 - v v v v v v v v v v v v v v v v ­+17 v v v v v v v v v v v v v v v v v ­+18 v v v v v v v v v v v v v v v v v v

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

acter width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line
includes 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay
starting from HFLB leading edge is calculated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P
Where P = 1 XIN pixel display time

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Repeat Lin e #

The internal RAM contains display and row control registers. The display registers have 450 locations which

1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at col­umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.

ROW # COLUMN #

0 1 28 29

0
1

ROW

CHARACTER ADDRESS BYTES

13
14

FIGURE 4. Ad d r ess By t es of Disp l ay Regist ers Memory Map

31

R
E
S
E
R
V
E
D

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CRADDR - Define ROM character address from address 0 to 511.

Row Control Registers, (Row 0 - 14)

CHS - Define double height character to the respective row.

ATTRIBUTE BYTES:

CHARACTER ATTRIBUTE BYTES

of DISPLAY REGISTERS

WINDOW1 ~ WINDOW4

PWM D/A

RESERVED

WINDOW SHADOW COLOR

ROW # COLUMN #

0 1 28 29 30 31

0
1

13
14

COLUMN#

ROW 15

0 11 12 22 23 27 28 31

FRAME

CRTL REG

MTV130MYSON

RESERVED

CRTL REG

COLUMN#

ROW 16

ADDRESS BYTES:
Address registers,

b8 b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

COLN 30

CWS - Define double width character to the respective row.

b7 b6 b5 b4 b3 b2 b1 b0

- BGR BGG BGB BLINK R G B

0 1 2 31

RESERVED

FIGURE 5. Attri b ut e Byt es of Disp l ay Registers Memory Map

CRADDR

b7 b6 b5 b4 b3 b2 b1 b0

- - - - - - CHS CWS

BGR, BGG, BGB - These three bits define the color of the background for its relative address character. If all

three bits are clear, no background will be shown(transparent). Therefore, total 7 back­ground color can be selected.

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MTV130MYSON

BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames.

R, G, B - These three bits are used to specify its relative address character color.

multi-color fonts. The 496 standard fonts are located from address 0 to 495. And the 16 multi-color fonts are

located from address 496 to 511. Each character and symbol consists of 12x18 dots matrix. The detail pattern

CHARACTERS AND SYMBOLS PATTERN

The color fonts comprises three different R, G, B fonts. When the code of color font is accessed, the separate

R/G/B dot pattern is output to corresponding R/G/B output. See Figure 6 for the sample displayed color font.

TERS AND SYMBOLS PATTERN

encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character

Background Color

FIGURE 6. Example of Mul t i -Colo r Fon t

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3.6 Charac ter ROM

MTV130 character ROM contains 512 built-in characters and symbols including 496 standard fonts and 16

structures for each character and symbols are shown in “
page18.

” on

3.7 Multi -Colo r Font

Note: No black color can defined in color font, black window underline the color font can make the dots
become black in color. The detail pattern structures for each character and symbols are shown in “CHARAC-

” on page 18.

B

G

R

Magent
Green
Blue
Cyan

TABLE 4. The Multi -Color Font Color Selection

R G B

0 0 0

Blue 0 0 1

Green 0 1 0

Cyan 0 1 1

Red 1 0 0

Magent 1 0 1

Yellow 1 1 0

White 1 1 1

3.8 L u mi n ance & bor der generator

There are 3 shift registers included in the design which can shift out of luminance and border dots to color
will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with

blackedge for right and bottom sides only.

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MTV130MYSON

3.9 Wind o w and frame cont r ol

The display frame position is completely controlled by the contents of VERTD and HORD. The window size

. Window

1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed infor-

mation is described as follows:

Window control registers,

START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the

WSHD - Enable shadowing on the window.

Frame control registers,

step is 4 Horizontal display lines. The initial value is 4 after power up.

CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character

ROW START ADDR

ROW END ADDR

COL START ADDR

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and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure5

1.
ROW 15

Column

0,3,6,OR 9

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

MSB LSB

Column

1,4,7,OR 10

Column

2,5,8,OR 11

WEN - Enable the relative background window display.

R, G, B - Specify the color of the relative background window.

2.
ROW 15

Column 12

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

COL END ADDR

MSB LSB

start address is greater than the end address, the window will be disabled.

b7 b6 b5 b4 b3 b2 b1 b0

VERTD

MSB LSB

WEN - WSHD

R G B

VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each

b7 b6 b5 b4 b3 b2 b1 b0

Column 13

MSB LSB

HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each

step is 6 dots. The initial value is 15 after power up.

Column 14

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b7 b6 b5 b4 b3 b2 b1 b0

- CH6 CH5 CH4 CH3 CH2 CH1 CH0

vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when
the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the con-

HORD

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tents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2

This byte is reserved for internal testing.

be appended below each display row, and the maximum space is 31 lines. The initial value is 0

BSEN - Enable the bordering and shadowing effect.

FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state

function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly

RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set

FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the

TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,

while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are

in high impedance state. The initial value is 0 after power up.

FSS - Font size selection.

and Table 3 for detail description of this operation.

MTV130MYSON

Column 15

Column 16

RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will

Column 17

OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.

SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise

b7 b6 b5 b4 b3 b2 b1 b0

Reserved

b7 b6 b5 b4 b3 b2 b1 b0

- - - RSPACE
MSB LSB

after power up.

b7 b6 b5 b4 b3 b2 b1 b0

OSDEN BSEN SHADOW FBEN BLEND WENCLR RAMCLR FBKGC

the bordering is chosen.

or vice verca.

BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blendinf-in/blending-out

takes about 0.5 second to fully display the whole menu or to disappear completely.

WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after

power up.

to "1". The initial value is 0 after power up.

displaying of characters or windows, otherwise, it outputs high only during the displaying of charac­ter.

Column 18

B7 b6 b5 b4 b3 b2 b1 b0

TRIC FSS - DWE HSP VSP PWM1 PWM0

= 1 ⇒ 12x18 font size selected.
= 0 ⇒ 12x16 font size selected.

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DWE - Enable double width. When the bit is set to “1”, the display of OSD menu can change to half resolution

Accept positive polarity Hsync input.

Accept negative polarity Hsync input.

Accept positive polarity Vsync input.

Accept negative polarity Vsync input.

malfunction may occur.

CSR, CSG, CSB - Define the color of bordering or shadowing on characters. The initial value is (0, 0, 0) after

force the FBKG pin output to high to disable video RGB while

PWMDA samp l i ng r ate

XIN frequency /(8 * 256)

XIN frequency /(4 * 256)

XIN frequency /(2 * 256)

XIN frequency /(1 * 256)

MTV130MYSON

Fonts desig n ed to be 12x18 displ ay

FIGURE 7. 12x18 and 12x16 Fonts

for double character width, and then the number of pixels of each line should be even. The initial value
is 0 after power up.

HSP - = 1 ⇒

= 0 ⇒

VSP - = 1 ⇒

= 0 ⇒

PWM1, PWM0 - Select the PWMCK output frequency.

= (0, 0) ⇒ XIN frequency /8

= (0, 1) ⇒ XIN frequency /4
= (1, 0) ⇒ XIN frequency /2
= (1, 1) ⇒ XIN frequency /1
The initial value is (0, 0) after power up.

Notes : When XIN is not present, don’t write data in any address. If data is written in any other address, a

TA B LE 5. PWMCK Frequenc y and PWMDA sampli ng rate

Output dis p lay if FSS=0; first and last lines omitt ed

(PWM1, PWM0) PWMCK Freq

( 0, 0 ) XIN frequency /8
( 0, 1 ) XIN frequency /4
( 1, 0 ) XIN frequency /2
( 1 ,1 ) XIN frequency /1

Column 19

Column 20

FSW - Enable full screen self-test pattern and

this bit is set to "1". The self-test pattern’s color is determined by (FSR, FSG, FSB) bits.

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B7 b6 b5 b4 b3 b2 b1 b0

- - - - - CSR CSG CSB

power up.

B7 b6 b5 b4 b3 b2 b1 b0

FSW - - - - FSR FSG FSB

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WW41, WW40 - Determines the shadow width of the window 4 when WSHD bit of th window 4 is e nabled.

Please refer to the Table 6 for more details.

WH41, WH40 - Determines the shadow height of the window 4 when WSHD bit of th window 4 is enabled.

Please refer to the Table 7 for more details.

by the registers of

WINDOW AREA

FSR, FSG, FSB - Define the color of full screen self-test pattern.

MTV130MYSON

Column 21

WW41 WW40 WW31 WW30 WW21 WW20 WW11 WW10

TABLE 6. Shadow Width Set t in g

(WW41, WW40) (0, 0) (0, 1) (1, 0) (1, 1)

B7 b6 b5 b4 b3 b2 b1 b0

Shadow Width

2 4 6 8

(unit in Pixel)

WW31, WW30 - Determines the shadow width of the window 3 when WSHD bit of th window 3 is e nabled.
WW21, WW20 - Determines the shadow width of the window 2 when WSHD bit of th window 2 is e nabled.
WW11, WW10 - Determines the shadow width of the window 1 when WSHD bit of th window 1 is enabled.

B7 b6 b5 b4 b3 b2 b1 b0

Column 22

WH41 WH40 WH31 WH30 WH21 WH20 WH11 WH10

TABLE 7. Shadow Heigh t Setting

(WH41, WH40) (0, 0) (0, 1) (1, 0) (1, 1)

Shadow Height

2 4 6 8

(unit in Line)

WH31, WH30 - Determines the shadow height of the window 3 when WSHD bit of th window 3 is enabled.
WH21, WH20 - Determines the shadow height of the window 2 when WSHD bit of th window 2 is enabled.
WH11, WH10 - Determines the shadow height of the window 1 when WSHD bit of th window 1 is enabled.

M Pixels

N Horizontal lines

Note:
M and N are defi n ed

row 15, column 21
and 22.

Bordering

Shad owi ng

N Horizontal lines

M Pixels

FIGURE 8. Character Borderi ng and Shadowin g and Shadowin g on Windo w

3.10 Color enco d er

Revision 1.0 12/18 28/April/2000

MTV130MYSON

The encoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border

3.11 PWM D/A conv er ter

are programmable by writing data to Column 23 to 26 registers of Row 15 with 8-bit resolution to control the

R1, G1, B1 - Define the shadow color of window 1. The initial value is (0, 0, 0) after power up.

R2, G2, B2 - Define the shadow color of window 2. The initial value is (0, 0, 0) after power up.

R3, G3, B3 - Define the shadow color of window 3. The initial value is (0, 0, 0) after power up.

R4, G4, B4 - Define the shadow color of window 4. The initial value is (0, 0, 0) after power up.

TECHNOLOGY

blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.

There are 4 open-drain PWM D/A outputs (PWM0 to PWM3). These PWM D/A converter outputs pulse width
pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (PWM1, PWM0) shown as

table 5. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage
(5V to 9V) for desired output range.

b7 b6 b5 b4 b3 b2 b1 b0

Column 23

|

Column 26

MSB LSB

PWMDA0 - PWMDA3 - Define the output pulse width of pin PWM0 to PWM3.

PWMDA0

|

PWMDA3

PWMCK

255
PWM0
PWM1
PWM2
PWM3

FIGURE 9. 5 Channel PWM Output Rising Edges A r e Separated by One PWMCK

Colum n 27 ~ colum n 31 : Reserved.

Notes : The regis t er loc ated at col um n 31 of row 15 ar e reserved for th e testin g . Don’t pr og r am th i s

byte anytime in normal operation.

ROW 16

Colum n 0

0 1

B7 b6 b5 b4 b3 b2 b1 b0

- R1 G1 B1 - R2 G2 B2

2 3 255

m m+1

0 1

2 3

4

Colum n 1

Revision 1.0 13/18 28/April/2000

B7 b6 b5 b4 b3 b2 b1 b0

- R3 G3 B3 - R4 G4 B4

TECHNOLOGY

D2-D0 - These 3 bits define the setup time of HFLB to XIN and the propagation delay R, G, B, FBKG and INT

Figure 12 and Table 8.

4.0 ABSOLUTE MA XIMUM RATINGS

DC Supply Voltage(VDD,VDDA)

Voltage with respect to Ground

Storage Temperature

Ambient Operating Temperature

5.0 OPERATING CONDITIONS

DC Supply Voltage(VDD,VDDA)

Operating T emperature

6.0 ELECTRICAL CHARACTERISTICS (Under Operat in g Condit io n s)

Input High Voltage

MTV130MYSON

Colum n 2

outputs. Please refer to

TA BL E 8. Out p ut and HFLB timi ng to Pixel Clock

Symbol (D2, D1, D0) Min. Typ. Max. Unit

t

SETUP

t

HOLD

t

pd

B7 b6 b5 b4 b3 b2 b1 b0

- - - - - D2 D1 D0

The initial value is (0, 0, 0) after power up.

0
1
2
3
4
5
6
7

- 500 - - ns

0
1
2
3
4
5
6
7

10
11
12
13
14
15
16
17

8

9
10
11
12
13
14
15

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

10

11
12
13
14
15
16
17

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns

Colum n 3 ~ c o l u mn 31 : Reserved.

-0.3 to +7 V

-0.3 to VDD+0.3 V

-65 to +150 oC
0 to +70 oC

+4.75 to +5.25 V

0 to +70 oC

Symbol Parameter Cond it io ns (Notes) Min. Max. Units

V

IH

(pin hflb, vflb, sda, sck, ssb)

- 0.7 * VDD VDD+0.3 V

Revision 1.0 14/18 28/April/2000

MTV130MYSON

7.0 SWITCHING CHA RACTERISTIC (Under Oper at in g Condi ti on s)

Input Low Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Open Drain Output High Volt-

up by external 5 to 9V power

Open Drain Output Low Volt-

Standby Current

START condition setup time

START condition hold time

STOP condition setup time

STOP condition hold time

minimum pulse width of HFLB

propagation delay of output to pixel clock

TECHNOLOGY

Symbol Parameter Cond it io ns (Notes) Min. Max. Units

- VSS-0.3 0.3 * VDD V

- VSS-0.3 0.2 * VDD V

I

≥ -5 mA

OH

IOL≤ 5 mA

VDD-0.8 - V

- 0.5 V

V

V

V

OH

OL

IL

(pin hflb, vflb, sda, sck)

(pin ssb)

-

V

ODH

age

(For all OD pins, and pulled

5 9 V

supply)

V

ODL

I

CC

I

SB

age

Operating Current

5 mA ≥ I

( For all OD pins )

Pixel rate=150MHz

I

Vin = VDD,

I

DOL

load = 0uA

load = 0uA

- 0.5 V

- 25 mA

- 12 mA

Symbol Parameter Min. Typ . Max. Units

f

HFLB

f

VFLB

T

r

T

f

t

BCSU

t

BCH

t

DCSU

t

DCH

t

SCKH

t

SCKL

t

SU:STA

t

HD:STA

t

SU:STO

t

HD:STO

t

SETUP

HFLB input frequency 15 - 150 KHz
VFLB input frequency - - 200 Hz
Output rise time - 3 - ns
Output fall time - 3 - ns
SSB to SCK set up time 200 - - ns
SSB to SCK hold time 100 - - ns
SDA to SCK set up time 200 - - ns
SDA to SCK hold time 100 - - ns
SCK high time 500 - - ns
SCK low time 500 - - ns

500 - - ns
500 - - ns
500 - - ns
500 - - ns

minimum HFLB delay to rising edge of pixel

TBD - TBD ns

clock

t

HOLD

t

pd

25 - - ns

TBD - TBD ns

PIXin pixel clock input 6 - 150 M Hz

Revision 1.0 15/18 28/April/2000

TECHNOLOGY

8.0 TIMING DIAGRAMS

FIGURE 11. Data in terf ac e ti ming(I

pd:: Propagation Delay to R,G,B, FBKG

t

SCKH

SCK

SSB

t

BCSU

SDA

FIGURE 10. Data in t er face ti m ing(SPI)

t

SCKH

SCK

t

SU:STA

SDA

t

HD:STA

t

t

SCKL

t

SCKL

DCSU

t

DCSU

MTV130MYSON

t

BCH

t

DCH

t

HD:STO

t

DCH

2

C)

t

SU:STO

PlXin

R,G,B, FBKG
HTONE

HFLB

t

and HTONE outputs

t

HOLD

t

SETUP

t

pd

FIGURE 12. Outp u t and HFLB Timin g to Pixel Clock

Revision 1.0 16/18 28/April/2000

TECHNOLOGY

9.0 PACKAGE DIMENSION

9.1 16 Pin PDIP 300mil

R40

312 +/-12

250 +/-4

55 +/-20

R10Max

(4X
)

90 +/-20

MTV130MYSON

350 +/-20

75 +/-20

90 +/-20

15 Max

115 Min

100Ty

p

9.2 20 Pin PDIP 300mil

75 +/-20

90 +/-20

15 Max

750 +/-10

18 +/-

2Typ

1020 +/-10

60 +/-

5Typ

7
Typ

35 +/-5

15 Min

7
Typ

R40

312 +/-12

250 +/-4

65 +/-4

310Max

55 +/-20

55 +/-4

65 +/-4

55 +/-4

310Max

10

R10Max

90 +/-20

(4X
)

350 +/-20

10

35 +/-5

115 Min

100Typ 18 +/-2Typ

60 +/-5Typ

15 Min

Revision 1.0 17/18 28/April/2000

TECHNOLOGY

Please see the attachment.

Myson Technology USA, Inc.

http://www.myson.com

FAX: [phone]

[e-mail]

Myson Technology, Inc.

http://www.myson.com.tw

No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, T aiwan, R. O. C.

Tel: [phone]

9.3 16 Pin SOP 300mil

0.406 +/-0.008

(4x)

0.406 +/-0.013

0.295 +/-0.004

0.015x45

o

MTV130MYSON

7o(4x)

0.091

0.016 +/-0.004 0.050

0.098 +/-0.006

9.4 20 Pin SOP 300 m il

20 11

0.406+/-0.012inch

0.295+/-0.004inch

1

0.016typ. 0.050typ.

10

10.0 CHARACTERS AND SYMBOLS PATTERN

0.028 +0.022 /-0.013

0.020x45

Fax: [phone]

Revision 1.0 18/18 28/April/2000

20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A.
Tel:[phone]