Datasheet MTV030N202, MTV030N24, MTV030N201, MTV030N Datasheet (MYSON)

ut notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

TECHNOLOGY

GENERAL DESCRIPTION

Full-screen display consists of 15 (rows) by 30 (columns)

Character bordering, shadowing and blinking effect.

5-channel/8-bit PWM D/A converter output.

and full-screen self-test pattern generator.

menu is formed by 15 rows x 30 columns, which can be

at the speed related to the OSD resolution. MCU can get

appropriate display size and center.

On-Screen Display with Auto-Sizing Controller

FEATURES

• Horizontal SYNC input up to 150 KHz.

• On-chip PLL circuitry up to 150 MHz.

• Minimum timing measurement among HFLB, VFLB, RIN,
GIN and BIN for auto sizing.

• Full screen self-test pattern generator.

• Programmable Hor. resolutions up to 1524 dots per line.

•

• Two font size 12x16 or 12x18 dot matrix per character.

• True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.

• Double character height and/or width control.

• Programmable positioning for display screen center.

•

• Programmable character height (18 to 71 lines) control.

• Row to row spacing control to avoid expansion distortion.

• 4 programmable windows with multi-level operation.

• Shadowing on windows with programmable shadow
width/height/color.

• Programmable adaptive approach to handle H, V sync
collision automatically by hardware.

• Software clears bit for full-screen erasing.

• Fade-in/fade-out or blending-in/blending-out effects.

•

• Compatible with SPI bus or I2C interface with slave
address 7AH/7BH (slave address is mask option).

• 16-pin, 20-pin or 24-pin PDIP package.

MTV030MYSON

MTV030 is designed for monitor applications to display
built-in characters or fonts onto monitor screens. The dis­play operation occurs by transferring data and control infor­mation from the micro-controller to RAM through a serial
data interface. It can execute full-screen display automati­cally , as well as specific functions such as character back­ground, bordering, shadowing, blinking, double height and
width, font by font color control, frame positioning, frame
size control by character height and row-to-row spacing,
horizontal display resolution, full-screen erasing, fade-in/
fade-out effect, windowing effect, shadowing on window

MTV030 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD

positioned anywhere on the monitor screen by changing
vertical or horizontal delay.

The auto sizing video measurement module measure
the timing relationship among HFLB, VFLB, and R, G, BIN

the measurement data, active video, front porth and back
porth, through I2C bus read/write operation to keep the

BL OCK DIAGRAM

SSB

SCK

SDA

VFLB

HFLB

VCO

PWM0
PWM1
PWM2
PWM3
PWM4

8

SERIAL DATA

INTERFACE

ARWDB

ADDRESS BUS

HDREN
VDREN

ADMINISTRATOR

NROW

VERTICAL

7

VSP

HSP

RP

CHS

VERTD

HORD

CH

8

8

DISPLAY

CONTROL

HORIZONTAL

DISPLAY CONTROL

PHASE LOCK LOOP

DATA

9

ROW, COL
ACK

5

RCADDR

9

DADDR

9

FONTADDR

5

WINADDR

5

PWMADDR

5

LPN
NROW
VDREN

ARWDB
HDREN

VCLKX

PWM D/A

CONVERTER

POWER ON RESET

PRB

8

DATA

8 LUMAR

DATA

DISPLAY & ROW

REGISTERS

8

CHARACTER ROM

5

LUMINANCE &

GENERATOR

8

WINDOWS &

CH

CONTROL

WRWGWB

ENCODER

8

AUTO SIZING

CONTROL

BORDGER

FRAME

FBKGC

BLANK

COLOUR

DATA

LPN

CWS

VCLKS

8

VERTD
8
7

LUMAR
LUMAG
LUMAB

VCLKX

DATA

CWS

CHS

DATA

HORD

BLINK

MEASUREMENT

LUMAG
LUMAB
BLINK

8

CRADDR

LUMA
BORDER

BSEN
SHADOW
OSDENB
HSP
VSP

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification witho

VDD

VSS

VDDA

VSSA

ROUT
GOUT
BOUT
FBKG
HTONE

RIN
GIN
BIN

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TECHNOLOGY

Analog ground .

Vol t age Control Oscil l ato r.

low pass filter.

Analog pow er supply.

Positive 5 V DC supply for internal

This pin is used to input the horizontal syn-

1.0 PIN CONNECTION

MTV030MYSON

VSSA

VCO

RP

VDDA

HFLB

SSB
SDA
SCK

VSSA

VCO

RP

VDDA

HFLB

SSB
SDA
SCK

RIN
GIN

20

VSS

19

ROUT

18

GOUT

17

BOUT

16

FBKG

15

INT
VFLB

14

MTV030N201-xx

MTV030N24-xx

VDD

13

PWM3

12

PWM2

11

24

VSS

23

ROUT

22

GOUT
BOUT

21

FBKG

20

INT

19

VFLB

18

VDD

17

PWM4

16

PWM3

15

PWM2

14

PWM1

13

VCO

RP

SSB
SDA
SCK

VCO

RP

SSB
SDA
SCK

RIN
GIN

BIN

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8
9
10

16

VSS

15

ROUT

14

GOUT

13

BOUT

12

FBKG

MTV030N-xx

11

INT
VFLB

10

VDD

9

20

VSS

19

ROUT

18

GOUT

17

BOUT

16

FBKG

15

INT
VFLB

14

MTV030N202-xx

VDD

13

NC

12

BIN

11

VSSA

VDDA

HFLB

PWM0
PWM1

VSSA

VDDA

HFLB

PWM0

2.0 PIN DESCRIPTIONS

Name I/O

N16 N201 N202 N24

VSSA - 1 1 1 1

VCO I/O 2 2 2 2

RP I/O 3 3 3 3 Bias Resistor. The bias resistor is used to regulate the appro-

VDDA - 4 4 4 4

HFLB I 5 5 5 5 Hori zontal inpu t.

Pin No.

Desc ripti ons

This ground pin is used to internal analog cir-

cuitry.

This pin is used to control the

internal oscillator frequency by DC voltage input from external

priate bias current for internal oscillator to resonate at specific
dot frequency.

analog circuitry. And a 0.1uF decoupling capacitor should be
connected across to VDDA and VSSA.

chronizing signal. It is a leading edge triggered and has an
internal pull-up resistor.

2/21 MTV030 Revision 1.0 10/15/1999

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Serial data in p ut.

internal display registers and control registers. It has an inter-

nal pull-up resistor.

The clock-input pin is used to synchronize

It is used for auto sizing measurement and

this signal is came from video pre-amp red output.

Green video inpu t .

this signal is came from video pre-amp green output.

It is used for auto sizing measurement and

this signal is came from video pre-amp blue output.

Open-Drain PWM D/A con v ert er 0.

Open-Drain PWM D/A con v ert er 1.

Open-Drain PWM D/A con v ert er 2.

Open-Drain PWM D/A con v ert er 3.

Open-Drain PWM D/A con v ert er 4.

Positive 5 V DC supply for internal digi-

Vert ic al inpu t .

This pin is used to input the vertical synchroniz-

16-color selection is achievable by

It is used to cut off external R, G, B sig-

MTV030MYSON

Name I/O

N16 N201 N202 N24

SSB I 6 6 6 6 Serial interf ace enable. It is used to enable the serial data

SDA I 7 7 7 7

SCK I 8 8 8 8 Serial clock inpu t.

RIN I - - 9 9 Red video input .

GIN I - - 10 10

BIN I - - 11 11 Blue video input.

NC - - - 12 - No connection.

PWM0 O - 9 - 12

PWM1 O - 10 - 13

PWM2 O - 11 - 14

PWM3 O - 12 - 15

PWM4 O - - - 16

VDD - 9 13 13 17 Digital power supp ly.

VFLB I 10 14 14 18

INT O 11 15 15 19 Intensity color output .

FBKG O 12 16 16 20 Fast Blanking outpu t.

BOUT O 13 17 17 21 Bl ue color output . It is a blue color video signal output.

GOUT O 14 18 18 22 Green color outp ut. It is a green color video signal output.

ROUT O 15 19 19 23 Red colo r outp ut . It is a red color video signal output.

VSS - 16 20 20 24 Digital ground. This ground pin is used to internal digital cir-

Pin No.

Desc ripti ons

and is also used to select the operation of I2C or SPI bus. If
this pin is left floating, I2C bus is enabled, otherwise the SPI
bus is enabled.

The external data transfer through this pin to

the data transfer. It has an internal pull-up resistor.

It is used for auto sizing measurement and

The output pulse width is

programmable by the register of Row 15, Column 23.

The output pulse width is

programmable by the register of Row 15, Column 24.

The output pulse width is

programmable by the register of Row 15, Column 25.

The output pulse width is

programmable by the register of Row 15, Column 26.

The output pulse width is

programmable by the register of Row 15, Column 27.

tal circuitry and a 0.1uF decoupling capacitor should be con­nected across to VDD and VSS.

ing signal. It is leading triggered and has an internal pull-up
resistor.

combining this intensity pin with R/G/B output pins.

nals of VGA while this chip is displaying characters or win­dows.

cuitry.

3/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission

should be starting from pulling SSB to "low" level, enabling MTV030 to receiving mode, and retain "low" level

until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

Format (a) R - C - D

Format (b) R - C - D

Format (c) R - C - D

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting

Figure 2. And the auto sizing video measurement data (total 10 bytes) are read only registers and the others

are write only registers.

There are three transmission formats for I

C write mode shown as below:

Format (a) S - R - C - D

Format (b) S - R - C - D

Format (c) S - R - C - D

And there is one transmission format for I

FIGURE 2. Dat a Trans m i ssion Pro t o c ol (I

TECHNOLOGY

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.

3.1.1 SPI bus

SSB

SCK

SDA

MSB LSB

first byte last byte

FIGURE 1. Data Tran s m issio n Prot ocol (SPI)

There are three transmission formats shown as below:

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where R=Row address, C=Column address, D=Display data

3.1.2 I2C bus

2

I
from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV030. The protocol is shown in

SCK

SDA

START ACK

B7 B6 B0 B7 B0

first byte

second byte last byte

2

C)

ACK STOP

2

→ R - C - D → R - C - D .....

→ C - D → C - D → C - D .....

→ D → D → D → D → D .....

Where S=Slave address, R=Row address, C=Column address, D=Display data

2

C read mode shown as below:

Format (a) S → D → D → D → D → D → D → D → D → D → D → dummy D → dummy D .....

Where S=Slave address, D=Measurement data

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C read mode, 10 bytes of auto sizing video measurement data will be output directly from byte 0 to

C R/W bit is set to “1”.

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and

increase transmission efficiency. The row and column address will be incremented automatically when the for-

mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy

There are 2 types of data should be accessed through the serial data interface, one is

ADDRESS

bytes of dis-

play registers, and other is

of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column

addresses when transferring data from external controller. The bit6 of column address is used to differentiate

the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is

addres s byt es, bit 5 of col u m n addr ess is th e MSB (bit8) and data bytes are the 8 LSB (bit7~bi t 0) of dis-

play fonts address

played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of

column address of address bytes again.

(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is

configured as the state diagram shown in Figure 3.

3.2 Address bus adminis tr ator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external

data write in. The external data write through serial data interface to registers must be synchronized by inter-

nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-

nal write using format (c).

3.3 Verti cal di sp l ay cont r ol

The vertical display control can generates different vertical display sizes for most display standards in current

The configuration of transmission formats.

Addr ess Bytes

Attr ibut e Bytes

MTV030MYSON

In the I
byte 9 and continues with dummy data until stop condition occurred when I

Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to

data.

2

TABLE 1.

of Displ ay Reg.

of Displ ay Reg.

2

Address b7 b6 b5 b4 b3 b2 b1 b0 Format

Row 1 0 0 R4 R3 R2 R1 R0 a,b,c

Column

Column

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row 1 0 1 R4 R3 R2 R1 R0 a,b,c

Column

Column

Data D7 D6 D5 D4 D3 D2 D1 D0 a,b,c

0 0 D8 C4 C3 C2 C1 C0 a,b

ab

0 1 D8 C4 C3 C2 C1 C0 c

c

0 0 x C4 C3 C 2 C1 C0 a,b

ab

0 1 x C4 C3 C 2 C1 C0 c

c

ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5

used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at

to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis­address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format

monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-

5/21 MTV030 Revision 1.0 10/15/1999

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cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as

The vertical display center for full screen display could be figured out according to the information of vertical

character would not be repeated.

Repeat Li n e Weigh t

FIGURE 3. Trans m issio n State Diagram

0, X

Initiate

MTV030MYSON

Input = b7, b6

X, X

DA

format (c)

COL

X, X

c

1, X

1, X

ROW

0, 1

c

0, 1

0, 0

format (b)

COL

format (a)

0, 0

ab

X, X

DA

1, X

ab

Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = one horizontal line display time

TA B L E 2. Repeat lin e weig h t of ch aract er

CH6 - CH0

CH6,CH5=11 +18*3
CH6,CH5=10 +18*2
CH6,CH5=0x +18

CH4=1 +16
CH3=1 +8
CH2=1 +4
CH1=1 +2
CH0=1 +1

TA B L E 3. Repeat line nu m ber of ch arac ter

Repeat Line

Weight

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Repeat Lin e #

+1 - - - - - - - - v - - - - - - - - ­+2 - - - - v - - - - - - - v - - - - ­+4 - - v - - - v - - - v - - - v - - -

+8 - v - v - v - v - v - v - v - v - ­+16 - v v v v v v v v v v v v v v v v ­+17 v v v v v v v v v v v v v v v v v ­+18 v v v v v v v v v v v v v v v v v v

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

6/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.4 Hori zontal dis pl ay contr o l

The horizontal display control is used to generate control timing for horizontal display based on double char-

HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-

acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-

Where P = One pixel display time = One horizontal line display time / (HORR*12)

The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input

is not present to MTV030, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in

3.6 Disp l ay & Row contr ol regist ers

are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-

play register has its corresponding character address on ADDRESS byte, its corresponding background color,

30

of DISPLAY REGISTERS

A TTRIBUTE

CRTL REG

TECHNOLOGY

acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and

lated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width

3.5 Phase loc k l o o p (PLL)

On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg­ister (HORR). The frequency of VCLK is determined by the following equation:

VCLK Freq = HFLB Freq * HORR * 12

oscillator to ensure data integrity.

The internal RAM contains display and row control registers. The display registers have 450 locations which

1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at col­umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.

ROW # COLUMN #

0 1 28 29

0
1

ROW

CHARACTER ADDRESS BYTES

13
14

31

R
E
S
E
R
V
E
D

FIGURE 4. Ad d r ess By t es of Disp l ay Regist ers Memory Map

7/21 MTV030 Revision 1.0 10/15/1999

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CRADDR - Define ROM character address from address 0 to 511.

Row Control Registers, (Row 0 - 14)

CHS - Define double height character to the respective row.

ATTRIBUTE BYTES:

BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames.

R, G, B - These three bits are used to specify its relative address character color.

CHARACTER ATTRIBUTE BYTES

of DISPLAY REGISTERS

WINDOW1 ~ WINDOW4

PWM D/A

RESERVED

WINDOW SHADOW COLOR

ROW # COLUMN #

0 1 28 29 30 31

0
1

13
14

COLUMN#

ROW 15

0 11 12 22 23 27 28 31

FRAME

CRTL REG

MTV030MYSON

RESERVED

CRTL REG

COLUMN#

ROW 16

ADDRESS BYTES:
Address registers,

b8 b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

COLN 30

CWS - Define double width character to the respective row.

b7 b6 b5 b4 b3 b2 b1 b0

- BGR BGG BGB BLINK R G B

0 1 2 31

RESERVED

FIGURE 5. Attri b ut e Byt es of Disp l ay Registers Memory Map

CRADDR

b7 b6 b5 b4 b3 b2 b1 b0

- - - - - - CHS CWS

BGR, BGG, BGB - These three bits define the color of the background for its relative address character. If all

three bits are clear, no background will be shown(transparent). Therefore, total 7 back­ground color can be selected.

8/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

multi-color fonts. The 496 standard fonts are located from address 0 to 495. And the 16 multi-color fonts are

located from address 496 to 511. Each character and symbol consists of 12x18 dots matrix. The detail pattern

CHARACTERS AND SYMBOLS PATTERN

The color fonts comprises three different R, G, B fonts. When the code of color font is accessed, the separate

R/G/B dot pattern is output to corresponding R/G/B output. See Figure 6 for the sample displayed color font.

TERS AND SYMBOLS PATTERN

encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character

Background Color

FIGURE 6. Example of Mul t i -Colo r Fon t

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3.7 Charac ter ROM

MTV030 character ROM contains 512 built-in characters and symbols including 496 standard fonts and 16

structures for each character and symbols are shown in “
page21.

” on

3.8 Multi -Colo r Font

Note: No black color can defined in color font, black window underline the color font can make the dots
become black in color. The detail pattern structures for each character and symbols are shown in “CHARAC-

” on page 21.

B

G

R

Magent
Green
Blue
Cyan

TABLE 4. The Multi -Color Font Color Selection

R G B

0 0 0

Blue 0 0 1

Green 0 1 0

Cyan 0 1 1

Red 1 0 0

Magent 1 0 1

Yellow 1 1 0

White 1 1 1

3.9 L u mi n ance & bor der generator

There are 3 shift registers included in the design which can shift out of luminance and border dots to color
will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with

blackedge for right and bottom sides only.

9/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.10 Windo w and frame cont ro l

The display frame position is completely controlled by the contents of VERTD and HORD. The window size

. Window

1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed infor-

mation is described as follows:

Window control registers,

START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the

WSHD - Enable shadowing on the window.

Frame control registers,

step is 4 Horizontal display lines. The initial value is 4 after power up.

CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character

ROW START ADDR

ROW END ADDR

COL START ADDR

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and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure5

1.
ROW 15

Column

0,3,6,OR 9

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

MSB LSB

Column

1,4,7,OR 10

Column

2,5,8,OR 11

WEN - Enable the relative background window display.

R, G, B - Specify the color of the relative background window.

2.
ROW 15

Column 12

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

COL END ADDR

MSB LSB

start address is greater than the end address, the window will be disabled.

b7 b6 b5 b4 b3 b2 b1 b0

VERTD

MSB LSB

WEN - WSHD

R G B

VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each

b7 b6 b5 b4 b3 b2 b1 b0

Column 13

MSB LSB

HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each

step is 6 dots. The initial value is 15 after power up.

Column 14

b7 b6 b5 b4 b3 b2 b1 b0

- CH6 CH5 CH4 CH3 CH2 CH1 CH0

vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when
the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the con-

HORD

10/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

tents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2

HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is,

be appended below each display row, and the maximum space is 31 lines. The initial value is 0

BSEN - Enable the bordering and shadowing effect.

FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state

function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly

RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set

FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the

TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,

while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are

in high impedance state. The initial value is 0 after power up.

TECHNOLOGY

and Table 3 for detail description of this operation.

b7 b6 b5 b4 b3 b2 b1 b0

Column 15

the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater
than or equal to 36 and smaller than 150M / (Hfreq*12). The initial value is 40 after power up.

Column 16

RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will

- HORR
MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

- - - RSPACE

MSB LSB

after power up.

Column 17

OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.

SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise

or vice verca.

BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blending-in/blending-out

takes about 0.5 second to fully display the whole menu or to disappear completely.

WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after

to "1". The initial value is 0 after power up.

b7 b6 b5 b4 b3 b2 b1 b0

OSDEN BSEN SHADOW FBEN BLEND WENCLR RAMCLR FBKGC

the bordering is chosen.

power up.

displaying of characters or windows, otherwise, it outputs high only during the displaying of charac­ter.

Column 18

B7 b6 b5 b4 b3 b2 b1 b0

TRIC FSS VMEN SELVCL HSP VSP VCO1 VCO0

11/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

FSS - Font size selection.

VMEN - Auto sizing video measurement enable bit. All video measurements commence at the following VFLB

SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition to avoid unstable

Accept positive polarity Hsync input.

Accept negative polarity Hsync input.

Accept positive polarity Vsync input.

Accept negative polarity Vsync input.

horizontal resolution register (HORR).

6 MHz < Pixel rate

28 MHz < Pixel rate

56 MHz < Pixel rate

112 MHz < Pixel rate

112000/(HORR * 12)

It is necessary to wait for the PLL to become stable while (i) the HORR register is changed; (ii) the (VCO1, VCO0)

When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written in any

= 1 ⇒ 12x18 font size selected.
= 0 ⇒ 12x16 font size selected.

MTV030MYSON

Fonts desig n ed to be 12x18 displ ay

FIGURE 7. 12x18 and 12x16 Fonts

pulse after the VMEN bit is set, complete the measurement after one vertical frame.

Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after
power up.

HSP - = 1 ⇒

= 0 ⇒

VSP - = 1 ⇒

= 0 ⇒

VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and

= (0, 0) ⇒

= (0, 1) ⇒
= (1, 0) ⇒
= (1, 1) ⇒

where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12
The initial value is (0, 0) after power up.

Output dis p lay if FSS=0; first and last lines omitt ed

< 28 MHz
< 56 MHz
< 112 MHz

< 150 MHz

Notes :

1. That is, if HORR is specified, then (VCO1, VCO0)
= (0, 0) if 6000/(HORR * 12) < HFLB Freq (KHz) < 28000/(HORR * 12)
= (0, 1) if 28000/(HORR * 12) < HFLB Freq (KHZ) < 56000/(HORR * 12)
= (1, 0) if 56000/(HORR * 12) < HFLB Freq (KHZ) <
= (1, 1) if 112000/(HORR * 12) < HFLB Freq (KHZ) < 150000/(HORR * 12)

2.

bits is changed; (iii) the horizontal signal (HFLB) is changed.

3.

other address, a malfunction may occur.

12/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

CSR, CSG, CSB - Define the color of bordering or shadowing on characters. The initial value is (0, 0, 0) after

force the FBKG pin output to high to disable video RGB while

WW41, WW40 - Determines the shadow width of the window 4 when WSHD bit of th window 4 is e nabled.

Please refer to the Table 6 for more details.

WH41, WH40 - Determines the shadow height of the window 4 when WSHD bit of th window 4 is enabled.

Please refer to the Table 7 for more details.

PWMCK Freq (14M ~ 28MHz)

PWMDA sam pling rate (54K ~ 109KHz)

TA B LE 5. PWMCK Frequenc y and PWMDA sampli ng rate

(VCO1, VCO0)

( 0, 0 ) HFLB Freq * HORR * 12 HFLB Freq * HORR * 12 / 256
( 0, 1 ) HFLB Freq * HORR * 6 HFLB Freq * HORR * 6 / 256
( 1, 0 ) HFLB Freq * HORR * 3 HFLB Freq * HORR * 3 / 256
( 1 ,1 ) HFLB Freq * HORR * 3 / 2 HFLB Freq * HORR * 3 / 512

MTV030MYSON

Column 19

Column 20

FSW - Enable full screen self-test pattern and

this bit is set to "1". The self-test pattern’s color is determined by (FSR, FSG, FSB) bits.

FSR, FSG, FSB - Define the color of full screen self-test pattern.

Column 21

TABLE 6. Shadow Width Set t in g

(WW41, WW40) (0, 0) (0, 1) (1, 0) (1, 1)

Shadow Width

(unit in Pixel)

B7 b6 b5 b4 b3 b2 b1 b0

- - - - - CSR CSG CSB

power up.

B7 b6 b5 b4 b3 b2 b1 b0

FSW - - - - FSR FSG FSB

B7 b6 b5 b4 b3 b2 b1 b0

WW41 WW40 WW31 WW30 WW21 WW20 WW11 WW10

2 4 6 8

WW31, WW30 - Determines the shadow width of the window 3 when WSHD bit of th window 3 is e nabled.
WW21, WW20 - Determines the shadow width of the window 2 when WSHD bit of th window 2 is e nabled.
WW11, WW10 - Determines the shadow width of the window 1 when WSHD bit of th window 1 is enabled.

Column 22

B7 b6 b5 b4 b3 b2 b1 b0

WH41 WH40 WH31 WH30 WH21 WH20 WH11 WH10

13/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.11 Colo r enco d er

The encoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border

3.12 PWM D/A co nv er t er

are programmable by writing data to Column 23 to 27 registers of Row 15 with 8-bit resolution to control the

by the registers of

WINDOW AREA

TECHNOLOGY

TABLE 7. Shadow Heigh t Setting

(WH41, WH40) (0, 0) (0, 1) (1, 0) (1, 1)

Shadow Height

(unit in Line)

WH31, WH30 - Determines the shadow height of the window 3 when WSHD bit of th window 3 is enabled.
WH21, WH20 - Determines the shadow height of the window 2 when WSHD bit of th window 2 is enabled.
WH11, WH10 - Determines the shadow height of the window 1 when WSHD bit of th window 1 is enabled.

Bordering

2 4 6 8

N Horizontal lines

Shad owi ng

M Pixels

M Pixels

N Horizontal lines

Note:
M and N are defi n ed

row 15, column 21
and 22.

FIGURE 8. Character Borderi ng and Shadowin g and Shadowin g on Windo w

blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.

There are 5 open-drain PWM D/A outputs (PWM0 to PWM4). These PWM D/A converter outputs pulse width
pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (VCO1, VCO0) shown as

table 5. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage
(5V to 9V) for desired output range.

b7 b6 b5 b4 b3 b2 b1 b0

Column 23

|

Column 27

PWMDA0

|

PWMDA4

MSB LSB

PWMDA0 - PWMDA4 - Define the output pulse width of pin PWM0 to PWM4.

14/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

3.13 Au t o si zing vid eo measurement

The auto sizing video measurement module monitors horizontal and vertical flyback pulses and their relation-

ship to video content. In horizontal measurement, the HFLB is the reference signal. As PLL clock is the certain

multiple of HFLB frequency, the measurements for HFLB and R,G,BIN are all based on the PLL clock. In ver-

have an exact timing relationship to the active raster display on the monitor. When the HFLB, VFLB sync sig-

MCU a lot of information about the display size and centering. If back porch is much smaller than front porth,

then the video information is too much to the left (or up in the vertical direction). If both front porth and back

the display size and center until front and back porthes are equal and the porthes to active video ratio is cor-

for different operating frequencies is needed. And it is recommend that video contrast is set to maximum first

for the correct capture of video information.

TECHNOLOGY

PWMCK

255
PWM0
PWM1
PWM2
PWM3
PWM4

FIGURE 9. 5 Channel PWM Out p ut Ris ing Edges A r e Separated by One PWMCK

Colum n 28 ~ colum n 31 : Reserved.

Notes : The regis t er loc ated at col um n 31 of row 15 ar e reserved for th e testin g . Don’t prog r am th i s

byte anytime in normal operation.

ROW 16

Colum n 0

0 1

B7 b6 b5 b4 b3 b2 b1 b0

- R1 G1 B1 - R2 G2 B2

2 3 255

m m+1

0 1

2 3

4

R1, G1, B1 - Define the shadow color of window 1. The initial value is (0, 0, 0) after power up.
R2, G2, B2 - Define the shadow color of window 2. The initial value is (0, 0, 0) after power up.

Colum n 1

R3, G3, B3 - Define the shadow color of window 3. The initial value is (0, 0, 0) after power up.
R4, G4, B4 - Define the shadow color of window 4. The initial value is (0, 0, 0) after power up.
Colum n 2 ~ c o l u mn 31 : Reserved.

tical measurement, the VFLB pulse is reference signal and the HFLB is the counting clock. HFLB and VFLB
nals and the R,G,BIN video signals (taken from the output of pre-amplifier) are compared, it will feedback to

B7 b6 b5 b4 b3 b2 b1 b0

- R3 G3 B3 - R4 G4 B4

porth percentage of the total display period is too large, then the display size is too small. MCU can change
rect. Please note that due to the deviation of analog circuits, building a ratio table of correct porches to video

15/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

All these measurements commence at the following VFLB pulse after enabling VMEN bit, complete the meas-

urement after one vertical frame, so minimum delay 2 vertical frame time after enabling VMEN bit is needed to

read out the measurement data. The horizontal measurement for R,G,BIN will store the minimum start loca-

tion and the maximum ending location in one vertical frame into registers. All of the input signals for timing

measurement are polarity programmable, so the different phase measurement can be obtained.

b1 ~ b0 : The most significant 2 bits of

b7 ~ b0 : The least significant 8 bits of

b1 ~ b0 : The most significant 2 bits of

b7 ~ b0 : The least significant 8 bits of

b2 ~ b0 : The most significant 3 bits of

which represents the H line distance between the first active

b7 ~ b0 : The least significant 8 bits of

which represents the H line distance between the first active

Auto sizing video measurement data bytes : read only registers

B7 b6 b5 b4 b3 b2 b1 b0

By t e 0

of R,G,BIN input and reference HFLB leading edge. See Figure 10.

By t e 1

of R,G,BIN input and reference HFLB leading edge. See Figure10.

- - - - - - Dhrgbsta
MSB

Dhrgbsta which represents the distance between the first active edge

B7 b6 b5 b4 b3 b2 b1 b0

Dhrgbsta

Dhrgbsta which represents the distance between the first active edge

MTV030MYSON

LSB

B7 b6 b5 b4 b3 b2 b1 b0

By t e 2

of R,G,BIN input and reference HFLB leading edge. See Figure 10.

By t e 3

of R,G,BIN input and reference HFLB leading edge. See Figure 10.

By t e 4

line of R,G,BIN input and reference VFLB leading edge. See Figure10.

By t e 5

- - - - - - Dhrgbend

Dhrgbend which represents the distance between the last active edge

B7 b6 b5 b4 b3 b2 b1 b0

Dhrgbend

Dhrgbend which represents the distance between the last active edge

B7 b6 b5 b4 b3 b2 b1 b0

- - - - - Dvrgbsta

MSB

Dvrgbsta

B7 b6 b5 b4 b3 b2 b1 b0

Dvrgbsta

MSB

LSB

LSB

Dvrgbsta

line of R,G,BIN input and reference VFLB leading edge. See Figure10.

16/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

b2 ~ b0 : The most significant 3 bits of

which represents the H line distance between the last active

b7 ~ b0 : The least significant 8 bits of

which represents the H line distance between the last active

b2 ~ b0 : The most significant 3 bits of

b7 ~ b0 : The least significant 8 bits of

B7 b6 b5 b4 b3 b2 b1 b0

By t e 6

line of R,G,BIN input and reference VFLB leading edge. See Figure 10.

By t e 7

line of R,G,BIN input and reference VFLB leading edge. See Figure10.

By t e 8

- - - - - Dvrgbend

MSB

Dvrgbend

B7 b6 b5 b4 b3 b2 b1 b0

Dvrgbend

Dvrgbend

B7 b6 b5 b4 b3 b2 b1 b0

- - - - OVER Dvsline

MSB

MTV030MYSON

LSB

OVER - = 1 ⇒ The line number counter is overflow.

= 0 ⇒ Not overflow.

Dvsline which represents the total H line count between two consecu-

tive VFLB pulses. See Figure10.

B7 b6 b5 b4 b3 b2 b1 b0

By t e 9

Dvsline which represents the total H line count between two consecu-

tive VFLB pulses. See Figure10.

Dvsline

LSB

17/21 MTV030 Revision 1.0 10/15/1999

4.0 ABSOLUTE MA XIMUM RATINGS

DC Supply Voltage(VDD,VDDA)

Voltage with respect to Ground

Storage Temperature

Ambient Operating Temperature

5.0 OPERATING CONDITIONS

DC Supply Voltage(VDD,VDDA)

Operating T emperature

6.0 ELECTRICAL CHARACTERISTICS (Under Operat in g Condit io n s)

Input High Voltage

Input High Voltage

HFLB

FIGURE 10. Timi n g Diagram of Auto Sizing Video Measurement

R,G,BIN

MTV030MYSON

TECHNOLOGY

HORRx12

VFLB

R,G,BIN

Dhrgbsta

Dhrgbend

Dvsline

Dvrgbsta

Dvrgbend

-0.3 to +7 V

-0.3 to VDD+0.3 V

-65 to +150 oC
0 to +70 oC

+4.75 to +5.25 V

0 to +70 oC

Symbol Parameter Condi ti on s (Notes) Min. Max. Units

V

IH

(pin hflb, vflb, sda, sck, ssb)

(pin rin, gin, bin)

- 0.7 * VDD VDD+0.3 V

- 0.7 * VDD VDD+0.3 V

18/21 MTV030 Revision 1.0 10/15/1999

MTV030MYSON

7.0 SWITCHING CHA RACTERISTIC (Under Oper at in g Condi ti on s)

Input Low Voltage

Input Low Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Open Drain Output High Volt-

up by external 5 to 9V power

Open Drain Output Low Volt-

Standby Current

START condition setup time

START condition hold time

STOP condition setup time

STOP condition hold time

TECHNOLOGY

Symbol Parameter Condi ti on s (Notes) Min. Max. Units

V

V

V

V

ODH

V

ODL

I

CC

I

SB

IL

OH

OL

(pin hflb, vflb, sda, sck)

(pin ssb)

(pin rin, gin, bin)

age

age

Operating Current

- VSS-0.3 0.3 * VDD V

- VSS-0.3 0.2 * VDD V

- VSS-0.3 0.6 * VDD V

I

≥ -5 mA

OH

IOL≤ 5 mA

-

(For all OD pins, and pulled

supply)

5 mA ≥ I

DOL

( For all OD pins )

Pixel rate=150MHz

I

load = 0uA

Vin = VDD,

I

load = 0uA

VDD-0.8 - V

- 0.5 V

5 9 V

- 0.5 V

- 25 mA

- 12 mA

Symbol Parameter Min. Typ. Max. Units

f

HFLB

f

VFLB

T

r

T

f

t

BCSU

t

BCH

t

DCSU

t

DCH

t

SCKH

t

SCKL

t

SU:STA

t

HD:STA

t

SU:STO

t

HD:STO

HFLB input frequency 15 - 150 KHz
VFLB input frequency - - 200 Hz
Output rise time - 3 - ns
Output fall time - 3 - ns
SSB to SCK set up time 200 - - ns
SSB to SCK hold time 100 - - ns
SDA to SCK set up time 200 - - ns
SDA to SCK hold time 100 - - ns
SCK high time 500 - - ns
SCK low time 500 - - ns

500 - - ns
500 - - ns
500 - - ns
500 - - ns

19/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

8.0 TIMING DIAGRAMS

9.0 PACKAGE DIMENSION

FIGURE 11. Data interfac e tim i ng (SPI)

t

SCKH

SCK

SSB

t

BCSU

SDA

t

SCKH

SCK

t

FIGURE 12. Data interface ti m i ng(I2C)

SDA

t

SU:STA

t

HD:STA

t

t

DCSU

SCKL

SCKL

t

DCSU

MTV030MYSON

t

BCH

t

DCH

t

HD:STO

t

DCH

t

SU:STO

9.1 16 Pin 300mil

75 +/-20

90 +/-20

115 Min

100Ty

R10Max

(4X

55 +/-4

)

90 +/-20

350 +/-20

10

312 +/-12

R40

15 Max

p

750 +/-10

18 +/-

2Typ

60 +/-

5Typ

7
Typ

35 +/-5

15 Min

55 +/-20

250 +/-4

65 +/-4

310Max

20/21 MTV030 Revision 1.0 10/15/1999

TECHNOLOGY

Please see the attachment.

Myson Technology USA, Inc.

http://www.myson.com

FAX: [phone]

[e-mail]

Myson Technology, Inc.

http://www.myson.com.tw

No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, T aiwan, R. O. C.

Tel: [phone]

9.2 20 Pin 300mil

R40

312 +/-12

250 +/-4

55 +/-20

MTV030MYSON

R10Max

(4X
)

90 +/-20

350 +/-20

75 +/-20

90 +/-20

15 Max

115 Min

100Typ 18 +/-2Typ

9.3 24 Pin 300mil

1020 +/-10

60 +/-5Typ

7
Typ

35 +/-5

15 Min

R40

312+/-12

R10Max
(4X)

55+/-20

65 +/-4

310Max

55 +/-4

80+/-20

10

350+/-20

250+/-4

930+/-10

115Min

15Max

100Ty

p

1245+/-10

18+/­2Typ

60+/­5Typ

7Ty

p

15Min.

10.0 CHARACTERS AND SYMBOLS PATTERN

Fax: [phone]

21/21 MTV030 Revision 1.0 10/15/1999

65+/-4

35+/-5

10

65+/-4

20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A.
Tel:[phone]