Datasheet MTU423 Datasheet (MYSON)

MYSON
TECHNOLOGY

MTU423

Universal Remote Controller

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No right s under any patent accompany the sale of the product.

MTU423 Revision 2.5 02/25/1997



FEATURES

• 4-bit microcomputer-based.

• Low current dissipation in STOP mode:

- 1.0uA (typical) 3.58MHz (@ 3.0V)

• Powerful instruction set (73 instructions):

- Binary addition, subtraction adjustment, logical operation in direct addressing mode and index addressing
mode.

- Single-bit manipulation instruction (set, reset, decision for branch).

- 4-bit input/output instruction.

- Various conditional branch instructions.

- 8 working registers and manipulation instructions.

- Index ROM data transfer instruction.

• ROM/RAM /Index ROM capacity:

- ROM capacity 2048 x 16 bits.

- RAM capacity 64 x 4 bits.

- Index ROM capacity 40960 x 4 bits.

• Input/Output ports:

- Input ports 2 ports/ 8pins (input port M/S).

- I/O ports 2 ports/ 8pins (input/output port I/OA, I/OB).

• 2 control outputs: carrier, light.

• Built-in carrier duty cycle divider.

• One 6-bit programmable timer.

• 4 levels of stack for nest subroutine.

• Operating voltage: 2.4V ~ 3.6V.

GENERAL DESCRIPTION

MTU423 is a high-frequency, high-performance, 4-bit microcomputer-based universal remote controller. It
contains a 4-bit ALU, ROM, RAM, input/output ports, timer, clock generator, index ROM and carrier control in a
single chip. The high frequency (3.58Hz) provides a wide range of infrared carrier output. The 40Kx4 index
ROM stores information of various remote controllers. The instruction set includes basic 4-bit instructions and
special instructions such as index ROM moving, auto-incrementation and carrier control instruction.

The STOP instruction can stop all internal operations such as the oscillator and divider, hence minimum power
dissipation can be achieved.

With an external 0.1µF capacitor, SRAM data can be saved for 3 minutes, which is long enough for a battery
change.

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BLOCK DIAGRAM

I/O PORT

OUTPUT

PORT

INDEX ROM

40K x 4

INPUT

PORT

4-BIT DATA BUS

OSCILLATOR

PREDIVIDER

DUTY CYCLE

DIVIDER

6-BIT

PRESET TIMER

CONTROL

CIRCUIT

ALU RAM 64 x 4

4-LEVEL STACK

11-BIT PROGRAM

COUNTER

PROM

2048 x 16

OSC IN

OSC
OUT

A1~4 B1~4 M1~4 S1~4

CARRIER

LIGHT

RESET

MTU423

M1

RESET

VDD

OSCOUT

OSCIN

VCC

IOB4

IOB3

IOB2

IOB1

IOA4

IOA3

S4

LIGHT

CARRIER

GND

IOA1

IOA2

S3

S2

S1

M4

M3

M2

PIN NUMBER PIN NAME %(um) y(um)

1 RESET 2848.8 1989.6
2 M1 2848.8 2380
3 M2 2503.7 2678.2
4 M3 2058.5 2678.2
5 M4 1668.1 2678.2
6 S1 1277.7 2678.2
7 S2 887.3 2678.2
8 S3 496.9 2678.2
9 S4 130.2 2335.2

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10 LIGHT 130.2 1954.4
11 CARRIER 130.2 1501.6
12 GND 130.2 1203.2
13 IOA1 130.2 905
14 IOA2 130.2 462
15 IOA3 452.6 130.2
16 IOA4 895.6 130.2
17 IOB1 1330.2 130.2
18 IOB2 1751.4 130.2
19 IOB3 2067.8 130.2
20 IOB4 2489 130.2
21 VCC 2848.8 333.4
22 OSCIN 2848.8 604
23 OSCOUT 2848.8 1341.2
24 VDD 2848.8 1579.2

1.0 PIN ASSIGNMENT

(use 300mil DIP)

Pin No. Pin Name Type Description

1 RESET I System reset pin (with internal pull-low).
2 M 1 I Input port (with internal pull-low).
3 M 2 I Input port (with internal pull-low).
4 M 3 I Input port (with internal pull-low).
5 M 4 I Input port (with internal pull-low).
6 S 1 I Output port (with internal pull-low).
7 S 2 I Output port (with internal pull-low).
8 S 3 I Output port (with internal pull-low).

9 S 4 I Output port (with internal pull-low).
10 LIGHT O Output port only for LED drive use.
11 CARRIER O Output port only for CARRIER OUT signal.
12 VSS Negative power supply pin.

13 IOA 1 I/O Input/Output port ( special use for low battery detection ).

14 IOA 2 I/O Input/Output port.
15 IOA 3 I/O Input/Output port.
16 IOA 4 I/O Input/Output port.
17 IOB 1 I/O Input/Output port.
18 IOB 2 I/O Input/Output port.
19 IOB 3 I/O Input/Output port.
20 IOB 4 I/O Input/Output port.
21 VCC Positive power supply pin for SRAM.

22
23

OSCIN

OSCOUT

IOTypically, a 3.58MHz crystal is connected across OSCIN/OSCOUT for

oscillation. R/C oscillation mode also available.

24 VDD Positive power supply pin.

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2.0 ABSOLUTE MAXIMUM RATINGS

at Ta = 0 to 70oC, VSS = 0V

Name Symbol Range Unit

Maximum Supply Voltage VDD -0.3 to +3.6 V
Maximum Input Voltage Vin -0.3 to VDD+0.3 V
Maximum Output Voltage Vout -0.3 to VDD+0.3 V
Maximum Operating Temperature Topg 0 to +70 o

C

Maximum Storage Temperature Tstg -25 to +125 o

C

3.0 ALLOWABLE OPERATING CONDITIONS

at Ta = 0 to 70oC, VSS = 0V

Name Symbol Condition Min. Max. Unit

Supply Voltage VDD 2.4 3.6 V
Input "H" Voltage Vih1 0.7 x VDD VDD V
Input "L" Voltage Vil1

all inputs except OSCIN

0 0.3 x VDD V
Input "H" Voltage Vih2 0.8 x VDD VDD V
Input "L" Voltage Vil2

OSCIN at RC OSC. mode

0 0.2 x VDD V

Fopg1

crystal OSC. mode

34MHz
Operating Freq.

Fopg2

RC OSC. mode

25MHz

4.0 ELECTRICAL CHARACTERISTICS

at Ta = 0 to 70oC, VSS = 0V

Input Resistance

at VDD = 2.4V

Name Symbol Condition Min. Typ. Max. Unit

M / S Pull-Down Tr Rmsd

Vi = VDD

200 500 1000 Kohm

RES Pull-Down R Rres

Vi = VDD

5 20 50 Kohm

DC Output Characteristics

Name Symb. Condition For Min. Typ. Max. Unit

Output "H" Voltage Vohl

Ioh = -1mA (VDD =2.4V )

1.8 2.1 V

Output "L" Voltage Voll

Iol = 5mA (VDD =2.4V )

LIGHT

0.5 V

Output "H" Voltage Voh2

Ioh = -1mA (VDD = 3V )

1.8 2.1 V

Output "L" Voltage Vol2

Iol = 30mA (VDD = 3V )

Carrier

1.3 V

Output "H" Voltage Voh3

Ioh = -500uA (VDD =2.4V)

1.8 2.1 V

Output "L" Voltage Vol3

Iol = 5 mA (VDD = 2.4V)

IO_A port

0.5 V

Output "H" Voltage Voh4

Ioh = -500uA (VDD =2.4V)

1.8 2.1 V

Output "L" Voltage Vol4

Iol = 1mA (VDD = 2.4V)

I/O_B port

0.6 1 V

5.0 INSTRUCTION TABLE

Instruction Machine Code Function Flag/Remark

NOP 0000 0000 0000 0000 No Operation
OPA Rx 0000 1000 10XX XXXX Port(A) <= (Rx)

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Instruction Machine Code Function Flag/Remark

OPB Rx 0001 0000 10XX XXXX Port(B) <= (Rx)
MRA Rx 0001 1010 10XX XXXX CF <= Rx3 CF
ADC Rx 0010 0000 00XX XXXX (AC) <= (Rx)+(AC)+(CF) CF
ADC* Rx 0010 0001 00XX XXXX (AC),(Rx) <= (Rx)+(AC)+(CF) CF
SBC Rx 0010 0010 00XX XXXX (AC) <= (Rx)+(AC)B+(CF) CF
SBC* Rx 0010 0011 00XX XXXX (AC),(Rx) <= (Rx)+(AC)B+(CF) CF
ADD Rx 0010 0100 00XX XXXX (AC) <= (Rx)+(AC) CF
ADD* Rx 0010 0101 00XX XXXX (AC),(Rx) <= (Rx)+(AC) CF
SUB Rx 0010 0110 00XX XXXX (AC) <= (Rx)+(AC)B+1 CF
SUB* Rx 0010 0111 00XX XXXX (AC),(Rx) <= (Rx)+(AC)B+1 CF
ADN Rx 0010 1000 00XX XXXX (AC) <= (Rx)+(AC)
ADN* Rx 0010 1001 00XX XXXX (AC),(Rx) <= (Rx)+(AC)
AND Rx 0010 1010 00XX XXXX (AC) <= (Rx) AND (AC)
AND* Rx 0010 1011 00XX XXXX (AC),(Rx) <= (Rx) AND (AC)
EOR Rx 0010 1100 00XX XXXX (AC) <= (Rx) EOR (AC)
EOR* Rx 0010 1101 00XX XXXX (AC),(Rx) <= (Rx) EOR (AC)
OR Rx 0010 1110 00XX XXXX (AC) <= (Rx) OR (AC)
OR* Rx 0010 1111 00XX XXXX (AC),(Rx) <= (Rx) OR (AC)
ADCI Ry,D 0011 0000 DDDD 0YYY (AC) <= (Ry)+(D)+(CF) CF
ADCI* Ry,D 0011 0001 DDDD 0YYY (AC),(Ry) <= (Ry)+(D)+(CF) CF
SBCI Ry,D 0011 0010 DDDD 0YYY (AC) <= (Ry)+(D)B+(CF) CF
SBCI* Ry,D 0011 0011 DDDD 0YYY (AC),(Ry) <= (Ry)+(D)B+(CF) CF
ADDI Ry,D 0011 0100 DDDD 0YYY (AC) <= (Ry)+(D) CF
ADDI* Ry,D 0011 0101 DDDD 0YYY (AC),(Ry) <= (Ry)+(D) CF
SUBI Ry,D 0011 0110 DDDD 0YYY (AC) <= (Ry)+(D)B+1 CF
SUBI* Ry,D 0011 0111 DDDD 0YYY (AC),(Ry) <= (Ry)+(D)B+1 CF
ADNI Ry,D 0011 1000 DDDD 0YYY (AC) <= (Ry)+(D)
ADNI* Ry,D 0011 1001 DDDD 0YYY (AC),(Ry) <= (Ry)+(D)
ANDI Ry,D 0011 1010 DDDD 0YYY (AC) <= (Ry) AND (D)
ANDI* Ry,D 0011 1011 DDDD 0YYY (AC),(Ry) <= (Ry) AND (D)
EORI Ry,D 0011 1100 DDDD 0YYY (AC) <= (Ry) EOR (D)
EORI* Ry,D 0011 1101 DDDD 0YYY (AC),(Ry) <= (Ry) EOR (D)
ORI Ry,D 0011 1110 DDDD 0YYY (AC) <= (Ry) OR (D)
ORI* Ry,D 0011 1111 DDDD 0YYY (AC),(Ry) <= (Ry) OR (D)
IPS Rx 0100 0000 00XX XXXX (AC),(Rx) <= Port(S)
IPM Rx 0100 0001 00XX XXXX (AC),(Rx) <= Port(M)
IPA Rx 0100 0010 00XX XXXX (AC),(Rx) <= Port(A)
IPA* Rx 0100 0010 10XX XXXX (AC),(Rx) <= Port(A) I/OA <= I/P
IPB Rx 0100 0011 00XX XXXX (AC),(Rx) <= Port(B)
IPB* Rx 0100 0011 10XX XXXX (AC),(Rx) <= Port(B) I/OB <= I/P
STA Rx 0100 0101 00XX XXXX (Rx) <= (AC)
SR0 Rx 0100 0110 00XX XXXX ACn, Rxn

AC3, Rx3

<= Rx(n+1)
<= 0

SR1 Rx 0100 0110 10XX XXXX ACn, Rxn

AC3, Rx3

<=(Rx(n+1)
<= 1

SL0 Rx 0100 0111 00XX XXXX ACn, Rxn

AC0, Rx0

<= Rx(n-1)
<= 0

SL1 Rx 0100 0111 10XX XXXX ACn, Rxn

AC0, Rx0

<= Rx(n-1)
<= 1

LDS Rx,D 0100 1DDD D0XX XXXX (AC),(Rx) <= (D)

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Instruction Machine Code Function Flag/Remark

MID Rx 0101 0000 00XX XXXX (AC),(Rx)

(ID)

<= (@ID)

<= (ID+1)
MSC Rx 0110 0000 00XX XXXX (AC),(Rx) <= STS3 B1 : TMRF
MAF Rx 0110 0010 00XX XXXX (AC),(Rx) <= STS1 TF2 : AC=0

TF3 : CF
LDA Rx 0110 1110 10XX XXXX (AC) <= (Rx)
MRW

Ry,Rx

0111 00YY Y0XX XXXX (AC),(Ry) <= (Rx)

MWR

Rx,Ry

0111 10YY Y0XX XXXX (AC),(Rx) <= (Ry)
JB0 X 1000 0XXX XXXX XXXX (PC) <= X if (AC0) = 1
JB1 X 1000 1XXX XXXX XXXX (PC) <= X if (AC1) = 1
JB2 X 1001 0XXX XXXX XXXX (PC) <= X if (AC2) = 1
JB3 X 1001 1XXX XXXX XXXX (PC) <= X if (AC3) = 1
JNZ X 1010 0XXX XXXX XXXX (PC) <= X

if (AC) ≠ 0
JNC X 1010 1XXX XXXX XXXX (PC) <= X if (CF) = 0
JZ X 1011 0XXX XXXX XXXX (PC) <= X if (AC) = 0
JC X 1011 1XXX XXXX XXXX (PC) <= X if (CF) = 1
JMP X 1100 0XXX XXXX XXXX (PC) <= X
CALL X 1100 1XXX XXXX XXXX (STACK)

(PC)

<= (PC)+1

<= X
RTS 1101 0000 0000 0000 (PC) <= (STACK) CALL Return
TMS Rx 1110 0100 00XX XXXX X3 ~X0

X5 ~X4

<= (Rx)

<= (AC1,0)
SF X 1110 1000 000X XXXX X0

X1
X2
X3
X4

:CF Set

:RL Set

:CO Set

:LIGHT reset to “L”

:BIT Control Set

CF
RL
CO
LIGHT
BC

RF X 1110 1010 000X XXXX X0

X1
X2
X3
X4

:CF Reset

:RL Reset

:CO Reset

:LIGHT set to “H”

:BIT Control Reset

CF
RL
CO
LIGHT
BC

ALM D,Rx 1110 1100 DDXX XXXX P3 ~ P0

P7 ~ P4
D7 , D6 = 00
D7 , D6 = 01
D7 , D6 = 1X

<= ( Rx )

<= ( AC )

1/4 DUTY

1/3 DUTY

1/2 DUTY

P7~P0 :Pre_
Divider Data

PLC X 1111 1000 0000 00X0 X1 : Reset TMRF
LIDL Rx 1111 1100 XXXX XXXX ID0-3

ID4-7

<= (Rx)

<= (AC)
LIDH Rx 1111 1101 XXXX XXXX ID8-11

ID12-15

<= (Rx)

<= (AC)
STOP 1111 1111 1111 1111 Stop operatio

n

Symbol Description

AC : Accumulator D : Immediate Data
ACn : Accumulator Bit N PC : Program Counter
Rx : Memory of Address X X : Address
Rxn : Memory Bit N of Address X CF : Carry Flag
Ry : Memory of Working Register Y IDh,l : Index Address
@ID : Memory of Index Address

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6.0 TYPICAL APPLICATION CIRCUIT DIAGRAM

RESET
M1
M2
M3
M4
S1
S2
S3
S4
LIGHT
CARRIER
VSS

VDD

OSCOUT

OSCIN

VCC

B4
B3
B2
B1
A4
A3
A2
A1

D2C4

D1

C1

VDD

C2

VDD

D3

VDD

R4 180K

C6

TEST MODE

R1

0.1K

VDD

R2

0.005K~0.01K

VDD

LED

D3

1K

IR LED

D4

3.58MHz

Q1

C1, C2 :20pf D1, D2 :(VT≅

0.2V)

C3 :100µfD3:LED
C4 :0.1µf D4 :IR LED
C5 :47µf
C6 :0.047µf

Note: The threshold voltage of D1, D2 cannot exceed the cutin voltage of Q1, or the IR LED (D4) will always turn

on.

7.0 PACKAGE DIMENSION

300 mil 24 PDIP
Unit: mil

930+/-10

R40

55+/-20

312+/-12

R10Max
(4X)

80+/-20

250+/-4

350+/-20

10

18+/-2Typ 60+/-5Typ

15Min.

15Max

115Min

100Typ

35+/-5

7Typ

1245+/-10

65+/-4

65+/-4