Datasheet MSP3405D, MSP3415D Datasheet (Micronas Intermetall)

MSP 3405D,
MSP 3415D
Multistandard

Edition Oct. 14, 1999
6251-475-2PD

PRELIMINARY DATA SHEET

MICRONAS

MICRONAS

Sound Processors

MSP 34x5D

Contents

Page Section Title

5 1. Introduction

5 1.1. Common Features of MSP 34x5D
5 1.2. Specific MSP 3415D Features
5 1.3. Unsupported MSP 34x0D Functions
5 1.4. MSP 34x0D Inputs and Outputs not included in the MSP 34x5D

6 2. Basic Features of the MSP 34x5D

6 2.1. Demodulator and NICAM Decoder Section
6 2.2. DSP-Section (Audio Baseband Processing)
6 2.3. Analog Section

7 3. Application Fields of the MSP 34x5D

7 3.1. NICAM plus FM/AM-Mono
7 3.2. German 2-Carrier System (DUAL FM System)

PRELIMINARY DATA SHEET

10 4. Architecture of the MSP 34x5D

10 4.1. Demodulator and NICAM Decoder Section
10 4.1.1. Analog Sound IF – Input Section
11 4.1.2. Quadrature Mixers
11 4.1.3. Low-pass Filtering Block for Mixed Sound IF Signals
12 4.1.4. Phase and AM Discrimination
12 4.1.5. Differentiators
12 4.1.6. Low-pass Filter Block for Demodulated Signals
12 4.1.7. High Deviation FM Mode
12 4.1.8. FM-Carrier-Mute Function in the Dual Carrier FM Mode
12 4.1.9. DQPSK-Decoder (MSP 3415D only)
12 4.1.10. NICAM-Decoder (MSP 3415D only)
13 4.2. Analog Section
13 4.2.1. SCART Switching Facilities
13 4.2.2. Stand-by Mode
13 4.3. DSP-Section (Audio Baseband Processing)
13 4.3.1. Dual Carrier FM Stereo/Bilingual Detection
14 4.4. Audio PLL and Crystal Specifications
14 4.5. Digital Control Output Pins
15 4.6. I

16 5. I

17 5.1. Protocol Description
18 5.2. Proposal for MSP 34x5D I
18 5.2.1. Symbols
18 5.2.2. Write Telegrams
18 5.2.3. Read Telegrams
18 5.2.4. Examples
19 5.3. Start-Up Sequence: Power-Up and I

2

S Bus Interface

2

C Bus Interface: Device and Subaddresses

2

C Telegrams

2

C-Controlling

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PRELIMINARY DATA SHEET

Contents, continued

Page Section Title

20 6. Programming the Demodulator Section

20 6.1. Short-Programming and General Programming of the Demodulator Part
21 6.2. Demodulator Write Registers: Table and Addresses
21 6.3. Demodulator Read Registers: Table and Addresses
22 6.4. Demodulator Write Registers for Short-Programming: Functions and Values
22 6.4.1. Demodulator Short-Programming
23 6.4.2. AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono (MSP 3415D only)
24 6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values
24 6.5.1. Register ‘AD_CV’
26 6.5.2. Register ‘MODE_REG’
27 6.5.3. FIR-Parameter
29 6.5.4. DCO-Registers
29 6.6. Demodulator Read Registers: Functions and Values
30 6.6.1. Autodetect of Terrestrial TV-Audio Standards
31 6.6.2. C_AD_BITS (MSP 3415D only)
31 6.6.3. ADD_BITS [10...3] (MSP 3415D only)
31 6.6.4. CIB_BITS (MSP 3415D only)
31 6.6.5. ERROR_RATE (MSP 3415D only)
32 6.6.6. CONC_CT (for compatibility with MSP 3410B)
32 6.6.7. FAWCT_IST (for compatibility with MSP 3410B)
32 6.6.8. PLL_CAPS
32 6.6.9. AGC_GAIN
32 6.7. Sequences to Transmit Parameters and to Start Processing
34 6.8. Software Proposals for Multistandard TV-Sets
34 6.8.1. Multistandard Including System B/G or I (NICAM/FM-Mono only) or

SECAM L (NICAM/AM-Mono only)
34 6.8.2. Multistandard Including System B/G with NICAM/FM-Mono and German DUAL FM
34 6.8.3. Satellite Mode
34 6.8.4. Automatic Search Function for FM-Carrier Detection

MSP 34x5D

36 7. Programming the DSP Section (Audio Baseband Processing)

36 7.1. DSP Write Registers: Table and Addresses
37 7.2. DSP Read Registers: Table and Addresses
38 7.3. DSP Write Registers: Functions and Values
38 7.3.1. Volume Loudspeaker Channel
39 7.3.2. Balance Loudspeaker Channel
39 7.3.3. Bass Loudspeaker Channel
40 7.3.4. Treble Loudspeaker Channel
40 7.3.5. Loudness Loudspeaker Channel
40 7.3.6. Spatial Effects Loudspeaker Channel
41 7.3.7. Volume SCART1
41 7.3.8. Channel Source Modes
41 7.3.9. Channel Matrix Modes
42 7.3.10. SCART Prescale
42 7.3.11. FM/AM Prescale
43 7.3.12. FM Matrix Modes
43 7.3.13. FM Fixed Deemphasis
43 7.3.14. FM Adaptive Deemphasis

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MSP 34x5D

Contents, continued

Page Section Title

43 7.3.15. NICAM Prescale (MSP 3415D only)
43 7.3.16. NICAM Deemphasis (MSP 3415D only)
43 7.3.17. I
43 7.3.18. ACB Register
44 7.3.19. Beeper
44 7.3.20. Identification Mode
44 7.3.21. FM DC Notch
44 7.3.22. Automatic Volume Correction (AVC)
45 7.4. Exclusions for the Audio Baseband Features
45 7.5. DSP Read Registers: Functions and Values
45 7.5.1. Stereo Detection Register
45 7.5.2. Quasi-Peak Detector
46 7.5.3. DC Level Register
46 7.5.4. MSP Hardware Version Code
46 7.5.5. MSP Major Revision Code
46 7.5.6. MSP Product Code
46 7.5.7. MSP ROM Version Code

2

S1 and I2S2 Prescale

PRELIMINARY DATA SHEET

47 8. Specifications

47 8.1. Outline Dimensions
49 8.2. Pin Connections and Short Descriptions
52 8.3. Pin Configurations
55 8.4. Pin Circuits
57 8.5. Electrical Characteristics
57 8.5.1. Absolute Maximum Ratings
58 8.5.2. Recommended Operating Conditions
62 8.5.3. Characteristics

66 9. Application Circuit

67 10. Appendix A: MSP 34x5D Version History

68 11. Data Sheet History

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PRELIMINARY DATA SHEET

MSP 34x5D

Multistandard Sound Processor

Release Notes: The hardware description in this
document is valid for the MSP 34x5D version A2 and
following versions. Revision bars indicate signifi­cant changes to the previous edition.

1. Introduction

The MSP 34x5D is designed as a single-chip Multistan-
dard Sound Processor for applications in analog and
digital TV sets, video recorders, and PC-cards. As deriv­ative versions of the MSP 34x0D, the MSP 34x5D com­bines all demodulator features of the MSP 34x0D with
less I/O and reduced audio baseband processing.

The IC is produced in submicron CMOS technology,
combined with high-performance digital signal proces­sing. The MSP 34x5D is available in the following
packages: PLCC68, PSDIP64, PSDIP52, PQFP80, and
PMQFP44.

Note: The MSP34x5D version has reduced control reg­isters and less functional pins. The remaining registers
are software compatible to the MSP 3410D. The pinning
is compatible to the MSP 3410D.

– Bass, treble, volume, loudness, and spatial effects

processing
– Full SCART in/out matrix without restrictions
– Improved FM-identification (as in MSPC)
– Demodulator short programming
– Autodetection for terrestrial TV-sound standards
– Improved carrier mute algorithm (as in MSPD)
– Improved AM-demodulation (as in MSPD)
– Digital control output pins D_CTR_OUT0/1
– Reduction of necessary controlling
– Less external components

1.2. Specific MSP 3415D Features

– All NICAM standards
– Precise bit-error rate indication
– Automatic switching from NICAM to FM/AM or vice

versa
– Improved NICAM synchronization algorithm

1.3. Unsupported MSP 34x0D Functions

1.1. Common Features of MSP 34x5D

– Dolby Pro Logic together with DPL 351xA
– Analog sound IF input
– No external filters required
– Stereo baseband input via integrated A/D converters
– Two pairs of D/A converters
– Two carrier FM

2

S Interface for version B3 and later versions

– I
– AVC: Automatic Volume Correction

Sound IF 1

MONO IN

SCART1 IN

SCART2 IN

I2C

2

2

2

MSP 34x5D

I2S

5

2

Loudspeaker
OUT

2

SCART
OUT

– Equalizer

1.4. MSP 34x0D Inputs and Outputs not included in

the MSP 34x5D

– 2nd IF input
– 3rd and 4th SCART input
– 2nd SCART output
– 2nd SCART DA
– Headphone output
– Subwoofer output
– ADR interface

Fig. 1–1: Main I/O signals of the MSP 34x5D

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MSP 34x5D

PRELIMINARY DATA SHEET

2. Basic Features of the MSP 34x5D

2.1. Demodulator and NICAM Decoder Section

The MSP 3415D is designed to simultaneously perform
digital demodulation and decoding of NICAM-coded TV
stereo sound, as well as demodulation of FM or AM­mono TV sound. Alternatively, two carrier FM systems
according to the German terrestrial specs can be pro­cessed with the MSP 34x5D.

The MSP 34x5D facilitates profitable multistandard ca­pability, offering the following advantages:

– Automatic Gain Control (AGC) for analog input:

input range: 0.10 – 3 Vpp
– integrated A/D converter for sound IF input
– all demodulation and filtering is performed on chip

and is individually programmable
– easy realization of all digital NICAM standards

(B/G, I, L and D/K, not for MSP 3405D)
– FM-demodulation of all terrestrial standards

(including identification decoding)
– no external filter hardware is required
– only one crystal clock (18.432 MHz) is necessary

2.3. Analog Section

– two selectable analog pairs of audio baseband inputs

(= two SCART inputs)
input level: ≤2 V RMS,
input impedance: ≥25 kΩ

– one selectable analog mono input (i.e. AM sound):

input level: ≤2 V RMS,
input impedance: ≥15 kΩ

– two high-quality A/D converters, S/N-Ratio: ≥85 dB

– 20 Hz to 20 kHz bandwidth for

SCART-to-SCART-copy facilities

– loudspeaker: one pair of four-fold oversampled

D/A-converters
output level per channel: max. 1.4 VRMS
output resistance: max. 5 kΩ
S/N-ratio: ≥85 dB at maximum volume
max. noise voltage in mute mode: ≤10 µV
(BW: 20 Hz ...16 kHz)

– one pair of four-fold oversampled D/A converters

supplying a pair of SCART-outputs.
output level per channel: max. 2 V RMS,
output resistance: max. 0.5 kΩ,
S/N-Ratio: ≥85 dB (20 Hz...16 kHz)

– high deviation FM-mono mode

(max. deviation: approx. ±360 kHz)

2.2. DSP-Section (Audio Baseband Processing)

– two digital inputs and one digital output via I

external signal processors like the DPL 351x.
– flexible selection of audio sources to be processed
– performance of terrestrial deemphasis systems

(FM, NICAM)
– digitally performed FM-identification decoding and

dematrixing
– digital baseband processing: volume, bass, treble,

loudness, and spatial effects
– simple controlling of volume, bass, treble, loudness,

and spatial effects

2

S bus for

6 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

3. Application Fields of the MSP 34x5D

In the following sections, a brief overview about the two
main TV sound standards, NICAM 728 and German FM­Stereo, demonstrates the complex requirements of a
multistandard audio IC.

3.1. NICAM plus FM/AM-Mono

According to the British, Scandinavian, Spanish, and
French TV-standards, high-quality stereo sound is
transmitted digitally. The systems allow two high-quality
digital sound channels to be added to the already exist­ing FM/AM-channel. The sound coding follows the for­mat of the so-called Near Instantaneous Companding
System (NICAM 728). Transmission is performed using
Differential Quadrature Phase Shift Keying (DQPSK).
Table 3–2 gives some specifications of the sound coding
(NICAM); Table 3–3 offers an overview of the modula­tion parameters.

In the case of NICAM/FM (AM) mode, there are three dif­ferent audio channels available: NICAM A, NICAM B,
and FM/AM-mono. NICAM A and B may belong either to
a stereo or to a dual language transmission. Information
about operation mode and about the quality of the NI­CAM signal can be read by the CCU via the control bus.
In the case of low quality (high bit error rate), the CCU
may decide to switch to the analog FM/AM-mono sound.
Alternatively, an automatic NICAM-FM/AM switching
may be applied.

3.2. German 2-Carrier System (DUAL FM System)

Since September 1981, stereo and dual sound pro­grams have been transmitted in Germany using the
2-carrier system. Sound transmission consists of the al­ready existing first sound carrier and a second sound
carrier additionally containing an identification signal.
More details of this standard are given in Tables 3–1 and
3–4. For D/K and M-Korea, very similar systems are used.

Table 3–1: TV standards

TV-System Position of Sound

Carrier [MHz]

B/G 5.5/5.7421875 FM-Stereo PAL Germany

B/G 5.5/5.85 FM-Mono/NICAM PAL Scandinavia,Spain

L 6.5/5.85 AM-Mono/NICAM SECAM-L France

I 6.0/6.552 FM-Mono/NICAM PAL UK

D/K 6.5 /6.2578125 D/K1

6.5/6.7421875 D/K2

6.5/5.85 D/K-NICAM

M
M-Korea

Satellite
Satellite

4.5

4.5/4.724212

6.5

7.02/7.2

Sound
Modulation

FM-Stereo

FM-Mono/NICAM

FM-Mono
FM-Stereo

FM-Mono
FM-Stereo

Color System Country

SECAM-East USSR

Hungary

NTSC USA

Korea

PAL
PAL

Europe (ASTRA)
Europe (ASTRA)

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MSP 34x5D

Roll-off fact

t

FM

FM

FM
analog and modulated

Table 3–2: Summary of NICAM 728 sound coding characteristics

Characteristics Values

Audio sampling frequency 32 kHz

Number of channels 2

Initial resolution 14 bit/sample

Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-sam-

ples (1 ms) blocks

Coding for compressed samples 2’s complement

Preemphasis CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz)

Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis

network (2 kHz)

PRELIMINARY DATA SHEET

Table 3–3: Summary of NICAM 728 sound modulation parameters

Specification I B/G L D/K

Carrier frequency of
digital sound

Transmission rate 728 kBit/s

Type of modulation Differentially encoded quadrature phase shift keying (DQPSK)

Spectrum shaping

or

Carrier frequency of
analog sound componen

Power ratio between
vision carrier and
analog sound carrier

Power ratio between

digital sound carrier

6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz

by means of Roll-off filters

1.0 0.4 0.4 0.4

6.0 MHz
mono

10 dB 13 dB 10 dB 16 dB 13 dB

10 dB 7 dB 17 dB 11 dB Hungary Poland

5.5 MHz
mono

6.5 MHz AM mono 6.5 MHz

terres­trial

cable

12 dB 7 dB

mono

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PRELIMINARY DATA SHEET

MSP 34x5D

Table 3–4: Key parameters for B/G, D/K, and M 2-carrier sound system

Sound Carriers Carrier FM1 Carrier FM2

B/G D/K M B/G D/K M

Vision/sound power difference 13 dB 20 dB

Sound bandwidth 40 Hz to 15 kHz
Pre-emphasis 50 µs 75 µs 50 µs 75 µs
Frequency deviation ±50 kHz ±25 kHz ±50 kHz ±25 kHz

Sound Signal Components

Mono transmission mono mono

Stereo transmission (L+R)/2 (L+R)/2 R (L–R)/2

Dual sound transmission language A language B

Identification of Transmission Mode on Carrier FM2

Pilot carrier frequency in kHz 54.6875 55.0699

Type of modulation AM

Modulation depth 50%

Modulation frequency mono: unmodulated

Tuner

33 34 39 MHz 5 9 MHz

SAW Filter Sound IF Filter

Sound
IF
Mixer

Vision
Demo­dulator

Mono

stereo: 117.5 Hz
dual: 274.1 Hz

According to the mixing characteristics
of the Sound-IF mixer, the Sound-IF
filter may be omitted.

1

MSP 34x5D

149.9 Hz

276.0 Hz

Loudspeaker

Composite
Video

SCART
Inputs

Fig. 3–1: Typical MSP 34x5D application

SCART1

SCART2

2

2

I2S1

Dolby
Pro Logic
Processor
DPLA

Digital
Signal
Source

I2S2

2

SCART1

SCART
Output

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MSP 34x5D

PRELIMINARY DATA SHEET

4. Architecture of the MSP 34x5D

Fig. 4–1 shows a simplified block diagram of the IC. Its
architecture is split into three main functional blocks:

1. demodulator and NICAM decoder section

2. digital signal processing (DSP) section performing
audio baseband processing

3. analog section containing two A/D-converters,
four D/A-converters, and SCART switching facilities.

4.1. Demodulator and NICAM Decoder Section

4.1.1. Analog Sound IF – Input Section

The input pins ANA_IN1+ and ANA_IN– offer the possi­bility to connect sound IF (SIF) sources to the MSP
34x5D. The analog-to-digital conversion of the prese­lected sound IF signal is done by an A/D-converter,
whose output can be used to control an analog automat­ic gain circuit (AGC), providing an optimal level for a
wide range of input levels. It is possible to switch be­tween automatic gain control and a fixed (setable) input
gain. In the optimal case, the input range of the A/D con­verter is completely covered by the sound IF source.
Some combinations of SAW filters and sound IF mixer
ICs, however, show large picture components on their
outputs. In this case, filtering is recommended. It was
found, that the high pass filters formed by the coupling
capacitors at pin ANA_IN1+ (as shown in the application
diagram) are sufficient in most cases.

Sound IF

ANA_IN1+

Mono

MONO_IN

SC1_IN_L

SCART1

SC1_IN_R

SC2_IN_L

SCART2

SC2_IN_R

Demodulator

and NICAM

Decoder

A/D

A/D

2

I

S_DA_IN1

2

S_DA_OUT

I

I2S_DA_IN2

I2S Interface

I2S1/2L/R I2S_L/R

FM1/AM

FM2

NICAM A

NICAM B

IDENT

DSP

SCART L

SCART R

I2S_CL

LOUD­SPEAKER L

LOUD­SPEAKER R

SCART1_L

SCART1_R

2

S_WS

I

XTAL_IN

D/A

D/A

D/A

D/A

XTAL_OUT

Audio PLL

2

D_CTR_OUT0/1

DACM_L

Loudspeaker

DACM_R

SC1_OUT_L

SCART

SC1_OUT_R

SCART Switching Facilities

Fig. 4–1: Architecture of the MSP 34x5D

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MSP 34x5D

4.1.2. Quadrature Mixers

The digital input coming from the integrated A/D conver­ter may contain audio information at a frequency range
of theoretically 0 to 9 MHz corresponding to the selected
standards. By means of two programmable quadrature
mixers, two different audio sources; for example, NI­CAM and FM-mono, may be shifted into baseband posi­tion. In the following, the two main channels are provided
to process either:

– NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2) si-

multaneously or, alternatively,

– FM2 (MSP-Ch1) and FM1 (MSP-Ch2).

NICAM is not possible with MSP 3405D.

Two programmable registers, to be divided up into low
and high part, determine frequency of the oscillator,
which corresponds to the frequency of the desired audio
carrier. In section 6.2., format and values of the registers
are listed.

4.1.3. Low-pass Filtering Block
for Mixed Sound IF Signals

Data shaping and/or FM bandwidth limitation is per­formed by a linear phase Finite Impulse Response (FIR­filter). Just like the oscillators’ frequency, the filter coeffi­cients are programmable and are written into the IC by
the CCU via the control bus. Thus, for example, different
NICAM versions can easily be implemented. Two not
necessarily different sets of coefficients are required,
one for MSP-Ch1 (NICAM or FM2) and one for MSP­Ch2 (FM1 = FM-mono). In section 6.5.3., several coeffi­cient sets are proposed.

VREFTOP

ANA_IN1+

ANA_IN-

FRAME
NICAMA

DCO2

AD_CV[7:1]

AGC AD

Pins

Internal signal lines (see fig. 4–5)

Demodulator Write Registers

DCO1

Oscillator

FIR1

Mixer Lowpass

MSP sound IF channel 1
(MSP-Ch1: FM2, NICAM)

MSP sound IF channel 2
(MSP-Ch2: FM1, AM)

Mixer Lowpass

FIR2

Oscillator

DCO2

Phase and
AM Dis­crimination

Amplitude

Phase and
AM Dis­crimination

MODE_REG[6]

Phase

Amplitude

Differen­tiator

Phase

DQPSK
Decoder

Differen­tiator

Carrier
Detect

AD_CV[9]

Carrier
Detect

MODE_REG[8]

MSP 3415D only

NICAM
Decoder

LowpassMute

LowpassMute

NICAMA

NICAMB

FM2

Mixer IDENT

FM1/AM

Fig. 4–2: Demodulator architecture of MSP 34x5D

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PRELIMINARY DATA SHEET

4.1.4. Phase and AM Discrimination

The filtered sound IF signals are demodulated by means
of the phase and amplitude discriminator block. On the
output, the phase and amplitude is available for further
processing. AM signals are derived from the amplitude
information, whereas the phase information serves for
FM and NICAM (DQPSK) demodulation.

4.1.5. Differentiators

FM demodulation is completed by differentiating the
phase information output.

4.1.6. Low-pass Filter Block
for Demodulated Signals

The demodulated FM and AM signals are further low­pass filtered and decimated to a final sampling frequen­cy of 32 kHz. The usable bandwidth of the final base­band signals is about 15 kHz.

4.1.7. High Deviation FM Mode

4.1.8. FM-Carrier-Mute Function
in the Dual Carrier FM Mode

To prevent noise effects or FM identification problems in
the absence of one of the two FM carriers, the
MSP 3415 D offers a carrier detection feature, which
must be activated by means of AD_CV[9]. If no FM carri­er is available at the MSPD channel 1, the correspond­ing channel FM2 is muted. If no FM carrier is available
at the MSPD channel 2, the corresponding channel FM1
is muted.

4.1.9. DQPSK-Decoder (MSP 3415D only)

In case of NICAM-mode, the phase samples are de­coded according the DQPSK-coding scheme. The out­put of this block contains the original NICAM-bitstream.

4.1.10. NICAM-Decoder (MSP 3415D only)

Before any NICAM decoding can start, the MSP must
lock to the NICAM frame structure by searching and syn­chronizing to the so-called Frame Alignment Words
(FAW).

By means of MODE_REG [9], the maximum FM-devi­ation can be extended to approximately ±360 kHz. Since
this mode can be applied only for the MSP sound IF
channel 2, the corresponding matrices in the baseband
processing must be set to sound A. Apart from this, the
coefficient sets 380 kHz FIR2 or 500 kHz FIR2 must be
chosen for the FIR2. In relation to the normal FM-mode,
the audio level of the high-deviation mode is reduced by
6 dB. The FM-prescaler should be adjusted accordingly.
In high deviation FM-mode, neither FM-stereo nor FM­identification nor NICAM processing is possible simulta­neously.

To reconstruct the original digital sound samples, the NI­CAM-bitstream has to be descrambled, deinterleaved,
and rescaled. Also, bit error detection and correction
(concealment) is performed in this NICAM specific
block.

To facilitate the Central Control Unit CCU to switch the
TV-set to the actual sound mode, control information on
the NICAM mode and bit error rate are supplied by the
the NICAM-Decoder. It can be read out via the I

An automatic switching facility (AUTO_FM) between NI­CAM and FM/AM reduces the amount of CCU-instruc­tions in case of bad NICAM reception.

2

C-Bus.

12 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

4.2. Analog Section

4.2.1. SCART Switching Facilities

The analog input and output sections include full matrix
switching facilities, which are shown in Fig. 4–3.

The switches are controlled by the ACB bits defined in
the audio processing interface (see section 7. Program­ming the DSP Section).

SCART_IN

SC1_IN_L/R

SC2_IN_L/R

MONO_IN

intern.
signal
lines

pins

ACB[5,9,8]

S1

ACB[6,11,10]

to Audio Baseband
Processing (DSP_IN)

A

D

SCARTL/R

SCART_OUT

4.3. DSP-Section (Audio Baseband Processing)

All audio baseband functions are performed by digital
signal processing (DSP). The DSP functions are
grouped into three processing parts: input preproces­sing, channel source selection, and channel postpro­cessing (see Fig. 4–5 and section 7.).

The input preprocessing is intended to prepare the vari­ous signals of all input sources in order to form a stan­dardized signal at the input to the channel selector. The
signals can be adjusted in volume, are processed with
the appropriate deemphasis, and are dematrixed if nec­essary.

Having prepared the signals that way, the channel selec­tor makes it possible to distribute all possible source sig­nals to the desired output channels.

All input and output signals can be processed simulta­neously with the exception that FM2 cannot be pro­cessed at the same time as NICAM. FM-identification
and adaptive deemphasis are not possible simulta­neously (if adaptive deemphasis is active, the ID-level in
stereo detection register is not valid).

from Audio Baseband
Processing (DSP_OUT)

SCART1_L/R

D

A

SC1_OUT_L/R

S2

Fig. 4–3: SCART switching facilities (see 7.3.18.)
Switching positions show the default configuration af­ter power-on reset. Note: SCART_OUT is undefined
after RESET!

4.2.2. Stand-by Mode

If the MSP 34x5D is switched off by first pulling STAND­BYQ low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Stand-by’-mode), the switches
S1 and S2 (see Fig. 4–3) maintain their position and
function. This facilitates the copying from selected
SCART-inputs to SCART-outputs in the TV-set’s stand­by mode.

In case of power-on start or starting from stand-by, the
IC switches automatically to the default configuration,
shown in Fig. 4–3. This action takes place after the first

2

I

C transmission into the DSP part. By transmitting the
ACB register first, the individual default setting mode of
the TV set can be defined.

4.3.1. Dual Carrier FM Stereo/Bilingual Detection

For the terrestrial dual FM carrier systems, audio in­formation can be transmitted in three modes: mono, ste­reo, or bilingual. To obtain information about the current
audio operation mode, the MSP 34x5D detects the so­called identification signal. Information is supplied via
the Stereo Detection Register to an external CCU.

IDENT

AM

Demodu-

lation

Stereo

Detection

Filter

Bilingual
Detection

Filter

Level

Detect

Level

Detect

Stereo

Detection

–

Register

Fig. 4–4: Stereo/bilingual detection

13Micronas

MSP 34x5D

2

PRELIMINARY DATA SHEET

Analog
Inputs

Demodulated
IF
Inputs

S Bus

puts

SCARTL

SCARTR

FM1/AM

FM2

NICAMA

NICAMB

I2S1L

2

S1R

I

2

I

S2L

2

S2R

I

DC level readout FM1

Deemphasis

50/75 µs

DC level readout FM2

Deemphasis

J17

MSP 3415D only

SCART

Prescale

FM /AM

Prescale

NICAM

Prescale

I2S1

Prescale

2

I

S2

Prescale

FM-Matrix

Loudspeaker

Channel

Matrix

SCART1
Channel

Matrix

Channel Souce Select

Quasi-Peak

Detector

Channel

Matrix

Fig. 4–5: Audio Baseband Processing (DSP-Firmware)

Bass

ȍ

AVC

Treble

Quasi peak readout L

Quasi peak readout R

I2S

Loudness

Beeper

NICAMA

Volume

Balance

Volume

Internal signal lines (see Fig. 4–2 and Fig. 4–3)

Loudspeaker L

Loudspeaker R

SCART1_L

SCART1_R

2

I

SL

I2SR

Loudspeaker
Outputs

SCART
Output

2

I

S

Outputs

Table 4–1: Some examples for recommended channel assignments for demodulator and audio processing part

Mode MSP Sound IF-

Channel 1

B/G-Stereo FM2 (5.74 MHz): R FM1 (5.5 MHz): (L+R)/2 B/G Stereo Speakers: FM Stereo

B/G-Bilingual FM2 (5.74 MHz): Sound B FM1 (5.5 MHz): Sound A No Matrix Speakers: FM Speakers: Sound A

NICAM-I-ST/

NICAM (6.552 MHz) FM (6.0 MHz): mono No Matrix Speakers: NICAM Speakers: Stereo

FM-mono

Sat-Mono not used FM (6.5 MHz): mono No Matrix Speakers: FM Sound A

Sat-Stereo 7.2 MHz: R 7.02 MHz: L No Matrix Speakers: FM Stereo

Sat-Bilingual 7.38 MHz: Sound C 7.02 MHz: Sound A No Matrix Speakers: FM Speakers: Sound A

Sat-High Dev.

don’t care 6.552 MHz No Matrix Speakers: FM Speakers: Sound A

Mode

4.4. Audio PLL and Crystal Specifications

MSP Sound IF­Channel 2

FM­Matrix

Channel­Select

Channel
Matrix

H. Phone: Sound B

H. Phone: Sound A

H. Phone: Sound B=C

H. Phone: Sound A

sult, the whole audio system is supplied with a con­trolled 18.432 MHz clock.

The MSP 34x5D requires a 18.432 MHz (12 pF, parallel)
crystal. The clock supply of the whole system depends
on the MSP 34x5D operation mode:

1. FM-Stereo, FM-Mono:

Remark on using the crystal:

External capacitors at each crystal pin to ground are re­quired (see General Crystal Recommendations on page

60).

The system clock runs free on the crystal’s 18.432
MHz.

4.5. Digital Control Output Pins

2. NICAM:
An integrated clock PLL uses the 364 kHz baud-rate,
accomplished in the NICAM demodulator block, to
lock the system clock to the bit rate, respectively, 32
kHz sampling rate of the NICAM transmitter. As a re-

The static level of two output pins of the MSP 34x5D
(D_CTR_OUT0/1) is switchable between HIGH and
LOW by means of the I

2

C-bus. This enables the control­ling of external hardware controlled switches or other
devices via I

2

C-bus (see section 7.3.18.).

14 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

4.6. I2S Bus Interface

By means of this standardized interface, additional fea­ture processors can be connected to the MSP 34x0D.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I2S_WS signal changes at the word bound­aries. The PHILIPS format, which is characterized by a
change of the I2S_WS signal one I2S_CL period before
the word boundaries, is selected by setting
MODE_REG[4]=1.

The MSP 34x5D normally serves as the master on the
I2S interface. Here, the clock and word strobe lines are
driven by the MSP. By setting MODE_REG[3]=1, the
MSP 34x5D is switched to a slave mode. Now, these
lines are input to the MSP and the master clock is syn­chronized to 576 times the I2S_WS rate (32 kHz). NI­CAM operation is not possible in this mode.

The I2S bus interface consists of five pins:

1. I2S_DA_IN1, I2S_DA_IN2:
For input, four channels (two channels per line, 2*16
bits) per sampling cycle (32 kHz) are transmitted.

2. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling
cycle (32 kHz) are transmitted.

3. I2S_CL:
Gives the timing for the transmission of I2S serial data
(1.024 MHz).

4. I2S_WS:
The I2S_WS word strobe line defines the left and right
sample.

A precise I2S timing diagram is shown in Fig. 4–6.

(Data: MSB first)

1/F

I2S_WS

SONY Mode SONY Mode

PHILIPS Mode

I2S_CL

I2S_DAIN

I2S_DAOUT

R LSB L MSB

R LSB L MSB

Detail C Detail A,B

I2S_CL

I2S_WS as INPUT

PHILIPS/SONY Mode programmable by MODE_REG[4]

Detail A

16 bit left channel

Detail B

16 bit left channel 16 bit right channel

1/F

I2SCL

T

I2SWS1

T

I2S5

T

I2SWS2

T

I2S6

I2SWS

PHILIPS Mode

Detail C

L LSB R MSB

L LSB R MSB

I2S_CL

I2S_DA_IN

16 bit right channel

T

I2S1

T

I2S3

R LSB L LSB

R LSB L LSB

T

I2S2

T

I2S4

I2S_WS as OUTPUT

Fig. 4–6: I2S bus timing diagram

I2S_DA_OUT

15Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

5. I2C Bus Interface: Device and Subaddresses

As a slave receiver, the MSP 34x5D can be controlled

2

via I

C bus. Access to internal memory locations is
achieved by subaddressing. The demodulator and the
DSP processor parts have two separate subaddressing
register banks.

In order to allow for more MSP 34x5D ICs to be con­nected to the control bus, an ADR_SEL pin has been im­plemented. With ADR_SEL pulled to high, low, or left
open, the MSP 34x5D responds to changed device ad­dresses. Thus, three identical devices can be selected.

By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.

The IC is selected by asserting a special device address
in the address part of an I
dress pair is defined as a write address (80, 84, or 88
and a read address (81, 85, or 89

2

C transmission. A device ad-

) (see Table 5–1).

hex

hex

Writing is done by sending the device write address, fol­lowed by the subaddress byte, two address bytes, and
two data bytes. Reading is done by sending the device
write address, followed by the subaddress byte and two
address bytes. Without sending a stop condition, read­ing of the addressed data is completed by sending the
device read address (81, 85, or 89
bytes of data (see Fig. 5–1: “I

2

C Bus Protocol” and sec-

tion 5.2. “Proposal for MSP 34x5D I

) and reading two

hex

2

C Telegrams”).

Due to the internal architecture of the MSP 34x5D the IC
cannot react immediately to an I

2

C request. The typical
response time is about 0.3 ms for the DSP processor
part and 1 ms for the demodulator part if NICAM proces­sing is active. If the receiver (MSP) can’t receive another
complete byte of data until it has performed some other
function; for example, servicing an internal interrupt, it
can hold the clock line I

2

C_CL LOW to force the trans­mitter into a wait state. The positions within a transmis­sion where this may happen are indicated by ’Wait’ in
section 5.1. The maximum Wait-period of the MSP dur­ing normal operation mode is less than 1 ms.

2

I

C bus error caused by MSP hardware problems:
In case of any internal error, the MSPs wait-period is ex­tended to 1.8 ms. Afterwards, the MSP does not ac­knowledge (NAK) the device address. The data line will
be left HIGH by the MSP and the clock line will be re­leased. The master can then generate a STOP condition

)

to abort the transfer.

By means of NAK, the master is able to recognize the er­ror state and to reset the IC via I

2

C bus. While transmit­ting the reset protocol (see section 5.2.4. on page 18) to
‘CONTROL’, the master must ignore the not acknowl­edge bits (NAK) of the MSP.

A general timing diagram of the I

2

C bus is shown in

Fig. 5–2 on page 18.

Table 5–1: I

2

C Bus Device Addresses

ADR_SEL Low High Left Open

Mode Write Read Write Read Write Read

MSP device address 80

hex

81

hex

84

hex

85

hex

88

hex

Table 5–2: I2C Bus Subaddresses

Name Binary Value Hex Value Mode Function

CONTROL 0000 0000 00 W software reset

TEST 0000 0001 01 W only for internal use

WR_DEM 0001 0000 10 W write address demodulator

RD_DEM 0001 0001 11 W read address demodulator

WR_DSP 0001 0010 12 W write address DSP

89

hex

RD_DSP 0001 0011 13 W read address DSP

16 Micronas

PRELIMINARY DATA SHEET

Ç

MSP 34x5D

Table 5–3: Control Register (Subaddress: 00

hex

)

Name Subaddress MSB 14 13..1 LSB

CONTROL 00 hex 1 : RESET

0 0 0

0 : normal

5.1. Protocol Description

Write to DSP or Demodulator

S write

device

address

Wait ACK sub-addr ACK addr-byte

high

ACK addr-byte low ACK data-byte high ACK data-byte low ACK P

Read from DSP or Demodulator

S write

device

address

Wait ACK sub-addr ACK addr-byte

high

ACK addr-byte

low

ACK S read

device

address

Wait ACK data-byte

high

ACK data-byte

Ç

Write to Control or Test Registers

S write

device

address

Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P

Note: S = I2C-Bus Start Condition from master

P = I

2

C-Bus Stop Condition from master

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, gray)

or master (=CCU, hatched)

NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate ‘End of Read’

or from MSP indicating internal error state

Wait = I

2

C-Clock line held low by the slave (=MSP) while interrupt is serviced (<1.8 ms)

low

NAK P

I2C_DA

2

C_CL

I

Fig. 5–1: I

1

0

SP

2

C bus protocol

(MSB first; data must be stable while clock is high)

17Micronas

MSP 34x5D

I2C_CL

T

I2C4

1/f

I2C

T

PRELIMINARY DATA SHEET

I2C3

T

I2C1

I2C_DA as input

I2C_DA as output

Fig. 5–2: I2C bus timing diagram

5.2. Proposal for MSP 34x5D I

5.2.1. Symbols

daw write device address
dar read device address
< Start Condition
> Stop Condition
aa Address Byte
dd Data Byte

T

I2C5

2

C Telegrams

Data: MSB first

T

I2COL2

T

I2C6

T

I2COL1

T

I2C2

5.2.2. Write Telegrams

<daw 00 d0 00> write to CONTROL register
<daw 10 aa aa dd dd> write data into demodulator
<daw 12 aa aa dd dd> write data into DSP

5.2.3. Read Telegrams

<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP

5.2.4. Examples

<80 00 80 00> RESET MSP statically
<80 00 00 00> clear RESET
<80 12 00 08 01 20> set loudspeaker channel source

to NICAM and Matrix to STEREO

18 Micronas

PRELIMINARY DATA SHEET

5.3. Start-Up Sequence: Power-Up and I2C-Controlling

After power-on or RESET (see Fig. 5–3), the IC is in an
inactive state. The CCU has to transmit the required co­efficient set for a given operation via the I

2

C bus. Initial­ization should start with the demodulator part. If required
for any reason, the audio processing part can be loaded
before the demodulator part.

DVSUP
AVSUP

4.5 V

MSP 34x5D

RESETQ

0.7×DVSUP

0.45...0.55×DVSUP

Internal
Reset

t/ms

Low-to-High
Threshold

High-to-Low
Threshold

t/ms

Reset Delay
>2 ms

High

Low

Power-up reset: threshold and timing
Note: 0.7×DVSUP means 3.5 Volt with DVSUP = 5.0 Volt

Fig. 5–3: Power-up sequence

t/ms

Note: The reset should
not reach high level
before the oscillator has
started. This requires a
reset delay of >2 ms

19Micronas

MSP 34x5D

6. Programming the Demodulator Section

6.1. Short-Programming and General Programming of the Demodulator Part

The Demodulator Part of the MSP 34x5D can be programmed in two different modes:

PRELIMINARY DATA SHEET

1. Demodulator Short-Programming facilitates a
comfortable way to set up the demodulator for many ter­restrial TV-sound standards with one single I
transmission. The coding is listed in section 6.4.1.. If a
parameter doesn’t coincide with the individual program­ming concept, it simply can be overwritten by using the
General Programming mode. Some bits of the registers
AD_CV (see section 6.5.1. ) and MODE_REG (see sec­tion 6.5.2. ) are not affected by the short-programming.
They must be transmitted once if their reset status does
not fit. The Demodulator Short-Programming is not com­patible to MSP 3410B and MSP 3400C.

Autodetection for terrestrial TV standards (as part of
the below Demodulator Short-Programming) provides
the most comfortable way to set up the MSPD-demodu­lator. This feature facilitates within 0.5 s the detection
and set-up of the actual TV-sound standard. Since the
detected standard is readable by the control processor,
the autodetection feature is mainly recommended for
the primary set-up of a TV-set: after having determined
once the corresponding TV-channels, their sound stan­dards can be stored and later on programmed by the De­modulator Short-Programming (see sections 6.4.1. and

6.6.1.).

2

C-Bus

2. General Programming ensures the software com­patibility to other MSPs. It offers a very flexible way to ap­ply all of the MSP 34x5D demodulator facilities. All regis­ters except 0020
corresponding to the individual requirements. For satel­lite applications, with their many variations, this mode
must be selected.

All transmissions on the control bus are 16 bits wide.
However, data for the demodulator part have only 8 or
12 significant bits. These data have to be inserted LSB­bound and filled with zero bits into the 16-bit transmis­sion word. Table 4–1 explains how to assign FM carriers
to the MSP-Sound IF channels and the corresponding
matrix modes in the audio processing part.

have to be written with values

hex

20 Micronas

PRELIMINARY DATA SHEET

6.2. Demodulator Write Registers: Table and Addresses

MSP 34x5D

Table 6–1: Demodulator Write Registers; Subaddress: 10

Demodulator
Write Registers

Demodulator
Short­Programming

AUTO_FM/AM 0021 Only for NICAM (MSP 3415D): Automatic switching between NICAM and

Write Registers necessary for General Programming Mode only

AD_CV 00BB input selection, configuration of AGC, Mute Function and selection of

MODE_REG 0083 mode register

FIR1
FIR2

DCO1_LO
DCO1_HI

DCO2_LO
DCO2_HI

Address
(hex)

0020 Write into this register to apply Demodulator Short Programming (see

0001
0005

0093
009B

00A3
00AB

Function

section 6.4.1.). If the internal setting coincidences with the individual re­quirements no more of the remaining Demodulator Write Registers have
to be transferred.

FM/AM in case of bad NICAM reception (see section 6.4.2.)

A/D-converter, FM-Carrier-Mute on/off

filter coefficients channel 1 (6 ⋅ 8 bit)
filter coefficients channel 2 (6 ⋅ 8 bit), + 3 ⋅ 8 bit offset (total 72 bit)

increment channel 1 Low Part
increment channel 1 High Part

increment channel 2 Low Part
increment channel 2 High Part

; these registers are not readable!

hex

PLL_CAPS 001F switchable PLL capacitors to tune open-loop frequency; to use only if

NICAM of MODE_REG = 0
normally not of interest for the customer

6.3. Demodulator Read Registers: Table and Addresses

Table 6–2: Demodulator Read Registers; Subaddress: 11

Demodulator
Read Registers

Result of
Autodetection

C_AD_BITS 0023 NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits

ADD_BITS 0038 NICAM: bit [10:3] of additional data bits

CIB_BITS 003E NICAM: CIB1 and CIB2 control bits

ERROR_RATE 0057 NICAM error rate, updated with 182 ms

CONC_CT 0058 only to be used in MSPB compatibility mode

Address
(hex)

007E see Table 6–13

Function

; these registers are not writeable!

hex

FAWCT_IST 0025 only to be used in MSPB compatibility mode

PLL_CAPS 021F Not for customer use.

AGC_GAIN 021E Not for customer use.

Note: All NICAM relevant registers are “0” for MSP 3405D.

21Micronas

MSP 34x5D

Reset, then

B/G

Terrestrial TV

1)

PRELIMINARY DATA SHEET

6.4. Demodulator Write Registers for Short-Programming: Functions and Values

In the following, the functions of some registers are explained and their (default) values are defined:

6.4.1. Demodulator Short-Programming

Table 6–3: MSP 34x5D Demodulator Short-Programming

Demodulator Short-Programming 0020

hex

TV-Sound Standard Internal Setting

Description Code

(hex)

AD_CV

(see Table 6–5)

2)

MODE_

2)

REG

(see
Table 6–8)

DCO1
(MHz)

DCO2
(MHz)

FIR1/2
Coefficients

Identifica­tion
Mode

Autodetection 0001 Detects and sets one of the standards listed below, if available. Results are to be

read out of the demodulator read register ”Result of Autodetection” (Section 6.6.1.)

M Dual-FM 0002 AD_CV-FM M1 4.72421 4.5 Reset, then

Standard M

B/G Dual-FM 0003 AD_CV-FM M1 5.74218 5.5

D/K1 Dual-FM 0004 AD_CV-FM M1 6.25781 6.5

see Table 6–11:
Terrestrial TV­Standards

Standard

D/K2 Dual-FM 0005 AD_CV-FM M1 6.74218 6.5

0006/
0007

reserved for future Dual FM Standards AUTO_

FM/AM

NICAM-Modes for MSP 3415D only; MSP 3405D responds with FM/AM Mono

B/G-NICAM-FM 0008 AD_CV-FM M2 5.85 5.5

L-NICAM-AM 0009 AD_CV-AM M3 5.85 6.5

see Table 6–11:

-

I-NICAM-FM 000A AD_CV-FM M2 6.552 6.0

Standards

D/K-NICAM-FM 000B AD_CV-FM M2 5.85 6.5

>000B reserved for future NICAM Standards

1)

corresponds to the actual setting of AUTO_FM (Address = 0021

2)

Bits of AD_CV or MODE_REG, which are not affected by the short-programming, must be transmitted sepa-

hex

)

rately if their reset status does not fit.

Note: All parameters in the DSP section (Audio Baseband Processing), except the identification mode register,
are not affected by the Demodulator Short-Programming . They still have to be defined by the control processor.

22 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

6.4.2. AUTO_FM/AM: Automatic Switching between

NICAM and FM/AM-Mono (MSP 3415D only)

In case of bad NICAM transmission or loss of the NI­CAM-carrier, the MSPD offers a comfortable mode to
switch back to the FM/AM-mono signal. If automatic
switching is active, the MSP internally evaluates the ER­ROR_RATE. All output channels which are assigned to
the NICAM-source are switched back to the FM/AM­mono source without any further CCU instruction, if the
NICAM-carrier fails or the ERROR_RATE exceeds the
definable threshold.

Note, that the channel matrix of the corresponding out­put-channels must be set according to the NICAM-mode
and need not be changed in the FM/AM-fall-back case.
An appropriate hysteresis algorithm avoids oscillating
effects. Bit 11 of the register C_AD_BITS (Address:
0023
tus (see section 6.6.2.).

) informs about the actual NICAM-FM/AM-Sta-

hex

There are two possibilities to define the threshold decid­ing for NICAM or FM/AM-mono (see Table 6–4):

1. default value of the MSPD (internal threshold=700,
i.e. switch to FM/AM if ERROR_RATE > 700)

2. definable by the customer (recommendable range:

threshold = 50....2000, i. e. Bits [10:1] = 25...1000).

Note:
The auto_fm feature is only active if the NICAM-bit of
MODE_REG is set.

Table 6–4: Coding of automatic NICAM-FM/AM switching; reset status: mode 0

Mode Auto_fm [11....0]

Addr. = 0021

0.
default

1. Bit [0] = 1

2. Bit [0] = 1

3. Bit [11] = [0] = 1

Bit [0] = 0
Bits [11...1] = 0

Bit [11:1] = 0

Bit [10:1] = 25...1000 int

Bit [11] = 0

Bit [10...1]= 0

hex

= threshold/2

Selected Sound at the
NICAM Channel Select

always NICAM none Compatible to MSP 3410B,

NICAM or FM/AM,
depending on
ERROR_RATE

NICAM or FM/AM,
depending on
ERROR_RATE

always FM/AM none Forced FM-mono mode,

Threshold Comment

700 dec automatic switching with

set by
customer

i.e. automatic switching is
disabled

internal threshold

automatic switching with
external threshold

i.e. automatic switching is
disabled

23Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values

6.5.1. Register ‘AD_CV’

Table 6–5: AD_CV Register; reset status: all bits are “0”

AD_CV 00BB

hex

Set by Short-Programming

Bit Meaning Settings AD_CV-FM AD_CV-AM

AD_CV [0] not used must be set to 0 0 0

AD_CV [6:1] Reference level in case of Automat-

101000 100011
ic Gain Control = on (see Table
6–6). Constant gain factor when
Automatic Gain Control = off
(see Table 6–7).

AD_CV [7] Determination of Automatic Gain or

Constant Gain

0 = constant gain
1 = automatic gain

1 1

AD_CV [8] not used must be set to 0 not affected not affected

AD_CV [9] MSP-Carrier-Mute Function

(Must be switched off in
High Deviation Mode)

0 = off: no mute
1 = on: mute as
described in section

1 0

4.1.8. on page 12

AD_CV [15–10] not used must be set to 0 0 0

Table 6–6: Reference values for active AGC (AD_CV[7] = 1)

Application Input Signal Contains AD_CV [6:1]

Ref. Value

AD_CV [6:1]
in integer

Range of Input Signal
at pin ANA_IN1+
and ANA_IN2+

Terrestrial TV
FM-Stereo 2 FM Carriers 101000 40 0.10 – 3 V

FM/NICAM 1 FM and 1 NICAM Carrier 101000 40 0.10 – 3 V
AM/NICAM 1 AM and 1 NICAM carrier 100011 35 0.10 – 1.4 V

recommended:

0.10 – 0.8V

NICAM only 1 NICAM Carrier only 010100 20 0.05 – 1.0 V

SAT 1 or more

100011 35 0.10 – 3 V

pp

pp

pp

1)

1)

pp

pp

pp

1)

FM Carriers

1)

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result.
Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions
of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may ap­pear.

24 Micronas

PRELIMINARY DATA SHEET

Table 6–7: AD_CV parameters for constant input gain (AD_CV[7]=0)

MSP 34x5D

Step AD_CV [6:1]

Constant Gain

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1)

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result.
Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions
of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may
appear.

000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100

Gain (dB) Input Level at pin ANA_IN1+

3.00

3.85

4.70

5.55

6.40

7.25

8.10

8.95

9.80

10.65

11.50

12.35

13.20

14.05

14.90

15.75

16.60

17.45

18.30

19.15

20.00

maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)

maximum input level: 0.14 V

pp

1)

25Micronas

MSP 34x5D

6.5.2. Register ‘MODE_REG’

The register ‘MODE_REG’ contains the control bits de­termining the operation mode of the MSP 34x5D; Table
6–8 explains all bit positions.

Table 6–8: Control word ‘MODE_REG’; reset status: all bits are “0”

PRELIMINARY DATA SHEET

MODE_REG 0083

hex

Set by

Short-Programming

Bit Function Comment Definition M1 M2 M3

[0] not used 0 : strongly recommended 0 0 0

[1] DCTR_TRI Digital Control Outputs

active / tri-state

[2] I2S_TRI I2S Outputs (I2S_CL,

I2S_WS, I2S_DA_OUT)

0 : active
1 : tri-state

0 : active
1 : tri-state

X X X

X X X

active / tri-state

[3] I2S Mode

[4] I2S_WS Mode WS due to the Sony or

1)

Master / Slave Mode of

2

the I

S Bus

Philips format

0 : Master
1 : Slave

0 : Sony
1 : Philips

X X X

X X X

[5] not used 1 : recommended X X X

[6] NICAM

1)

Mode of MSP-Ch1
MSP 3405D: always FM

0 : FM
1 : Nicam

0 1 1

[7] not used 0 : strongly recommended 0 0 0

[8] FM AM Mode of MSP-Ch2 0 : FM

0 0 1

1 : AM

[9] HDEV High Deviation Mode

(channel matrix must be

0 : normal
1 : high deviation mode

0 0 0

sound A)

[11:10] not used 0 : strongly recommended 0 0 0

[12] MSP-Ch1 Gain see Table 6–11 0 : Gain = 6 dB

0 0 0

1 : Gain = 0 dB

[13] FIR1-Filter

Coeff. Set

see Table 6–11 0 : use FIR1

1 : use FIR2

1 0 0

[14] not used 0 : strongly recommended 0 0 0

[15] AM-Gain Gain for AM

Demodulation

1)

In case of NICAM operation, I2S slave mode is not possible.
In case of I

2

S slave mode, no synchronization to NICAM is allowed.

0 : 0 dB (default. of MSPB)
1 : 12 dB (recommended)

1 1 1

X: not affected by
short-programming

26 Micronas

PRELIMINARY DATA SHEET

f

MSP 3405D)

see Table 6–11

see Table 6–11

Table 6–9: Channel modes ‘MODE_REG [6, 8, 9]‘

MSP 34x5D

NICAM
bit[6]

1 0 0 NICAM (undefined sound

FM AM
bit[8]

HDEV
bit[9]

MSP-Ch1 MSP-Ch2

FM1

or

1 1 0

AM

0 0 0 FM2 FM1

0 0 1 – High Deviation FM

6.5.3. FIR-Parameter

The following data values (see Table 6–10) are to be
transferred 8 bits at a time embedded LSB-bound in
a 16-bit word.

The loading sequences must be obeyed. To change a
coefficient set, the complete block FIR1 or FIR2 must be
transmitted.

Table 6–10: Loading sequence for FIR-coefficients

FIR1 0001

No. Symbol Name Bits Value

1 NICAM/FM2_Coeff. (5) 8

2 NICAM/FM2_Coeff. (4) 8

3 NICAM/FM2_Coeff. (3) 8

(MSP-Ch1: NICAM/FM2)

hex

Note: For compatibility with MSP 3410B, IMREG1 and

IMREG2 have to be transmitted. The value for IMREG1

4 NICAM/FM2_Coeff. (2) 8

and IMREG2 is 004. Due to the partitioning to 8-bit units,
the values 04

hex

, 40

, and 00

hex

hex

arise.

5 NICAM/FM2_Coeff. (1) 8

6 NICAM/FM2_Coeff. (0) 8

FIR2 0005

No. Symbol Name Bits Value

1 IMREG1 8 04

2 IMREG1 / IMREG2 8 40

3 IMREG2 8 00

4 FM/AM_Coef (5) 8

5 FM/AM_Coef (4) 8

6 FM/AM_Coef (3) 8

7 FM/AM_Coef (2) 8

8 FM/AM_Coef (1) 8

9 FM/AM_Coef (0) 8

(MSP-Ch2: FM1/AM )

hex

hex

hex

hex

27Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

Table 6–11: 8-bit FIR-coefficients (decimal integer) for MSP 34x5D; reset status: all coefficients are “0”

Coefficients for FIR1 0001

B/G-, D/K­NICAM-FM

Coef(i) FIR1 FIR2 FIR1 FIR2 FIR1 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2

0 –2 3 2 3 –2 –4 3 73 9 3 –8 –1 –1 –1

1 –8 18 4 18 –8 –12 18 53 18 18 –8 –9 –1 –1

2 –10 27 –6 27 –10 –9 27 64 28 27 4 –16

3 10 48 –4 48 10 23 48 11 9 47 48 36 5 2 2

4 50 66 40 66 50 79 66 101 55 66 78 65 59 59

5 86 72 94 72 86 126 72 127 64 72 107 123 126 126

MODE­REG[12]

MODE­REG[13]

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 1 1 1 1 1 1 0

and FIR2 0005

hex

Terrestrial TV-Standards

I-

NICAM-FML-NICAM-AM

hex

B/G-,D/K-,
M-Dual FM

FM - Satellite

FIR filter corresponds to a
bandpass with a band­width of B = 130 to 500 kHz

130
kHz

180
kHz

200
kHz

280
kHz

380
kHz

B

c

500
kHz

–8

frequencyf

Auto­search

–8

For compatibility, except for the FIR2-AM and the autosearch sets, the FIR-filter programming as used for the MSP 3410B is also possible.

28 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

6.5.4. DCO-Registers

For a chosen TV standard, a corresponding set of 24-bit
registers determining the mixing frequencies of the
quadrature mixers, has to be written into the IC. In Table
6–12, some examples of DCO registers are listed. It is
necessary to divide them up into low part and high part.
The formula for the calculation of the registers for any
chosen IF-Frequency is as follows:

INCR

= int ( f / fs ⋅ 2

dec

24

)

with: int = integer function

f = IF-frequency in MHz
f

= sampling frequency (18.432 MHz)

S

Conversion of INCR into hex-format and separation of
the 12-bit low and high parts lead to the required register
values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI or LO
for MSP-Ch2).

6.6. Demodulator Read Registers:
Functions and Values

All registers except C_AD_BITs are 8 bit wide. They can
be read out of the RAM of the MSP 34x5D.

All transmissions take place in 16-bit words. The valid 8
bit data are the 8 LSBs of the received data word.

To enable appropriate switching of the channel select
matrix of the baseband processing part, the NICAM or
FM-identification parameters must be read and eva­luated by the CCU. The FM-identification registers are
described in section 7.2. To handle the NICAM-sound
and to observe the NICAM-quality, at least the registers
C_AD_BITS and ERROR_RATE must be read and eva­luated by the CCU. Additional data bits and CIB bits, if
supplied by the NICAM transmitter, can be obtained by
reading the registers ADD_BITS and CIB_BITS.

Observing the presence and quality of NICAM can be
delegated to the MSP 34x5D, if the automatic switching
feature (AUTO_FM, section 6.4.2.) is applied.

Table 6–12: DCO registers for the MSP 34x5D; reset status: DCO_HI/LO = ”0000”

Freq.
[MHz]

DCO1_LO 0093

DCO_HI

hex

, DCO1_HI 009B

hex

DCO_LO

hex

; DCO2_LO 00A3

hex

Freq.
[MHz]

, DCO2_HI 00AB

hex

DCO_HI

hex

4.5 03E8 000

5.04

5.5

5.58

5.7421875

6.0

6.2

6.5

6.552

0460
04C6
04D8
04FC

0535
0561
05A4
05B0

0000
038E
0000
00AA

0555
0C71
071C
0000

5.76

5.85

5.94

6.6

6.65

6.8

0500
0514
0528

05BA
05C5
05E7

7.02 0618 0000 7.2 0640 0000

7.38 0668 0000 7.56 0690 0000

hex

DCO_LO

0000
0000
0000

0AAA
0C71
01C7

hex

29Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

6.6.1. Autodetect of Terrestrial TV-Audio Standards

By means of autodetect, the MSP 34x5D offers a simple
and fast (<0.5 s) facility to detect the actual TV-audio
standard. The algorithm checks for the FM-mono and
NICAM carriers of all common TV-Sound Standards.
The following notes must be considered when applying
the autodetect feature:

1. Since there is no way to distinguish between AM and
FM-carrier, a carrier detected at 6.5 MHz is inter­preted as an AM-carrier. If video detection results in
SECAM-East, the MSPD result “9” of autodetect must
be reinterpreted as “B

” in case of CAD_BITS[0] =

hex

1, or as “4” or “5” by using the demodulator short pro­gramming mode. A simple decision can be made be­tween the two D/K FM-stereo standards by setting
D/K1 and D/K2 using the short programming mode
and checking the identification of both versions (see
Table 6–13).

2. During active autodetect, I

2

C-transfers are not rec­ommended except for reading the autodetect result.
Under no circumstances should the following param­eters: Prescale FM/AM, FM Matrix, Deemphasis FM,
Quasi-Peak Detector Source, and Quasi-Peak De­tector Matrix be written. Results exceeding 07FF

hex

indicate an active autodetect.

3. The results are to be understood as static information,
i.e. no evaluation of FM or NICAM identification con­cerning the dynamic mode (stereo, bilingual, or
mono) are done.

4. Before switching to autodetect, the audio processing
part should be muted. Do not forget to demute after
having received the result.

Table 6–13: Result of Autodetection

Result of Autodetect 007E

hex

Code Detected TV-Sound Standard
(Data) hex Note: After detection the detected standard is set automatically according to Table 6–3.

>07FF autodetect still active

0000 no TV Sound Standard was detected; select sound standard manually

0002 M Dual-FM, even if only FM1 is available

0003 B/G Dual-FM, even if only FM1 is available

0008 B/G-FM-NICAM, only if NICAM is available (MSP 3415D only)

L_AM-NICAM, whenever a 6.5 MHz carrier is detected, even if NICAM is not available.
If also D/K might be possible a decision has to be made according to the video-mode:

Video = SECAM_EAST

0009

Video = SECAM_L → no more activities nec-

essary

CAD_BITS[0] = 0 CAD_BITS[0] = 1

To be set by means of the
short programming mode:

D/K1 or D/K2
see section 6.6.1.

D/K-NICAM
(standard 000B

hex

)

000A I-FM-NICAM, even if NICAM is not available

Note: Similar as for the Demodulator Short-Programming, the Autodetection does not affect most of the pa­rameters of the DSP section (Audio Baseband Processing): The following exceptions are to be considered:
– identification mode: Autodetection resets and sets the corresponding identification mode.
– Prescale FM/AM and FM matrix and Deemphasis FM are undefined after Autodetection.

30 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

6.6.2. C_AD_BITS (MSP 3415D only)

NICAM operation mode control bits and A[2...0] of the
additional data bits.

Format:

MSB C_AD_BITS 0023

11 ... 7 6 5 4 3 2 1 0

Auto
_FM

... A[2] A[1] A[0] C4 C3 C2 C1 S

hex

LSB

Important: “S” = Bit [0] indicates correct NICAM-syn-

chronization (S=1). If S = 0, the MSP 34x5D has not yet
synchronized correctly to frame and sequence, or has
lost synchronization. The remaining read registers are
therefore not valid. The MSP 34x5D mutes the NICAM
output automatically and tries to synchronize again as
long as MODE_REG[6] is set.

The operation mode is coded by C4-C1 as shown in
Table 6–14.

Table 6–14: NICAM operation modes as defined by the
EBU NICAM 728 specification

6.6.3. ADD_BITS [10...3] (MSP 3415D only)

Contains the remaining 8 of the 11 additional data bits.
The additional data bits are not yet defined by the NI­CAM 728 system.

Format:

MSB ADD_BITS 0038

7 6 5 4 3 2 1 0

A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3]

hex

LSB

6.6.4. CIB_BITS (MSP 3415D only)

Cib bits 1 and 2 (see NICAM 728 specifications)

Format:

MSB CIB_BITS 003E

7 6 5 4 3 2 1 0

x x x x x x CIB1 CIB2

hex

LSB

C4 C3 C2 C1 Operation Mode

0 0 0 0 Stereo sound (NICAMA/B),

independent mono sound (FM1)

0 0 0 1 Two independent mono signals

(NICAMA, FM1)

0 0 1 0 Three independent mono channels

(NICAMA, NICAMB, FM1)

0 0 1 1 Data transmission only; no audio

1 0 0 0 Stereo sound (NICAMA/B), FM1 car-

ries same channel

1 0 0 1 One mono signal (NICAMA). FM1

carries same channel as NICAMA

1 0 1 0 Two independent mono channels

(NICAMA, NICAMB). FM1 carries
same channel as NICAMA

1 0 1 1 Data transmission only; no audio

x 1 x x Unimplemented sound coding option

(not yet defined by EBU NICAM 728
specification)

6.6.5. ERROR_RATE (MSP 3415D only)

Average error rate of the NICAM reception in a time in­terval of 182 ms, which should be close to 0.. The initial
and maximum value of ERROR_RATE is 2047. This val­ue is also active, if the NICAM bit of MODE_REG is not
set. Since the value is achieved by filtering, a certain
transition time (appr. 0.5 sec) is unavoidable. Accept­able audio may have error_rates up to a value of 700int.
Individual evaluation of this value by the CCU and an ap­propriate threshold may define the fallback mode from
NICAM to FM/AM-mono in case of poor NICAM recep­tion.

The bit error rate per second (BER) can be calculated by
means of the following formula:

BER = ERROR_RATE * 12.3*10

–6

/s

If the automatic switching feature (AUTO_FM; section

6.4.2. on page 23) is applied, reading of ERROR_RATE
can be omitted.

ERROR_RATE 0057

hex

AUTO_FM: monitor bit for the AUTO_FM Status:
0: NICAM source is NICAM
1: NICAM source is FM

Error free 0000

maximum error rate 07FF

hex

hex

31Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

6.6.6. CONC_CT (for compatibility with MSP 3410B)

This register contains the actual number of bit errors of
the previous 728-bit data frame. Evaluation of
CONC_CT is no longer recommended.

6.6.7. FAWCT_IST (for compatibility with MSP3410B)

For compatibility with MSP 3410B this value equals 12
as long as NICAM quality is sufficient. It decreases to 0
if NICAM reception gets poor. Evaluation of FAWCT_IST
is no longer recommended.

6.6.8. PLL_CAPS

It is possible to read out the actual setting of the
PLL_CAPS. In standard applications, this register is not
of interest for the customer.

PLL_CAPS 0021F

minimum frequency 0111 1111 7F

nominal frequency 0101 0110 56

hex

hex

hex

RESET

6.7. Sequences to Transmit Parameters

and to Start Processing

After having been switched on, the MSP has to be initial­ized by transmitting the parameters according to the
LOAD_SEQ_1/2 of Table 6–15. The data are immedi­ately active after transmission into the MSP. It is no long­er necessary to transmit LOAD_REG_1/2 or
LOAD_REG_1 as it was for MSP 3410B. Nevertheless,
transmission of LOAD_REG_1/2 or LOAD_REG_1
does no harm.

For NICAM operation, the following steps listed in ‘NI­CAM_WAIT, _READ and _Check’ in Table 6–15 must be
taken.

For FM-stereo operation, the evaluation of the identifica­tion signal must be performed. For a positive identifica­tion check, the MSP 34x5D sound channels have to be
switched corresponding to the detected operation
mode.

maximum frequency 0000 0000 00

hex

6.6.9. AGC_GAIN

It is possible to read out the actual setting of AGC_GAIN
in Automatic Gain Mode. In standard applications, this
register is not of interest for the customer.

AGC_GAIN 0021E

max. amplification

hex

0001 0100 14

hex

(20 dB)

min. amplification

0000 0000 00

hex

(3 dB)

32 Micronas

PRELIMINARY DATA SHEET

Table 6–15: Sequences to initialize and start the MSP 34x5D

LOAD_SEQ_1/2: General Initialization

General Programming Mode Demodulator Short Programming

Write into MSP 34x5D: Write into MSP 34x5D:

1. AD_CV

2. FIR1

3. FIR2

4. MODE_REG

5. DCO1_LO

6. DCO1_HI

7. DCO2_LO

8. DCO2_HI

AUDIO PROCESSING INIT

Initialization of Audio Baseband Processing section, which may be customer dependant (see section 7.).

NICAM_WAIT: Automatic Start of the NICAM-Decoder if Bit[6] of MODE_REG is set to 1

1. Wait at least 0.25 s

For example: Addr: 0020
Alternatively, for terrestrial reception, the autodetect feature
can be applied.

, Data 0008

hex

MSP 34x5D

hex

NICAM_CHECK: Read NICAM specific information and check for presence, operation mode, and quality of NICAM signal.
DO NOT read and DO NOT evaluate Stereo Detection register.

Read out of MSP 34x5D (For MSP 3405D, all NICAM read registers contain “0”):

1. C_AD_BITS

2. CONC_CT or ERROR_RATE; if AUTO_FM is active, reading of CONC_CT or ERROR_RATE can be omitted.

Evaluation of C_AD_BITS and CONC_CT or ERROR_RATE in the CCU (see section 6.6.).
If necessary, switch the corresponding sound channels within the audio baseband processing section.

FM_WAIT: Automatic start of the FM-identification process if Bit[6] of MODE_REG is set to 0.

1. Ident Reset

2. Wait at least 0.5 s

FM_IDENT_CHECK: Read Stereo Detection register and check for operation mode of dual carrier FM.
DO NOT read and DO NOT evaluate NICAM specific information.

Read out of MSP 34x5D:

1. Stereo Detection register (DSP register 0018

Evaluation of the Stereo Detection register (see section 7.5.1.)
If necessary, switch the corresponding sound channels within the audio baseband processing section.

LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2

Write into MSP 34x5D: Write into MSP 34x5D:

1. FIR1 (6 ⋅ 8 bit)

2. MODE_REG (12 bit)

3. DCO1_LO (12 bit)

4. DCO1_HI

, high part)

hex

For example: Addr: 0020

, Data: 0003

hex

hex

PAUSE: Duration of “Pause” determines the repetition rate of the NICAM or the FM_IDENT-check.

33Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

6.8. Software Proposals for Multistandard TV-Sets

To familiarize the reader with the programming scheme
of the MSP 34x5D demodulator part, three examples in
the shape of flow diagrams are shown in the following
sections.

6.8.1. Multistandard Including System
B/G or I (NICAM/FM-Mono only) or
SECAM L (NICAM/AM-Mono only)

Fig. 6–1 shows a flow diagram for the CCU software,
applied for the MSP 34x5D in a TV set, which facilitates
NICAM and FM/AM-mono sound. For the instructions,
please refer to Table 6–15.

If the program is changed, resulting in another program
within the same TV-sound system, no parameters of the
MSP 34x5D need be modified. To facilitate the check for
NICAM, the CCU has only to continue at the ’NI­CAM_WAIT’ instruction. During the NICAM-identifica­tion process, the MSP 34x5D must be switched to the
FM-mono sound.

6.8.2. Multistandard Including System B/G
with NICAM/FM-Mono and German DUAL FM

Fig. 6–3 shows a flow diagram for the CCU software,
applied for the MSP 34x5D in a TV set, which supports
all standards according to System B/G. For the instruc­tions used in the diagram, please refer to Table 6–15.

After having switched on the TV-set and having initial­ized the MSP 34x5D (LOAD_SEQ_1/2), FM-mono
sound is available.

Fig. 6–3 shows that to check for any stereo or bilingual
audio information, the sound standards 0008
NICAM) and 0003

must simply be set alternately. If

hex

hex

(B/G-

successful, the MSP 3415D must switch to the desired
audio mode.

6.8.3. Satellite Mode

Fig. 6–2 shows the simple flow diagram to be used for
the MSP 34x5D in a satellite receiver. For FM-mono op­eration, the corresponding FM carrier should preferably
be processed at the MSP-channel 2.

START

LOAD_SEQ_1/2

Set Sound Standard

0008

hex

Alternatively:

0009

Audio Processing Init

NICAM_CHECKPause

000A

hex

NICAM_WAIT

hex

Fig. 6–1: CCU software flow diagram for NICAM/FM
or AM mono with Demodulator Short Programming

START

MSP-Channel 1
FM2-Parameter

MSP-Channel 2
FM1-Parameter

Audio Processing

Init

STOP

Fig. 6–2: CCU software flow diagram: SAT-mode

6.8.4. Automatic Search Function
for FM-Carrier Detection

The AM demodulation ability of the MSP 34x5D offers
the possibility to calculate the “field strength” of the mo­mentarily selected FM carrier, which can be read out by
the CCU. In SAT receivers, this feature can be used to
make automatic FM carrier search possible.

Therefore, the MSPD has to be switched to AM-mode
(MODE_REG[8]), FM-Prescale must be set to
7F

hex

= +127

, and the FM DC notch must be

dec

switched off. The sound-IF frequency range must now
be “scanned” in the MSPD-channel 2 by means of the
programmable quadrature mixer with an appropriate in­cremental frequency (i.e. 10 kHz).

34 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

Pause

LOAD_SEQ_1/2

Sound Standard

Audio Processing

NICAM_WAIT

Yes

NICAM_CHECK

LOAD_SEQ_1

Sound Standard

START

Set

0008

hex

Init

NICAM

?

Set

0003

hex

No

After each incrementation, a field strength value is avail­able at the quasi-peak detector output (quasi-peak de­tector source must be set to FM), which must be ex­amined for relative maxima by the CCU. This results in
either continuing search or switching the MSP 34x5D
back to FM demodulation mode.

During the search process, the FIR2 must be loaded
with the coefficient set “AUTOSEARCH”, which enables
small bandwidth, resulting in appropriate field strength
characteristics. The absolute field strength value (can
be read out of “quasi peak detector output FM1”) also
gives information on whether a main FM carrier or a sub­carrier was detected, and as a practical consequence,
the FM bandwidth (FIR1/2) and the deemphasis (50 µs
or adaptive) can be switched automatically.

Due to the fact that a constant demodulation frequency
offset of a few kHz, leads to a DC-level in the demodu­lated signal, further fine tuning of the found carrier can
be achieved by evaluating the “DC Level Readout FM1”.
Therefore, the FM DC Notch must be switched on, and
the demodulator part must be switched back to FM-de­modulation mode.

For a detailed description of the automatic search func­tion, please refer to the corresponding MSP 3400C Win­dows software.

FM_WAIT

Pause

FM_

Stereo/Biling.

IDENT_CHECK

Mono

LOAD_SEQ_1

Set

Sound Standard

0008

hex

Fig. 6–3: CCU software flow diagram: standard B/G
with NICAM or FM stereo with Demodulator Short
Programming Mode

Note: The automatic search is still possible by evaluat­ing only the DC Level Readout FM1 (DC Notch On) as
it is described with the MSP 3410B, but the above men­tioned method is faster. If this DC Level method is ap­plied with the MSP 34x5D, it is recommended to set
MODE_REG[15] to 1 (AM-Gain= 12 dB) and to use the
new Autosearch FIR2 coefficient set as given in Table
6–11.

35Micronas

MSP 34x5D

É

É

É

É

É

7. Programming the DSP Section (Audio Baseband Processing)

7.1. DSP Write Registers: Table and Addresses

PRELIMINARY DATA SHEET

Table 7–1: DSP Write Registers; Subaddress: 12

DSP Write Register Address High/

; if necessary these registers are readable as well.

hex

Adjustable Range, Operational Modes Reset Mode

Low

Volume loudspeaker channel 0000

Volume / Mode loudspeaker channel L 1/8 dB Steps, Reduce Volume / Tone Control 00

Balance loudspeaker channel [L/R] 0001

H [+12 dB ... –114 dB, MUTE] MUTE

hex

H [0..100 / 100 % and vv][–127..0 / 0 dB and vv]

hex

hex

100%/100%

Balance Mode loudspeaker L [Linear mode / logarithmic mode] linear mode

Bass loudspeaker channel 0002

Treble loudspeaker channel 0003

Loudness loudspeaker channel 0004

Loudness Filter Characteristic

Spatial effect strength loudspeaker ch. 0005

H [+12 dB ... –12 dB] 0 dB

hex

H [+12 dB ... –12 dB] 0 dB

hex

H [0 dB ... +17 dB] 0 dB

hex

L [NORMAL, SUPER_BASS] NORMAL

H [–100%...OFF...+100%] OFF

hex

Spatial effect mode/customize L [SBE, SBE+PSE] SBE+PSE

Volume SCART1 channel 0007

hex

H [00

hex

... 7F

],[+12 dB ... –114 dB, MUTE] 00

hex

hex

Volume / Mode SCART1 channel L [Linear mode / logarithmic mode] linear mode

Loudspeaker channel source 0008

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

Loudspeaker channel matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA

SCART1 channel source 000A

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

SCART1 channel matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA

I2S channel source 000B

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

I2S channel matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA

Quasi-peak detector source

ЙЙЙЙЙЙЙЙЙЙ

000C

hex

ÉÉ

H

É

[FM/AM, NICAM, SCART, I2S1, I2S2]

ЙЙЙЙЙЙЙЙЙЙЙЙ

FM/AM

ÉÉÉÉ

Quasi-peak detector matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA

Prescale SCART 000D

Prescale FM/AM 000E

hex

hex

H [00

H [00

hex

hex

... 7F

... 7F

] 00

hex

] 00

hex

hex

hex

FM matrix L [NO_MAT, GSTEREO, KSTEREO] NO_MAT

Deemphasis FM 000F

H [OFF, 50 µs, 75 µs, J17] 50 µs

hex

Adaptive Deemphasis FM L [OFF, WP1] OFF

Prescale NICAM (MSP 3415D only) 0010

Prescale I2S2 0012

ACB Register (SCART Switching

0013

H [00

hex

H [00

hex

H/L Bits [15..0] 00

hex

hex

hex

... 7F

... 7F

] 00

hex

] 10

hex

hex

hex

hex

Facilities)

Beeper 0014

Identification Mode 0015

Prescale I2S1 0016

FM DC Notch 0017

Automatic Volume Correction 0029

H/L [00

hex

L [B/G, M] B/G

hex

H [00

hex

L [ON, OFF] ON

hex

H [off, on, decay time] OFF

hex

hex

hex

... 7F

... 7F

]/[00

hex

hex

... 7F

hex

] 10

] 0/0

hex

hex

36 Micronas

PRELIMINARY DATA SHEET

7.2. DSP Read Registers: Table and Addresses

MSP 34x5D

Table 7–2: DSP Read Registers; Subaddress: 13

; these registers are not writable

hex

DSP Read Register Address High/Low Output Range

Stereo detection register 0018

Quasi peak readout left 0019

Quasi peak readout right 001A

DC level readout FM1/Ch2-L 001B

DC level readout FM2/Ch1-R 001C

MSP hardware version code 001E

MSP major revision code 001E

MSP product code 001F

MSP ROM version code 001F

hex

hex

hex

hex

hex

hex

hex

hex

hex

H [80

H & L [00

H & L [00

hex

hex

hex

H & L [8000

H & L [8000

H [00

L [00

H [05

L [00

hex

hex

hex

hex

... 7F

... 7FFF

... 7FFF

... 7FFF

hex

... 7FFF

hex

... FF

... FF

, 0F

... FF

] 8 bit two’s complement

hex

] 16 bit two’s complement

hex

] 16 bit two’s complement

hex

] 16 bit two’s complement

hex

] 16 bit two’s complement

hex

]

hex

]

hex

]

hex

]

hex

37Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

7.3. DSP Write Registers: Functions and Values

Write registers are 16 bit wide, whereby the MSB is de-

2

noted bit [15]. Transmissions via I

C bus have to take
place in 16-bit words. Some of the defined 16-bit words
are divided into low [7..0] and high [15..8] byte, or in an
other manner, thus holding two different control entities.
All write registers are readable. Unused parts of the
16-bit registers must be zero. Addresses not given in this
table must not be written at any time!

7.3.1. Volume Loudspeaker Channel

Volume

0000

hex

[15..4]

Loudspeaker

+12 dB 0111 1111 0000 7F0

+11.875 dB 0111 1110 1110 7EE

+0.125 dB 0111 0011 0010 732

0 dB 0111 0011 0000 730

–0.125 dB 0111 0010 1110 72E

hex

hex

hex

hex

hex

Clipping Mode

0000

hex

[3..0]

Loudspeaker

Reduce Volume 0000 0

hex

RESET

Reduce Tone Control 0001 1

Compromise Mode 0010 2

hex

hex

If the clipping mode is set to “Reduce Volume”, the fol­lowing clipping procedure is used: To prevent severe
clipping effects with bass or treble boosts, the internal
volume is automatically limited to a level where, in com­bination with either bass or treble setting, the amplifica­tion does not exceed 12 dB.

If the clipping mode is “Reduce Tone Control”, the bass
or treble value is reduced if amplification exceeds 12 dB.

If the clipping mode is “Compromise Mode”, the bass or
treble value and volume are reduced half and half if am­plification exceeds 12 dB.

–113.875 dB 0000 0001 0010 012

–114 dB 0000 0001 0000 010

Mute 0000 0000 0000 000

hex

hex

hex

RESET

Fast Mute 1111 1111 1110 FFE

The highest given positive 8-bit number (7F

) yields in

hex

hex

a maximum possible gain of 12 dB. Decreasing the vol­ume register by 1 LSB decreases the volume by 1 dB.
Volume settings lower than the given minimum mute the
output. With large scale input signals, positive volume
settings may lead to signal clipping.

The MSP 34x5D loudspeaker volume function is divided
up in a digital and an analog section.

With Fast Mute, volume is reduced to mute position by
digital volume only. Analog volume is not changed. This
reduces any audible DC plops. Going back from Fast
Mute should be done to the volume step before Fast
Mute was activated.

The Fast Mute facility is activated by the I

2

C command.
After 75 ms (typically), the signal is completely ramped
down.

Example: Vol.:

+6 dB

Bass:
+9 dB

Red. Volume 3 9 5

Red. Tone Con. 6 6 5

Compromise 4.5 7.5 5

Treble:
+5 dB

38 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

7.3.2. Balance Loudspeaker Channel

Positive balance settings reduce the left channel without
affecting the right channel; negative settings reduce the
right channel leaving the left channel unaffected. In lin­ear mode, a step by 1 LSB decreases or increases the
balance by about 0.8% (exact figure: 100/127). In loga­rithmic mode, a step by 1 LSB decreases or increases
the balance by 1 dB.

Balance Mode

0001

hex

[3..0]

Loudspeaker

linear 0000 0

hex

RESET

logarithmic 0001 1

hex

Linear Mode

Balance Loudspeaker

0001

hex

H

Channel [L/R]

Left muted, Right 100% 0111 1111 7F

Left 0.8%, Right 100% 0111 1110 7E

Left 99.2%, Right 100% 0000 0001 01

hex

hex

hex

7.3.3. Bass Loudspeaker Channel

Bass Loudspeaker 0002

hex

+20 dB 0111 1111 7F

+18 dB 0111 1000 78

+16 dB 0111 0000 70

+14 dB 0110 1000 68

+12 dB 0110 0000 60

+11 dB 0101 1000 58

+1 dB 0000 1000 08

+1/8 dB 0000 0001 01

0 dB 0000 0000 00

RESET

–1/8 dB 1111 1111 FF

–1 dB 1111 1000 F8

–11 dB 1010 1000 A8

–12 dB 1010 0000 A0

H

hex

hex

hex

hex

hex

hex

hex

hex

hex

hex

hex

hex

hex

Left 100%, Right 100% 0000 0000 00

RESET

Left 100%, Right 99.2% 1111 1111 FF

Left 100%, Right 0.8% 1000 0010 82

Left 100%, Right muted 1000 0001 81

Logarithmic Mode

Balance Loudspeaker

0001

hex

H

Channel [L/R]

Left –127 dB, Right 0 dB 0111 1111 7F

Left –126 dB, Right 0 dB 0111 1110 7 E

Left –1 dB, Right 0 dB 0000 0001 01

Left 0 dB, Right 0 dB 0000 0000 00

RESET

Left 0 dB, Right –1 dB 1111 1111 FF

Left 0 dB, Right –127 dB 1000 0001 81

hex

hex

hex

hex

hex

hex

hex

hex

hex

hex

With positive bass settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recom­mended to set bass to a value that, in conjunction with
volume, would result in an overall positive gain.

Left 0 dB, Right –128 dB 1000 0000 80

hex

39Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

7.3.4. Treble Loudspeaker Channel

Treble Loudspeaker 0003

hex

+15 dB 0111 1000 78

+14 dB 0111 0000 70

+1 dB 0000 1000 08

+1/8 dB 0000 0001 01

0 dB 0000 0000 00

H

hex

hex

hex

hex

hex

RESET

–1/8 dB 1111 1111 FF

–1 dB 1111 1000 F8

–11 dB 1010 1000 A8

–12 dB 1010 0000 A0

hex

hex

hex

hex

With positive treble settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recom­mended to set treble to a value that, in conjunction with
volume, would result in an overall positive gain.

to set loudness to a value that, in conjunction with vol­ume, would result in an overall positive gain.

By means of ‘Mode Loudness’, the corner frequency for
bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up.
The point of constant volume is shifted from 1 kHz to
2 kHz.

7.3.6. Spatial Effects Loudspeaker Channel

Spatial Effect Strength

0005

hex

H

Loudspeaker

Enlargement 100% 0111 1111 7F

Enlargement 50% 0011 1111 3 F

Enlargement 1.5% 0000 0001 01

Effect off 0000 0000 00

hex

hex

hex

hex

RESET

Reduction 1.5% 1111 1111 FF

Reduction 50% 1100 0000 C0

hex

hex

7.3.5. Loudness Loudspeaker Channel

Loudness

0004

hex

Loudspeaker

+17 dB 0100 0100 44

+16 dB 0100 0000 40

+1 dB 0000 0100 04

0 dB 0000 0000 00

RESET

Mode Loudness

0004

hex

Loudspeaker

Normal (constant
volume at 1 kHz)

Super Bass (constant

0000 0000 00
RESET

0000 0100 04

volume at 2 kHz)

Reduction 100% 1000 0000 80

Spatial Effect Mode

H

Loudspeaker

Stereo Basewidth En-

hex

hex

hex

hex

largement (SBE) and
Pseudo Stereo Effect
(PSE). (Mode A)

Stereo Basewidth En­largement (SBE) only.
(Mode B)

Spatial Effect Cus-

L

hex

hex

tomize Coefficient
Loudspeaker

max high pass gain 0000 0

2/3 high pass gain 0010 2

0005

hex

0000 0
RESET
0000 0

0010 2

0005

hex

RESET

1/3 high pass gain 0100 4

hex

[7:4]

hex

hex

hex

[3:0]

hex

hex

hex

Loudness increases the volume of low and high frequen­cy signals, while keeping the amplitude of the 1 kHz ref-

min high pass gain 0110 6

automatic 1000 8

hex

hex

erence frequency constant. The intended loudness has
to be set according to the actual volume setting. Be­cause loudness introduces gain, it is not recommended

40 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

There are several spatial effect modes available:

Mode A (low byte = 00

) is compatible to the formerly

hex

used spatial effect. Here, the kind of spatial effect de­pends on the source mode. If the incoming signal is in
mono mode, Pseudo Stereo Effect is active; for stereo
signals, Pseudo Stereo Effect and Stereo Basewidth
Enlargement is effective. The strength of the effect is
controllable by the upper byte. A negative value reduces
the stereo image. A rather strong spatial effect is recom­mended for small TV sets where loudspeaker spacing is
rather close. For large screen TV sets, a more moderate
spatial effect is recommended. In mode A, even in case
of stereo input signals, Pseudo Stereo Effect is active,
which reduces the center image.

In Mode B, only Stereo Basewidth Enlargement is effec­tive. For mono input signals, the Pseudo Stereo Effect
has to be switched on.

It is worth mentioning, that all spatial effects affect ampli­tude and phase response. With the lower 4 bits, the fre­quency response can be customized. A value of 0000

bin

yields a flat response for center signals (L = R) but a high
pass function of L or R only signals. A value of 0110

bin

has a flat response for L or R only signals but a lowpass
function for center signals. By using 1000

, the fre-

bin

quency response is automatically adapted to the sound
material by choosing an optimal high pass gain.

Logarithmic Mode

Volume SCART1 0007

hex

+12 dB 0111 1111 0000 7F0

+11.875 dB 0111 1110 1110 7EE

+0.125 dB 0111 0011 0010 732

0 dB 0111 0011 0000 730

–0.125 dB 0111 0010 1110 72E

–113.875 dB 0000 0001 0010 012

–114 dB 0000 0001 0000 010

Mute 0000 0000 0000 000

RESET

7.3.8. Channel Source Modes

Loudspeaker Source 0008

SCART1 Source 000A

I2S Source 000B

Quasi-Peak

000C

hex

hex

hex

hex

Detector Source

[15..4]

hex

hex

hex

hex

hex

hex

hex

hex

H

H

H

H

7.3.7. Volume SCART1

Volume Mode SCART1 0007

hex

linear 0000 0

RESET

logarithmic 0001 1

Linear Mode

Volume SCART1 0007

hex

OFF 0000 0000 00

RESET

0 dB gain

0100 0000 40

(digital full scale (FS)

RMS

RMS

output)

0111 1111 7F

output)

to 2 V

+6 dB gain (–6 dBFS
to 2 V

[3..0]

H

hex

hex

hex

hex

hex

FM/AM 0000 0000 00

RESET

NICAM (MSP 3415D only) 0000 0001 01

SCART 0000 0010 02

I2S1 0000 0101 05

I2S2 0000 0110 06

7.3.9. Channel Matrix Modes

Loudspeaker Matrix 0008

SCART1 Matrix 000A

I2S Matrix 000B

Quasi-Peak

000C

hex

hex

hex

hex

Detector Matrix

SOUNDA / LEFT /
MSP-IF-CHANNEL2

SOUNDB / RIGHT /

0000 0000 00
RESET

0001 0000 10

MSP-IF-CHANNEL1

hex

hex

hex

hex

hex

L

L

L

L

hex

hex

STEREO 0010 0000 20

MONO 0011 0000 30

hex

hex

41Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

7.3.10. SCART Prescale

Volume Prescale

000D

hex

H

SCART

OFF 0000 0000 00

hex

RESET

0 dB gain (2 V

RMS

in-

0001 1001 19

hex

put to digital full scale)

+14 dB gain
(400 mV

RMS

input to

0111 1111 7F

hex

digital full scale)

Comments for the FM/AM-Prescaling:

For the High Deviation Mode, the FM prescaling values
can be used in the range from 13

hex

to 30

. Please

hex

consider the internal reduction of 6 dB for this mode. The
FIR-bandwidth should be selected to 500 kHz.

1)

Given deviations will result in internal digital full scale
signals. Appropriate clipping headroom has to be set by
the customer. This can be done by decreasing the listed
values by a specific factor.

2)

In the mentioned SIF-level range, the AM-output level
remains stable and independent of the actual SIF-level.
In this case, only the AM degree of audio signals above
40 Hz determines the AM-output level.

7.3.11. FM/AM Prescale

Volume Prescale FM

000E

hex

(Normal FM Mode)

OFF 0000 0000 00

RESET

Maximum Volume
(28 kHz deviation

1)

0111 1111 7F

recommended FIR­bandwidth: 130 kHz)

Deviation 50 kHz

1)

0100 1000 48
recommended FIR­bandwidth: 200 kHz

Deviation 75 kHz

1)

0011 0000 30
recommended FIR­bandwidth: 200 or
280 kHz

Deviation 150 kHz

1)

0001 1000 18
recommended FIR­bandwidth: 380 kHz

Maximum deviation

1)

192 kHz

0001 0011 13

recommended FIR­bandwidth: 380 kHz

Prescale for adaptive

0001 0000 10
deemphasis WP1
recommended FIR­bandwidth: 130 kHz

H

hex

hex

hex

hex

hex

hex

hex

Volume Prescale FM

000E

hex

H

(High Dev.- Mode)

OFF 0000 0000 00

hex

RESET

Deviation 150 kHz

1)

0011 0000 30

hex

recommended FIR­bandwidth: 380 kHz

Maximum deviation

1)

384 kHz

0001 0100 14

hex

recommended FIR­bandwidth: 500 kHz

Volume Prescale AM 000E

hex

OFF 0000 0000 00

H

hex

RESET

SIF input level:

1) 2)

0.1 Vpp – 0.8 Vpp

0.8 Vpp – 1.4 Vpp

1)

0111 1100 7C

<7C

hex

hex

Note: For AM, the bit MODE_REG[15] must be 1.

42 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

7.3.12. FM Matrix Modes

FM Matrix 000E

hex

NO MATRIX 0000 0000 00

L

hex

RESET

GSTEREO 0000 0001 01

KSTEREO 0000 0010 02

hex

hex

NO_MATRIX is used for terrestrial mono or satellite ste­reo sound. GSTEREO dematrixes [(L+R)/2, R] to [L, R]
and is used for German dual carrier stereo system
(Standard B/G). KSTEREO dematrixes [(L+R)/2,
(L–R)/2] to [L, R] and is used for the Korean dual carrier
stereo system (Standard M).

7.3.13. FM Fixed Deemphasis

Deemphasis FM 000F

hex

50 µs 0000 0000 00

H

hex

RESET

75 µs 0000 0001 01

J17 0000 0100 04

OFF 0011 1111 3 F

hex

hex

hex

7.3.17. I

2

S1 and I2S2 Prescale

Prescale I2S1 0016

Prescale I2S2 0012

hex

hex

H

H

OFF 0000 0000 00

0 dB gain 0001 0000 10

RESET

+18 dB gain 0111 1111 7F

7.3.18. ACB Register (see Fig. 4–3); [15:14] = 0 !

Definition of Digital Control Output Pins

ACB Register 0013

hex

[15..14]

D_CTR_OUT0

low (RESET)
high

x0
x1

D_CTR_OUT1

low (RESET)
high

0x
1x

hex

hex

hex

7.3.14. FM Adaptive Deemphasis

FM Adaptive

000F

hex

Deemphasis WP1

OFF 0000 0000 00

RESET

WP1 0011 1111 3F

7.3.15. NICAM Prescale (MSP 3415D only)

Volume Prescale

0010

hex

NICAM

OFF 0000 0000 00

RESET

0 dB gain 0010 0000 20

+12 dB gain 0111 1111 7F

Definition of SCART Switching Facilities

L

ACB Register 0013

[13..0]

hex

DSP IN

Selection of Source:

hex

hex

* SC1_IN_L/R

MONO_IN
SC2_IN_L/R
Mute

xx xx00 xx00 0000
xx xx01 xx00 0000
xx xx10 xx00 0000
xx xx11 xx10 0000

SC1_OUT_L/R

Selection of Source:

SC2_IN_L/R
MONO_IN

H

SCART1 via D/A
SC1_IN_L/R
Mute

hex

xx 01xx x0x0 0000
xx 10xx x0x0 0000
xx 11xx x0x0 0000
xx 01xx x1x0 0000
xx 11xx x1x0 0000

* = RESET position, which becomes active at the
time of the first write transmission on the control

hex

bus to the audio processing part (DSP). By writing
to the ACB register first, the RESET state can be

hex

redefined.

Note: After RESET, SC1_OUT_L/R is undefined!

7.3.16. NICAM Deemphasis (MSP 3415D only)

A J17 Deemphasis is always applied to the NICAM sig­nal. It is not switchable.

Note: If “MONO_IN” is selected at the DSP_IN selec­tion, the channel matrix mode of the corresponding out­put channel(s) must be set to “sound A”.

43Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

7.3.19. Beeper

Beeper Volume 0014

hex

OFF 0000 0000 00

H

hex

RESET

Maximum Volume (full

0111 1111 7F

hex

digital scale FDS)

Beeper Frequency 0014

hex

16 Hz (lowest) 0000 0001 01

1 kHz 0100 0000 40

4 kHz (highest) 1111 1111 FF

L

hex

hex

hex

A squarewave beeper can be added to the loudspeaker
channel. The addition point is just before volume adjust­ment.

7.3.20. Identification Mode

7.3.21. FM DC Notch

The DC compensation filter (FM DC Notch) for FM input
can be switched off. This is used to speed up the auto­matic search function (see section 6.8.4.). In normal FM­mode, the FM DC Notch should be switched on.

FM DC Notch 0017

hex

ON 0000 0000 00

L

hex

Reset

OFF 0011 1111 3F

hex

7.3.22. Automatic Volume Correction (AVC)

AVC on/off 0029

AVC off and Reset

of int. variables

hex

0000 0

RESET

AVC on 1000 8

[15:12]

hex

hex

Identification Mode 0015

Standard B/G
(German Stereo)

Standard M

0000 0000 00
RESET

0000 0001 01

hex

L

hex

hex

(Korean Stereo)

Reset of Ident-Filter 00 11 1111 3F

hex

To shorten the response time of the identification algo­rithm after a program change between two FM-stereo
capable programs, the reset of the ident-filter can be ap­plied.

Sequence:

1. Program change

2. Reset ident-filter

3. Set identification mode back to standard B/G

4. Wait approx. 0.5 sec.

5. Read stereo detection register

AVC Decay Time 0029

8 sec (long)
4 sec (middle)
2 sec (short)
20 ms (very short)

1)

intended for quick adaptation to the average

1)

hex

1000 8

0100 4

0010 2

0001 1

[11:8]

hex
hex
hex
hex

volume level after channel change

Different sound sources (e.g. terrestrial channels, SAT
channels, or SCART) fairly often do not have the same
volume level. Advertisements during movies usually
have a higher volume level than the movie itself. This re­sults in annoying volume changes. The AVC solves this
problem by equalizing the volume level.

To prevent clipping, the AVC’s gain decreases quickly in
dynamic boost conditions. To suppress oscillation ef­fects, the gain increases rather slowly for low-level in­puts. The decay time is programmable by the AVC regis­ter bits [11:8].

For input signals ranging from −24 dBr to 0 dBr, the AVC
maintains a fixed output level of −18 dBr. Fig. 7–1 shows
the AVC output level versus its input level. For prescale
and volume registers set to 0 dB, a level of 0 dBr corre­sponds to full scale input/output. This is

– SCART in-, output 0 dBr = 2.0 V

rms

– Loudspeaker and Aux output 0 dBr = 1.4 Vrms

44 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

output level
[dBr]

–12

–18

–24

–30 –24 –18 –12 –6+6

0

input level

[dBr]

Fig. 7–1: Simplified AVC characteristics

To reset the internal variables, the AVC should be
switched off and on during any channel or source
change. For standard applications, the recommended
decay time is 4 sec.

Note: AVC should not be used in any Dolby Pro Logic
mode.

7.5.1. Stereo Detection Register

Stereo Detection

0018

hex

H

Register

Stereo/Bilingual Mode Reading ID-level

(two’s complement)

MONO near zero

STEREO positive value (ideal

reception: 7F

hex

)

BILINGUAL negative value (ideal

reception: 80

hex)

If FM Adaptive Deemphasis WP1 is active, the ID-level
in Stereo Detection Register is not valid.

A control processor evaluating the content of the Stereo
Detection Register (ID-level), should use the threshold
recommendations, shown in Fig. 7–2 for switching to
Stereo/Bilingual and back to Mono mode.

7.4. Exclusions for the Audio Baseband Features

In general, all functions can be switched independently
of the others. One exception exists:

1. NICAM cannot be processed simultaneously with the
FM2 channel (MSP 3415D only).

2. FM adaptive deemphasis WPI cannot be processed
simultaneously with the FM-identification.

7.5. DSP Read Registers: Functions and Values

All readable registers are 16-bit wide. Transmissions via

2

I

C bus have to take place in 16-bit words. Single data
entries are 8 bit. Some of the defined 16-bit words are
divided into low and high byte, thus holding two different
control entities.

These registers are not writeable.

Mode

Stereo

–20–25

Mono

20 25

Biling.

Fig. 7–2: Recommended thresholds for Stereo/
Mono/Bilingual switching

7.5.2. Quasi-Peak Detector

Quasi-Peak

0019

hex

Readout Left

Quasi-Peak

001A

hex

Readout Right

Quasi peak readout [0

... 7FFF

hex

hex

values are 16 bit two’s
complement

ID-level

[Dec]

H+L

H+L

]

The quasi peak readout register can be used to read out
the quasi peak level of any input source, in order to ad­just all inputs to the same normal listening level. The re­fresh rate is 32 kHz. The feature is based on a filter time
constant:

attack-time: 1.3 ms
decay-time: 37 ms

45Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

7.5.3. DC Level Register

DC Level Readout

001B

hex

H+L

FM1 (MSP-Ch2)

DC Level Readout

001C

hex

H+L

FM2 (MSP-Ch1)

DC Level [8000

... 7FFF

hex

hex

]
values are 16 bit two’s
complement

The DC level register measures the DC component of
the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
FM frequencies fine tuning. A too low demodulation fre­quency (DCO) results in a positive DC-Level and vice
versa. For further processing, the DC content of the de­modulated FM signals is suppressed. The time constant
τ, defining the transition time of the DC Level Register,
is approximately 28 ms.

7.5.4. MSP Hardware Version Code

7.5.5. MSP Major Revision Code

Major Revision 001E

MSP 34x5D 04

hex

hex

L

The MSP 34x5D is the fourth generation of ICs in the
MSP family.

7.5.6. MSP Product Code

Product 001F

MSP 3405D 05

MSP 3415D 0F

hex

hex

hex

H

By means of the MSP-Product Code, the control proces­sor is able to decide whether or not NICAM-controlling
should be accomplished.

7.5.7. MSP ROM Version Code

Hardware Version 001E

Hardware Version [00

MSP 34x5D – A2 01

MSP 34x5D – B3 02

hex

hex

hex

hex

... FF

hex

H

]

A change in the hardware version code defines hard­ware optimizations that may have influence on the chip’s
behavior. The readout of this register is identical to the
hardware version code in the chip’s imprint.

ROM Version 001F

Major software revision [00

MSP 34x5D – A2 22

MSP 34x5D – B3 23

hex

hex

hex

hex

... FF

hex

L

]

A change in the ROM version code defines internal soft­ware optimizations, that may have influence on the
chip’s behavior, e.g. new features may have been in­cluded. While a software change is intended to create no
compatibility problems, customers that want to use the
new functions can identify new MSP 34x5D versions ac­cording to this number.

To avoid compatibility problems with the MSPB series,
an offset of 20

is added to the ROM version code of

hex

the chip’s imprint.

46 Micronas

PRELIMINARY DATA SHEET

E

E

8. Specifications

8.1. Outline Dimensions

MSP 34x5D

619

60

9

44

4327

0.12±

25.14

1

10

2

9

26

0.12±

25.14

Fig. 8–1:

68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g
Dimensions in mm

0.2±

x 45 °1.1

±0.05

1.9

±0.1

4.05

±0.15

4.75

0.05±

0.71

0.04±

0.23

0.06±

0.48

0.9

0.3±

23.3

0.1

0.1±

24.2

16 x 1.27 = 20.32

1.27

2

24.2

0.1±

1.2 x 45°

1.27

7.5

7.5

0.1±

SPGS0027-2(P68)/1E

0.1±

16 x 1.27 = 20.32

0.28

SPGS0016-5(P64)/1

±0.1

19.3

±0.05

18

±0.06

±0.5

20.3

3364

132

57.7

1

1.778
31 x 1.778 = 55.1

±0.1

±0.05

±0.1

0.48

±0.06

±0.2

0.8

±0.1

3.8

±0.2

3.2

Fig. 8–2:

64-Pin Plastic Shrink Dual Inline Package

(PSDIP64)

Weight approximately 9.0 g
Dimensions in mm

2752

126

47.0

1

1.778
25 x 1.778 = 44.4

±0.1

±0.05

±0.1

0.48

±0.06

±0.1

±0.2

4.0

0.6

±0.2

2.8

SPGS0016-5(P52)/1

15.6

±0.06

0.28

16.3

Fig. 8–3:

52-Pin Plastic Shrink Dual In Line Package

(PSDIP52)

Weight approximately 5.5 g
Dimensions in mm

±0.1

±0.1

14

±1

47Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

4164

65

8

241

0.15±

0.15±

17.2

80

1.8

10.3

9.8

16

23.2

Fig. 8–4:

80-Pin Plastic Quad Flat Package

(PQFP80)

Weight approximately 1.61 g
Dimensions in mm

2333

0.17

0.1±

0.1±

8

5

0.1±

20

SPGS705000-1(P80)/1E

0.8

15 x 0.8 = 12.0

1.8

0.8

23 x 0.8 = 18.4

0.04±

0.17

40

0.05±

0.37

25

0.05±

1.3

±0.2

3

0.06±

2.7

0.1

0.1±

10 x 0.8 = 8

0.1±

14

0.1±

0.8

22

12

11

0.2±

2.15

0.2±

13.2

34

1.75

44

1.75

1.3

1

0.2±

13.2

Fig. 8–5:

44-Pin Plastic Metric Quad Flat Package
(PMQFP44)
Weight approx. 0.4 g
Dimensions in mm

2.0

0.075±

0.375

0.1

0.1±

0.1±

10

0.1±

0.1±

10

SPGS0006-3(P44)/1E

0.8

10 x 0.8 = 8

48 Micronas

PRELIMINARY DATA SHEET

(if not used)

8.2. Pin Connections and Short Descriptions

NC = not connected (leave vacant for future compatibility reasons)
TP = Test Pin (leave vacant; pin is used for production test only)
LV = leave vacant
X = obligatory; connect as described in application circuit diagram

MSP 34x5D

Pin No. Pin Name Type Connection

PLCC
68-pin

1 16 14 9 – TP OUT LV Test pin

2 – – – – NC LV Not connected

3 15 13 8 – TP OUT LV Test pin

4 14 12 7 17 I2S_DA_IN1 IN LV I2S1 data input

5 13 11 6 16 I2S_DA_OUT OUT LV I2S data output

6 12 10 5 15 I2S_WS IN/OUT LV I2S word strobe

7 11 9 4 14 I2S_CL IN/OUT LV I2S clock

8 10 8 3 13 I2C_DA IN/OUT X I2C data

9 9 7 2 12 I2C_CL IN/OUT X I2C clock

10 8 – 1 – NC LV Not connected

11 7 6 80 11 STANDBYQ IN X Standby (low-active)

12 6 5 79 10 ADR_SEL IN X I2C Bus address select

13 5 4 78 9 D_CTR_OUT0 OUT LV Digital control output 0

PSDIP
64-pin

PSDIP
52-pin

PQFP
80-pin

PMQFP
44-pin

Short Description

14 4 3 77 8 D_CTR_OUT1 OUT LV Digital control output 1

15 3 – 76 – NC LV Not connected

16 2 – 75 – NC LV Not connected

17 – – – – NC LV Not connected

18 1 2 74

19 64 1 73 7 TP LV Test pin

20 63 52 72 6 XTAL_OUT OUT X Crystal oscillator

21 62 51 71 5 XTAL_IN IN X Crystal oscillator

22 61 50 70 4 TESTEN IN X Test pin

23 60 49 69 – NC LV Not connected

24 59 48 68 3 ANA_IN– IN LV IF common

25 58 47 67 2 ANA_IN1+ IN LV IF input 1

26 57 46 66 1 AVSUP X Analog power supply +5 V

– – – 65 – AVSUP X Analog power supply +5 V

– – – 64 – NC LV Not connected

1)

– NC LV Not connected

– – – 63 – NC LV Not connected

49Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

Short DescriptionConnection

PLCC
68-pin

PSDIP
64-pin

PSDIP
52-pin

PQFP
80-pin

PMQFP
44-pin

TypePin NamePin No. Short DescriptionConnection

(if not used)

(if not used)

27 56 45 62 44 AVSS X Analog ground

– – – 61 – AVSS X Analog ground

28 55 44 60 43 MONO_IN IN LV Mono input

– – – 59 – NC LV Not connected

29 54 43 58 42 VREFTOP X Reference voltage IF A/D

converter

30 53 42 57 41 SC1_IN_R IN LV Scart 1 input, right

31 52 41 56 40 SC1_IN_L IN LV Scart 1 input, left

32 51 – 55 39 ASG1 AHVSS Analog shield ground 1

33 50 40 54 38 SC2_IN_R IN LV Scart 2 input, right

34 49 39 53 37 SC2_IN_L IN LV Scart 2 input, left

35 48 – 52

1)

– NC LV or

Not connected

AHVSS

36 47 38 51 – NC LV Not connected

37 46 37 50 – NC LV Not connected

38 45 – 49 – NC LV Not connected

39 44 – 48 – NC LV Not connected

40 43 – 47 – NC LV Not connected

41 – – 46 – NC LV Not connected

42 42 36 45 36 AGNDC X Analog reference voltage

high voltage part

43 41 35 44 35 AHVSS X Analog ground

– – – 43 – AHVSS X Analog ground

– – – 42 – NC LV Not connected

– – – 41 – NC LV Not connected

44 40 34 40 34 CAPL_M X Volume capacitor MAIN

45 39 33 39 33 AHVSUP X Analog power supply +8 V

46 38 32 38 32 NC LV Not connected

47 37 31 37 31 SC1_OUT_L OUT LV Scart 1 output, left

48 36 30 36 30 SC1_OUT_R OUT LV Scart 1 output, right

49 35 29 35 29 VREF1 X Reference ground 1

high voltage part

50 34 28 34 28 NC LV Not connected

51 33 27 33 – NC LV Not connected

52 – – 32 – NC LV Not connected

50 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

TypePin NamePin No. Short DescriptionConnection

PLCC
68-pin

53 32 – 31 – NC LV Not connected

54 31 26 30 – NC LV Not connected

55 30 – 29 – NC LV Not connected

56 29 25 28 27 DACM_L OUT LV Loudspeaker out, left

57 28 24 27 26 DACM_R OUT LV Loudspeaker out, right

58 27 23 26 25 VREF2 X Reference ground 2

59 26 22 25 24 NC LV Not connected

60 25 21 24 23 NC LV Not connected

– – – 23 – NC LV Not connected

– – – 22 – NC LV Not connected

61 24 20 21 22 RESETQ IN X Power-on-reset

62 23 – 20 – NC LV Not connected

PSDIP
64-pin

PSDIP
52-pin

PQFP
80-pin

PMQFP
44-pin

(if not used)

(if not used)

Short DescriptionConnection

high voltage part

63 22 – 19 – NC LV Not connected

64 21 19 18 – NC LV Not connected

65 20 18 17 21 I2S_DA_IN2 IN LV I2S2 data input

66 19 17 16 – DVSS X Digital ground

– – – 15 – DVSS X Digital ground

– – – 14 20 DVSS X Digital ground

67 18 16 13 19 DVSUP X Digital power supply +5 V

– – – 12 – DVSUP X Digital power supply +5 V

– – – 11 – DVSUP X Digital power supply +5 V

68 17 15 10 18 TP_CO OUT LV Test pin (Use this pin to

1) Note: For PQFP80 package ONLY and for A2 version ONLY, the following pin-allocation is valid:
Pin 74 = TP, Pin 52 = ASG2

define the capacitor size at
crystal oscillator.)

51Micronas

MSP 34x5D

8.3. Pin Configurations

PRELIMINARY DATA SHEET

TP

I2C_CL

NC

STANDBYQ

ADR_SEL
D_CTR_OUT0
D_CTR_OUT1

NC

NC

NC
NC

XTAL_OUT

XTAL_IN

TESTEN

NC

ANA_IN–

ANA_IN1+

AVSUP

TP

I2S_CL

I2C_DA

10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26

NC

TP

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

789

654321

MSP 34x5D

29 30 31 32 33 34 35 36 37 38 39

27 28

TP_CO

DVSUP

DVSS

I2S_DA_IN2

NC

NC

68 67 66 65 64 63 62 61

43424140

NC

RESETQ

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

NC
NC

VREF2
DACM_R
DACM_L
NC
NC

NC
NC

NC
NC
VREF1
SC1_OUT_R
SC1_OUT_L

NC
AHVSUP
CAPL_M

AVSS

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

SC2_IN_R

SC2_IN_L

Fig. 8–6: 68-pin PLCC package

AHVSS

AGNDC

NC

NC

NC

NC

NC

NC

NC

52 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

1

NC
NC

2
3

NC

NC

DVSS

NC
NC
NC

NC
NC

NC
NC
NC

4
5
6
7
8

9
10
11
12
13
14
15

TP

16

TP

17
18
19
20

21

22

23

24

25

26

27

28

29
30
31
32

D_CTR_OUT1
D_CTR_OUT0

ADR_SEL

STANDBYQ

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

TP_CO
DVSUP

I2S_DA_IN2 NC

RESETQ

VREF2

DACM_R

DACM_L

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

48
47
46

MSP 34x5D

45

44
43
42
41
40
39
38
37
36
35
34
33

TP
XTAL_OUT
XTAL_IN
TESTEN
NC
ANA_IN–
ANA_IN1+
AVSUP
AVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
ASG1

SC2_IN_R
SC2_IN_L
NC
NC
NC

NC
NC
AGNDC
AHVSS
CAPL_M
AHVSUP
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
NC

1

TP

NC
D_CTR_OUT1
D_CTR_OUT0

ADR_SEL

STANDBYQ

I2C_CL
I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

TP
TP

TP_CO

DVSUP

DVSS

I2S_DA_IN2

NC

RESETQ

NC

NC

VREF2
DACM_R
DACM_L

NC

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17
18
19
20

21

22

23

24

25

26

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

MSP 34x5D

36
35
34
33

32
31
30
29
28
27

Fig. 8–8: 52-pin PSDIP package

XTAL_OUT
XTAL_IN
TESTEN
NC
ANA_IN–
ANA_IN1+
AVSUP
AVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L

SC2_IN_R
SC2_IN_L
NC
NC
AGNDC
AHVSS
CAPL_M
AHVSUP
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
NC

Fig. 8–7: 64-pin PSDIP package

53Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

SC2_IN_L

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

NC

MONO_IN

AVSS

AVSS

NC

NC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

65AVSUP

66AVSUP

67ANA_IN1+

68ANA_IN–

69NC

70TESTEN

71XTAL_IN

72XTAL_OUT

73TP

74NC

75NC

76NC

77D_CTR_OUT1

78D_CTR_OUT0

79ADR_SEL

80STANDBYQ

123456789101112131415161718192021222324

MSP 34x5D

NC

NC

NC

NC

NC

NC

NC

AGNDC

AHVSS

AHVSS

NC

NC

CAPL_M40

AHVSUP39

NC38

SC1_OUT_L37

SC1_OUT_R36

VREF135

NC34

NC33

NC32

NC31

NC30

NC29

DACM_L28

DACM_R27

VREF226

NC25

NC

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

TP

TP

TP_CO

Fig. 8–9: 80-pin PQFP package

DVSUP

DVSUP

NC

NC

NC

RESETQ

NC

NC

NC

I2S_DA_IN2

DVSS

DVSS

DVSS

DVSUP

54 Micronas

PRELIMINARY DATA SHEET

NC

VREF1

SC1_OUT_R

SC1_OUT_L

NC

AHVSUP

33 32 31 30 29 28 27 26 25 24 23

34CAPL_M

35AHVSS

36AGNDC

37SC2_IN_L

38SC2_IN_R

39ASG1

40SC1_IN_L

41SC1_IN_R

42VREFTOP

43MONO_IN

44AVSS

MSP 34x5D

1234567891011

MSP 34x5D

DACM_L

DACM_R

VREF2

NC

NC

RESETQ22

I2S_DA_IN221

DVSS20

DVSUP19

TP_CO18

I2S_DA_IN117

I2S_DA_OUT16

I2S_WS15

I2S_CL14

I2C_DA13

I2C_CL12

AVSUP

ANA_IN+

ANA_IN–

TESTEN

XTAL_IN

D_CTR_OUT1

TP

XTAL_OUT

STANDBYQ

ADR_SEL

D_CTR_OUT0

Fig. 8–10: 44-pin PMQFP package

8.4. Pin Circuits (pin numbers refer to PLCC68 package)

Fig. 8–11: Input Pins 4, 11, 12, 61, and 65

(I2S_DA_IN1, STANDBYQ, ADR_SEL, RESETQ,
and I2S_DA_IN2)

DVSUP

P

N

GND

DVSUP

P

N

GND

Fig. 8–12: Output pins 5, 13, 14, and 68
(I2S_DA_OUT, D_CTR_OUT0/1, TP_CO)

Fig. 8–13: Input/Output pins 6 and 7
(I2S_WS, I2S_CL)

N

GND

Fig. 8–14: Input/Output Pins 8 and 9
(I2C_DA, I2C_CL)

55Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

P

3–30 pF

3–30 pF

500 k

N

Fig. 8–15: Input/Output Pins 20 and 21
(XTAL_OUT/IN)

ANA_IN1+

ANA_IN–
VREFTOP

125 k

≈ 3.75 V

Fig. 8–19: Pin 42 (AGNDC)

0...2 V

Fig. 8–20: Capacitor Pin 44
(CAPL_M)

A

D

40 pF

80 k

300

Fig. 8–16: Input Pins 24, 25, and 29
(ANA_IN–, ANA_IN1+, VREFTOP)

24 k

≈ 3.75 V

Fig. 8–17: Input Pin 28 (MONO_IN)

40 k

≈ 3.75 V

Fig. 8–18: Input Pins 30, 31, 33, and 34
(SC1–2_IN_L/R)

≈ 3.75 V

Fig. 8–21: Output Pins 47, 48
(SC1_OUT_L/R)

AHVSUP

0...1.2 mA

3.3 k

Fig. 8–22: Output Pins 56, 57
(DACM_L/R)

56 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

8.5. Electrical Characteristics

8.5.1. Absolute Maximum Ratings

Symbol Parameter Pin Name Min. Max. Unit

T

A

T

S

V

SUP1

V

SUP2

V

SUP3

dV

P

TOT

V

Idig

I

Idig

V

Iana

I

Iana

SUP23

Ambient Operating Temperature – 0 70

1)

°C

Storage Temperature – –40 125 °C

First Supply Voltage AHVSUP –0.3 9.0 V

Second Supply Voltage DVSUP –0.3 6.0 V

Third Supply Voltage AVSUP –0.3 6.0 V

Voltage between AVSUP
and DVSUP

Package Power Dissipation
PLCC68 without Heat Spreader
PSDIP64 without Heat Spreader
PSDIP52 without Heat Spreader
PMQFP44 without Heat Spreader

Input Voltage, all Digital Inputs –0.3 V

AVSUP,
DVSUP

AHVSUP,
DVSUP,
AVSUP

–0.5 0.5 V

1200
1300
1200

1)

910

+0.3 V

SUP2

mW

Input Current, all Digital Pins – –20 +20 mA

Input Voltage, all Analog Inputs SCn_IN_s,

3)

–0.3 V

SUP1

+0.3 V

MONO_IN

Input Current, all Analog Inputs SCn_IN_s,

3)

–5 +5 mA

MONO_IN

2)

2)

I

Oana

I

Oana

Output Current, all SCART Outputs SC1_OUT_s

Output Current, all Analog Outputs

DACM_s

3) 4) 4)

4), 5) 4), 5)

except SCART Outputs

I

Cana

1)

For PMQFP44 package, max. ambient operating temperature is 65 °C.

2)

positive value means current flowing into the circuit

3)

“n” means “1” or “2”, “s” means “L” or “R”

4)

The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.

5)

Total chip power dissipation must not exceed absolute maximum rating.

Output Current, other pins
connected to capacitors

CAPL_M
AGNDC

4) 4)

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi­mum ratings conditions for extended periods may affect device reliability.

57Micronas

MSP 34x5D

I2C_DA

8.5.2. Recommended Operating Conditions

= 0 to 70 °C)

(at T

A

PRELIMINARY DATA SHEET

Symbol Parameter

V

V

V

V

SUP1

SUP2

SUP3

RLH

First Supply Voltage AHVSUP 7.6 8.0 8.7

Second Supply Voltage DVSUP 4.75 5.0 5.25 V

Third Supply Voltage AVSUP 4.75 5.0 5.25 V

RESET Input Low-to-High
Transition Voltage

V

RHL

RESET Input High-to-Low
Transition Voltage

(see also Fig. 5–3 on page 19)

V

V

V

V

DIGIL

DIGIH

DIGIL

DIGIH

Digital Input Low Voltage ADR_SEL 0.2 V

Digital Input High Voltage 0.8 V

Digital Input Low Voltage STANDBYQ 0.2 V

Digital Input High Voltage
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

t

STBYQ1

STANDBYQ Setup Time before
Turn-off of Second Supply Voltage

Pin Name

Min. Typ. Max. Unit

1)

V

RESETQ 0.7 0.8 DVSUP

0.45 0.55 DVSUP

SUP2

SUP2

SUP2

STANDBYQ,

0.8

0.5
1 µs

V
V

SUP2
SUP2

DVSUP

I2C-Bus Recommendations

V

V

t

I2C1

t

I2C2

t

I2C5

I2CIL

I2CIH

I2C-Bus Input Low Voltage I2C_CL,

I2C-Bus Input High Voltage

0.6 V

I2C Start Condition Setup Time 120 ns

I2C Stop Condition Setup Time 120 ns

I2C-Data Setup Time before

55 ns

Rising Edge of Clock

t

I2C6

I2C-Data Hold Time after

55 ns

Falling Edge of Clock

t

I2C3

t

I2C4

f

I2C

1)

For MSP 34x5D-A1 and -A2 versions in PMQFP44 package, only 8.4 V is allowed.

I2C-Clock Low Pulse Time I2C_CL 500 ns

I2C-Clock High Pulse Time 500 ns

I2C-Bus Frequency 1.0 MHz

0.3 V

SUP2

SUP2

58 Micronas

PRELIMINARY DATA SHEET

MSP 34x5D

ParameterSymbol

I2S-Bus Recommendations

V

I2SIH

I2S-Data Input Low Voltage
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

V

I2SIL

I2S-Data Input High Voltage
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

t

I2S1

I2S-Data Input Setup Time
before Rising Edge of Clock

t

I2S2

I2S-Data Input Hold Time
after falling Edge of Clock

f

I2SCL

I2S-Clock Input Frequency
when MSP in I

R

I2SCL

f

I2SWS

I2S-Clock Input Ratio when
MSP in I

2

S-Slave Mode

I2S-Word Strobe Input Frequency
when MSP in I

2

S-Slave Mode

2

S-Slave Mode

Pin Name

UnitMax.Typ.Min.

I2S_DA_IN1/2

I2S_DA_IN1/2

0.25

0.2

0.75

0.5

20 ns

V
V

V
V

SUP2
SUP2

SUP2
SUP2

I2S_CL

0 ns

I2S_CL 1.024 MHz

0.9 1.1

I2S_WS 32.0 kHz

V

I2SIDL

V

I2SIDH

t

I2SWS1

t

I2SWS2

I2S-Input Low Voltage when
MSP in I

2

S-Slave Mode
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

I2S-Input High Voltage when
MSP in I

2

S-Slave Mode
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

I2S-Word Strobe Input Setup Time
before Rising Edge of Clock when
MSP in I

2

S-Slave Mode

I2S-Word Strobe Input Hold Time
after falling Edge of Clock when
MSP in I

2

S-Slave Mode

I2S_CL
I2S_WS

0.25

0.2

0.75

0.5

V
V

V
V

60 ns

0 ns

SUP2
SUP2

SUP2
SUP2

59Micronas

MSP 34x5D

PRELIMINARY DATA SHEET

ParameterSymbol

Pin Name

General Crystal Recommendations

f

P

Crystal Parallel Resonance Fre­quency at 12 pF Load Capacitance

R

R

C

0

Crystal Series Resistance 8 25 Ω

Crystal Shunt
(Parallel) Capacitance

C

L

External Load Capacitance

1)

XTAL_IN,
XTAL_OUT

Crystal Recommendations for Master-Slave Applications

f

TOL

D

C

f

CL

TEM

1

Accuracy of Adjustment –20 +20 ppm

Frequency Variation vs Temp. –20 +20 ppm

Motional (Dynamic) Capacitance 19 24 fF

Required Open Loop Clock
Frequency (T

= 25 °C)

amb

XTAL_IN,
XTAL_OUT

18.432 MHz

6.2 7.0 pF

PSDIP 1.5
PLCC 3.3
P(M)QFP 3.3

18.431 18.433

UnitMax.Typ.Min.

pF
pF
pF

MHz

Crystal Recommendations for FM / NICAM Applications (No Master-Slave Mode possible)

f

TOL

D

C

f

CL

TEM

1

Accuracy of Adjustment –30 +30 ppm

Frequency Variation vs Temp. –30 +30 ppm

Motional (Dynamic) Capacitance 15 fF

Required Open Loop Clock
Frequency (T

= 25 °C)

amb

XTAL_IN,
XTAL_OUT

18.4305 18.4335

MHz

Crystal Recommendations for FM Applications (No Master-Slave Mode possible)

f

TOL

D

TEM

Accuracy of Adjustment –100 +100 ppm

Frequency Variation versus

–50 +50 ppm

Temperature

Amplitude Recommendation for Operation with External Clock Input (C

V

XCA

1)

External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-

External Clock Amplitude XTAL_IN 0.7 V

after reset = 22 pF)

load

quency of the internal PLL and to stabilize the frequency in closed-loop operation.
Due to different layouts, the accurate capacitor size should be determined with the customer PCB

. The sug-

gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.

pp

To define the capacitor size, reset the MSP without transmitting any further I
0083

Bit [14]=1. Measure the frequency at pin TP_CO (see pin description in table on page 51). Change the

hex

2

C telegrams. Set MODE_REG

capacitor size until the free running frequency at pin TP_CO matches 6.144000 MHz (=18.432000 MHz / 3) as
closely as possible. The higher the capacity, the lower the resulting clock frequency.

60 Micronas

PRELIMINARY DATA SHEET

1)

1)

MSP 34x5D

ParameterSymbol

Pin Name

Analog Input and Output Recommendations

C

AGNDC

AGNDC-Filter-Capacitor AGNDC –20% 3.3 µF

Ceramic Capacitor in Parallel –20% 100 nF

C

inSC

DC-Decoupling Capacitor in front

SCn_IN_s

of SCART Inputs

V

inSC

V

inMONO

R

LSC

C

LSC

C

VMA

C

FMA

SCART Input Level 2.0 V

Input Level, Mono Input MONO_IN 2.0 V

SCART Load Resistance SC1_OUT_s

SCART Load Capacitance 6.0 nF
Main Volume Capacitor CAPL_M 10 µF

Main Filter Capacitor DACM_s

Recommendations for Analog Sound IF Input Signal

C

VREFTOP

VREFTOP-Filter-Capacitor VREFTOP –20% 10 µF

UnitMax.Typ.Min.

–20% 330 +20% nF

RMS

RMS

10 kΩ

1)

–10% 1 +10% nF

F

IF_FM

V

IF_FM

V

IF_AM

R

FMNI

R

AMNI

R

FM

R

FM1/FM2

R

FC

R

FV

PR

IF

Ceramic Capacitor in Parallel –20% 100 nF

Analog Input Frequency Range 0 9 MHz

Analog Input Range FM/NICAM 0.1 0.8 3 Vpp

Analog Input Range AM/NICAM 0.1 0.45 0.8 Vpp

Ratio: NICAM Carrier/FM Carrier
(unmodulated carriers) BG:

I:

Ratio: NICAM Carrier/AM Carrier
(unmodulated carriers)

–20
–23

–7
–10

0
0

dB
dB

–25 –11 0 dB

dB

Ratio: FM-Main/FM-Sub Satellite 7 dB

Ratio: FM1/FM2
German FM-System

Ratio: Main FM Carrier/

ANA_IN1+,
ANA_IN–

15 – – dB

7 dB

Color Carrier

Ratio: Main FM Carrier/

15 – – dB

Luma Components
Passband Ripple – – ±2 dB

SUP

HF

Suppression of Spectrum
Above 9.0 MHz

FM

MAX

Maximum FM-Deviation (apprx.)
normal mode
high deviation mode

1)

“n” means “1” or “2”, “s” means “L” or “R”

15 – dB

±180

kHz

±360

61Micronas

MSP 34x5D

D_CTR_OUT1

8.5.3. Characteristics

PRELIMINARY DATA SHEET

= 0 to 70 °C, f

at T

A

at T

= 60 °C, f

A

CLOCK

= 18.432 MHz, V

CLOCK

= 18.432 MHz, V

SUP1

= 7.6 to 8.7 V, V

SUP1

= 8 V, V

SUP2

= 4.75 to 5.25 V for min./max. values

SUP2

= 5 V for typical values, TJ = Junction Temperature

MAIN (M) = Loudspeaker Channel

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

f

CLOCK

D

CLOCK

t

JITTER

V

xtalDC

t

Startup

I

SUP1A

I

SUP1S

I

SUP2A

Clock Input Frequency XTAL_IN 18.432 MHz

Clock High to Low Ratio 45 55 %

Clock Jitter (Verification not
provided in production test)

DC-Voltage Oscillator 2.5 V

Oscillator Startup Time at
VDD Slew-rate of 1 V/1 µs

First Supply Current (active)

Analog Volume for Main and Aux at 0 dB
Analog Volume for Main and Aux at –30 dB

First Supply Current
(standby mode) at T

Second Supply Current (active)
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

= 27 °C

j

XTAL_IN,
XTAL_OUT

AHVSUP

DVSUP

0.4 2 ms

9.6

6.3

3.5 5.6 7.7 mA STANDBYQ = low

86
50

17.1

11.2

95
70

50 ps

24.6

16.1mAmA

102
85

mA
mA

I

SUP3A

Digital Contol Outputs

V

DCTROL

V

DCTROH

I2C-Bus

V

I2COL

I

I2COH

t

I2COL1

t

I2COL2

Third Supply Current (active)
MSP 34x5D version A1, A2
MSP 34x5D version B3 and later

Digital Output Low Voltage D_CTR_OUT0

Digital Output High Voltage

I2C-Data Output Low Voltage I2C_DA 0.4 V I

I2C-Data Output High Current 1.0 µA V

I2C-Data Output Hold Time
after Falling Edge of Clock

I2C-Data Output Setup Time
before Rising Edge of Clock

AVSUP

I2C_DA,
I2C_CL

15
20

4.0 V I

15 ns

100 ns f

25
35

35
45

0.4 V I

mA
mA

DCTR

DCTR

I2COL

I2COH

= 1 MHz

I2C

= 1 mA

= –1 mA

= 3 mA

= 5 V

62 Micronas

PRELIMINARY DATA SHEET

I2S_CL

1)

1)

→

I2S-Bus

MSP 34x5D

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

V

I2SOL

V

I2SOH

f

I2SWS

f

I2SCL

t

I2S1/I2S2

t

I2S3

t

I2S4

t

I2S5

t

I2S6

I2S Output Low Voltage I2S_WS

I2S Output High Voltage

I2S Word Strobe Output Frequency I2S_WS 32.0 kHz NICAM-PLL closed

I2S Clock Output Frequency I2S_CL 1024 kHz

I2S Clock High/Low Ratio 0.9 1 1.1

I2S Data Setup Time
before Rising Edge of Clock

I2S Data Hold Time
after Falling Edge of Clock

I2S Word Strobe Setup Time
before Rising Edge of Clock

I2S Word Strobe Hold Time
after Falling Edge of Clock

Analog Ground

V

AGNDC0

R

outAGN

AGNDC Open Circuit Voltage AGNDC 3.67 3.77 3.87 V R
AGNDC Output Resistance 70 125 180 kΩ 3 V ≤ V

Analog Input Resistance

R

inSC

SCART Input Resistance
from T

= 0 to 70 °C

A

I2S_DA_OUT

I2S_CL
I2S_DA_OUT

I2S_CL
I2S_WS

SCn_IN_s

1)

0.4 V I

4.0 V I

I2SOL

I2SOH

= 1 mA

= –1 mA

200 ns CL = 30 pF

180 ns

200 ns

180 ns

≥ 10 MΩ

load

AGNDC

25 40 58 kΩ f

= 1 kHz, I = 0.05 mA

signal

≤ 4 V

R

inMONO

MONO Input Resistance
from T

= 0 to 70 °C

A

Audio Analog-to-Digital-Converter

V

AICL

Effective Analog Input Clipping
Level for Analog-to-Digital­Conversion

SCART Outputs

R

outSC

dV

OUTSC

A

SCtoSC

f

rSCtoSC

SCART Output Resistance
at T

= 27 °C

j

from T

= 0 to 70 °C

A

Deviation of DC-Level at SCART
Output from AGNDC Voltage

Gain from Analog Input
to SCART Output

Frequency Response from Analog
Input to SCART Output
Bandwidth: 0 to 20000 Hz

V

outSC

Effective Signal Level at SCART­Output during full-scale Digital In­put Signal from DSP

1)

“n” means “1”, or “2”; “s” means “L” or “R”

MONO_IN 15 24 35 kΩ f

SCn_IN_s1),
MONO_IN

2.00 2.25 V

RMS

SC1_OUT_s

200
200

330 460

500

Ω
Ω

= 1 kHz, I = 0.1 mA

signal

f

= 1 kHz

signal

f

= 1 kHz, I = 0.1 mA

signal

–70 +70 mV

SCn_IN_s

–1.0 +0.5 dB f

MONO_IN

SC1_OUT_s

,

SC1_OUT_s

1)

–0.5 +0.5 dB with resp. to 1 kHz

1)

1.8 1.9 2.0 V

RMS

signal

f

signal

= 1 kHz

= 1 kHz

63Micronas

MSP 34x5D

to ground by Z < 1 kΩ

()

Main Outputs

PRELIMINARY DATA SHEET

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

R

outMA

V

outDCMA

Main Output Resistance
at T

= 27 °C

j

from T

= 0 to 70 °C

A

DC-Level at Main-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB

V

outMA

Effective Signal Level at Main-Out­put during full-scale Digital Input
Signal from DSP for Analog Vol­ume at 0 dB

Analog Performance

SNR Signal-to-Noise Ratio

from Analog Input to
SCART Output

THD Total Harmonic Distortion

from Analog Input to
SCART Output

XTALK Crosstalk Attenuation

DACM_s1)

MONO_IN,
SCn_IN_s

1)

→
SC1_OUT_s1)

MONO_IN,
SCn_IN_s

1

)

→
SC1_OUT_s

f

= 1 kHz, I = 0.1 mA

2.1

2.1

3.3 4.6

5.0

kΩ
kΩ

signal

1.8 2.04612.28 V
mV

1.23 1.37 1.51 V

RMS

f

signal

= 1 kHz

93 96 dB Input Level = –20 dB,

f

= 1 kHz,

sig

equally weighted
20 Hz...20 kHz

0.01 0.03 % Input Level = –3 dBr,
f

= 1 kHz,

sig

1

)

equally weighted
20 Hz...20 kHz

between left and right channel within
SCART Input/Output pair (L→R, R→L)

SCn_IN → SC1_OUT1) 80 dB

PSRR: rejection of noise on AHVSUP at 1 kHz

PSRR AGNDC AGNDC 80 dB

From Analog Input to
SCART Output

MONO_IN,
SCn_IN_s

1)

70 dB

SC1_OUT_s1)

S/N

THD

FM

FM

FM Input to Main/SCART Output DACM_s1),

SC1_OUT_s

Total Harmonic Distortion and
Noise of FM demodulated signal on

DACM_s1),
SC1_OUT_s

73 dB 1 FM-carrier 5.5 MHz,

1

)

1

)

0.1 %

Main/SCART Outputs

S/N

NICAM

Signal-to-Noise Ratio of NICAM
Baseband Signal on Main/SCART

DACM_s1),
SC1_OUT_s

72 dB NICAM: –6 dB, 1 kHz,

1

)

Outputs

Input Level = –3 dB,
f

= 1 kHz, unused

sig

analog inputs connected

equally weighted
20 Hz...20 kHz

50 µs, 1 kHz, 40 kHz de­viation; RMS, unweighted
0 to 15 kHz (for S/N);
full input range,
FM-Prescale = 46h,
Vol = 0 dB →
Output Level 1 Vrms at
DACM_s; SPM = 3

RMS unweighted
0 to 15 kHz,
NICAM_Prescale = 7Fh,
Vol = 9 dB →
Output level 1 V
DACM_s

SPM = 8

;

RMS

at

1)

“n” means “1” or “2”; “s” means “L” or “R”
SPM: Short Programming Mode

64 Micronas

PRELIMINARY DATA SHEET

FM/AM-Prescale

3C

ANA_IN

Input Level

dBr

MSP 34x5D

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

THD

NICAM

Total Harmonic Distortion and
Noise of NICAM Baseband Signal

DACM_s1),
SC1_OUT_s

1

)

0.1 % 2.12 kHz, modulator input

on Main/SCART Outputs

BER

S/N

NI

AM

NICAM: Bit Error Rate – 1 10

Signal-to-Noise Ratio of AM Base­band Signal on Main/SCART Out-

DACM_s1),
SC1_OUT_s

48 dB SIF input range:

1

)

puts

THD

AM

Total Harmonic Distortion and
Noise of AM Demodulated Signal

DACM_s1),
SC1_OUT_s

1

)

0.3 %

on Main/SCART Outputs

R

IFIN

DC

VREFTOP

DC

ANA_IN

XTALK

BW

IF

IF

Input Impedance ANA_IN1+,

ANA_IN–

1.5

10.5214.1

2.5

17.6kΩkΩ

DC Voltage at VREFTOP VREFTOP 2.56 2.66 2.76 V

DC Voltage on IF inputs ANA_IN1+,

1.3 1.5 1.7 V

ANA_IN–

Crosstalk Attenuation ANA_IN1+,

40 dB f

–

3 dB Bandwidth

10 MHz

AGC AGC Step Width 0.85 dB

level = 0 dBref
SPM = 8

–7

FM and NICAM,
norm conditions

0.1–0.8 Vpp; AM= 70%,
1 kHz, RMS unweighted
(S/N); 0 to 15 kHz,

Vol = 0 dB → Output level:

=

0.5 V
AM + NICAM, norm condi-

at DACM_s

RMS

hex

,

tions; SPM = 9

Gain AGC = 20 dB
Gain AGC = 3 dB

= 1 MHz

signal

p

= –2

dV

FMOUT

dV-

NICAMOUT

fR

FM

Tolerance of Output Voltage
of FM Demodulated Signal

Tolerance of Output Voltage
of NICAM Baseband Signal

FM Frequency Response on Main/
SCART Outputs,
Bandwidth 20 to 15000 Hz

fR

NICAM

NICAM Frequency Response on
Main/SCART Outputs,
Bandwidth 20 to 15000 Hz

SEP

FM

SEP

NICAM

XTALK

FM

XTALK-

NICAM

1)

“n” means “1” or “2”; “s” means “L” or “R”

FM Channel Separation (Stereo) DACM_s1),

NICAM Channel Separation
(Stereo)

FM Crosstalk Attenuation (Dual) DACM_s1),

NICAM Crosstalk Attenuation
(Dual)

SPM: Short Programming Mode

DACM_s1),
SC1_OUT_s

DACM_s1),
SC1_OUT_s

DACM_s1),
SC1_OUT_s

DACM_s1),
SC1_OUT_s

SC1_OUT_s

DACM_s1),
SC1_OUT_s

SC1_OUT_s

DACM_s1),
SC1_OUT_s

–1.5 +1.5 dB 1 FM-carrier, 50 µs, 1 kHz

1

)

–1.5 +1.5 dB 2.12 kHz, modulator input

1

)

–1.0 +1.0 dB 1 FM-carrier 5.5 MHz,

1

)

40 kHz deviation; RMS

level = 0 dBref

50 µs, modulator input
level = –14.6 dBref; RMS

–1.0 +1.0 dB Modulator input

1

)

50 dB 2 FM-carriers

1

)

level = –12 dB dBref; RMS

5.5/5.74 MHz, 50 µs,
1 kHz, 40 kHz deviation;
RMS

80 dB

1

)

80 dB 2 FM-carriers

1

)

5.5/5.74 MHz, 50 µs,
1 kHz, 40 kHz deviation;
RMS

80 dB

1

)

65Micronas

MSP 34x5D

9. Application Circuit

PRELIMINARY DATA SHEET

AHVSS

Tuner 1

330 nF

330 nF

330 nF

330 nF

330 nF

Signal GND

IF 1 IN

56 pF56 pF

ANA_IN1+ (58) 25

28 (55) MONO_IN

31 (52) SC1_IN_L

30 (53) SC1_IN_R

32 (51) ASG1

34 (49) SC2_IN_L

33 (50) SC2_IN_R

ANA_IN– (59) 24

10 µF100

nF

–

+

VREFTOP (54) 29

3.3

100

µF

nF

+

AGNDC (42) 42

C s. section 8.5.2.

18.432
MHz

+

XTAL_IN (62) 21

XTAL_OUT (63) 20

DACM_L (29) 56

DACM_R (28) 57

+8.0 V

10 µF

CAPL_M (40) 44

1 nF

Alternative circuit for
ANA_IN1+ for more
attenuation of video
components:

1 K

1 µF

1 µF

56 p100 p

ANA_IN1+

MAIN

5V

5V

DVSS

DVSS

ResetQ
(from CCU,
see
section.5.3.)

11 (7) STANDBYQ

12 (6) ADR_SEL

8 (10) I2C_DA

9 (9) I2C_CL

6 (12) I2S_WS

7 (11) I2S_CL

4 (14) I2S_DA_IN1

65 (20) I2S_DA_IN2

5 (13) I2S_DA_OUT

61 (24) RESETQ

MSP 34x5D

27 (56) AVSS

AVSS

45 (39) AHVSUP

67 (18) DVSUP

100
nF

26 (57) AVSUP

66 (19) DVSS

100
nF

5 V 5 V 8.0 V

SC1_OUT_L (37) 47

SC1_OUT_R (36) 48

D_CTR_OUT0 (5) 13

D_CTR_OUT1 (4) 14

TESTEN (61) 22

43 (41) AHVSS

100
nF

49 (35) VREF1

58 (27) VREF2

100Ω

100Ω

+

+

22 µF

22 µF

AVSS

Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package.

66 Micronas

PRELIMINARY DATA SHEET

10. Appendix A: MSP 34x5D Version History

A1

First hardware release MSP 3415D

A2

Second hardware release MSP 3405D and MSP 3415D

B3

– I2S Bus supported with version B3 and later versions
– digital input specification changed with version B3 and

later versions (see section ... )

– max. analog high supply voltage AHVSUP 8.7 V

MSP 34x5D

67Micronas

MSP 34x5D

11. Data Sheet History

1. Preliminary Data Sheet: “MSP 34x5D Multistandard
Sound Processors”, Aug. 5, 1998, 6251-475-1PD.
First release of the preliminary data sheet.

2. Preliminary Data Sheet: “MSP 34x5D Multistandard
Sound Processors”, Oct. 14, 1999, 6251-475-2PD.
Second release of the preliminary data sheet.
Major changes:

– specification for version B3 added

(see Appendix A: Version History)
– specification for I
– section 8.1.: Outline Dimensions for all packages

changed

2

S interface added

PRELIMINARY DATA SHEET

Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. [phone]
Fax [phone]
E-mail: [e-mail]
Internet: www.micronas.com

Printed in Germany
Order No. 6251-475-2PD

All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirma­tion form; the same applies to orders based on development samples
delivered. By this publication, Micronas GmbH does not assume re­sponsibility for patent infringements or other rights of third parties
which may result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on
a retrieval system, or transmitted without the express written consent
of Micronas GmbH.

68 Micronas

MSP 34xxD

Preliminary Data Sheet Supplement

Subject:
Data Sheet Concerned:

Supplement:
Edition:

MSP 34xxD Family Compatibility Differences:

The MSP-family (MSP 3410D, MSP 3400D, MSP 3415D, MSP 3405D, MSP 3417D, MSP 3407D) is currently avail-

able in different technologies (0.8 µ, 0.5 µ, and 0.45 µ).
The specific differences of the various implementations are listed in the attached table.

Compatibility Differences
All MSP 34xxD Data Sheets:

6251-482-2PD, 6251-475-2PD, 6251-486-2PD
No. 3/ 6251-526-3PDS
Oct. 11, 2000

Micronas page 1 of 1

Micronas

Compatibility Differences between 0.5/0.45µ and 0.8µ MSPD Devices

H1, H3

H2, H4

H5

MSP 3415D / MSP 3405DMSP 3410D / MSP 3400D

Version Code

Technology

Mask Iteration Code

B4 A2 A1

C5

0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ

67, 6B, 6G 8C and 94

G1, G4

6C, 6D 8D

B3 B2

G2, G5

Feature Documented in

Datasheet Reference

MSP 3400D, MSP 3410D Edit. May 1999

MSP 3405D, MSP 3415D Edit Oct. 1999

General Hardware

Power Consumption Datasheet 910 mW 640 mW 600 mW 910 mW 640 mW 600 mW 910 mW 640 mW 600 mW

Total Electromagnetic Radiation (EMR) - - -

V

typical

AGNDC0

DC

Digital Input Pin characteristics

(I2S_IN1/2, I2S_WS/CL, StANDBYQ)

VREFTOP

Maximum V

typical

sup1

Datasheet 3.73 V 3.73 V 3.73 V
Datasheet 2.6 V 2.6 V 2.6 V
Datasheet 8.4 V 8.4 V 8.4 V

Datasheet - - -

due to less Power Consumption

less

due to less Power Consumption

3.77 V

2.66 V

8.7 V

modified specifications

(see datasheet)

less

3.77 V 3.77 V

2.66 V 2.66 V

8.7 V 8.7 V

modified specifications

(see datasheet)

Demodulator

Carrier Mute - - -

AM-Frequency Response

Automatic Standard Detection - - -

- - -

slightly slower, but more stable:

64ms mute, 500 ms demute

more flat more flat

faster, more stable and with mute-

function

slightly slower, but more stable:

64ms mute, 500 ms demute

faster, more stable and with mute-

function

Baseband Processing

J17-Deemphasis for FM-Input channels

I2S-Bus

Frequency response of 50/75µs Deemphasis - - -

DC_Level (DSP-Reg.: 1B

/1C

)

hex

hex

Datasheet

Supplement

Datasheet not available

available available available

- - -

not available

(75µs instead of J17)

available available not available

more flat more flat more flat

Level increased by

appr. 15% 1*)

not available

(75µs instead of J17)

Level increased by

appr. 15% 1*)

MSP 3417D / MSP 3407DMSP-Type

6E, 6F 8F

MSP 3407D, MSP 3417D Edit Jan. 2000

due to less Power Consumption

modified specifications

(see datasheet)

slightly slower, but more stable:

64ms mute, 500 ms demute

faster, more stable and with mute-

not available

(75µs instead of J17)

Level increased by

appr. 15% 1*)

G3, G6,

less

more flat

function

Date: 11.10.00 Page 1 of 2 Pages

Micronas

H1, H3

H2, H4

H5

Version Code

Technology

Mask Iteration Code

B4 A2 A1

0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ

67, 6B, 6G 8C and 94

C5

G1, G4

6C, 6D 8D

Feature Documented in

D/A-Outputs

S/N-ratio

- - -

improved

Pinning

SCART2_Out pin Datasheet connected

DAC-Headphone pins Datasheet connected

Audio_Clock_Out Datasheet connected

The following pins refer to PQFP80:

Pin 52 Datasheet ASG2 ASG2 ASG2 ASG2

Pin 32 Datasheet ASG3 ASG3
Pin 14 Datasheet not connected DVSS DVSS not connected DVSS DVSS

Pin 16 Datasheet DVSS not connected not connected DVSS not connected not connected

connected not connected
connected

connected

not connected

(s. Datasheet P.59)

*1) In spite of increased DC-level controller-algorithms for automatic Sat-Carrier detection should run properly

MSP 3415D / MSP 3405DMSP 3410D / MSP 3400D

improved improved

not connected

not connected

(s. Datasheet P.51)

not connected

(s. Datasheet P.51)

not connected

(s. Datasheet P.51)

MSP 3417D / MSP 3407DMSP-Type

B3 B2

G2, G5

6E, 6F 8F

not connected
not connected

not connected

MSP 34x7D not available in 80-PQFP

MSP 34x7D not available in 80-PQFP
MSP 34x7D not available in 80-PQFP

MSP 34x7D not available in 80-PQFP

G3, G6,

Date: 11.10.00 Page 2 of 2 Pages