Datasheet MSP3400D, MSP3410D Datasheet (Micronas Intermetall)

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MSP 3400D, MSP 3410D Multistandard Sound Processors

Edition May 14, 1999 6251-482-2PD

PRELIMINARY DATA SHEET

MICRONAS

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MSP 34x0D PRELIMINARY DATA SHEET

Contents

Page Section Title

5 1. Introduction

5 1.1. Common Features of MSP 34x0D 5 1.2. Specific Features of MSP 3410D

6 2. Basic Features of the MSP 34x0D

6 2.1. Demodulator and NICAM Decoder Section 6 2.2. DSP Section (Audio Baseband Processing) 6 2.3. Analog Section

7 3. Application Fields of the MSP 34x0D

7 3.1. NICAM plus FM/AM-Mono 7 3.2. German 2-Carrier System (Dual-FM System)

10 4. Architecture of the MSP 34x0D

10 4.1. Demodulator and NICAM Decoder Section 10 4.1.1. Analog Sound IF – Input Section 11 4.1.2. Quadrature Mixers 11 4.1.3. Low-pass Filtering Block for Mixed Sound IF Signals 12 4.1.4. Phase and AM Discrimination 12 4.1.5. Differentiators 12 4.1.6. Low-pass Filter Block for Demodulated Signals 12 4.1.7. High-Deviation FM Mode 12 4.1.8. FM Carrier Mute Function in the Dual-Carrier FM Mode 12 4.1.9. DQPSK Decoder 12 4.1.10. NICAM Decoder 13 4.2. Analog Section 13 4.2.1. SCART Switching Facilities 13 4.2.2. Stand-by Mode 13 4.3. DSP Section (Audio Baseband Processing) 13 4.3.1. Dual-Carrier FM Stereo/Bilingual Detection 15 4.4. Audio PLL and Crystal Specifications 15 4.5. ADR Bus Interface 15 4.6. Digital Control Output Pins

16 4.7. I

S Bus Interface

17 5. I

C Bus Interface: Device and Subaddresses

18 5.1. Protocol Description 19 5.2. Proposal for MSP 34x0D I

C Telegrams 19 5.2.1. Symbols 19 5.2.2. Write Telegrams 19 5.2.3. Read Telegrams 19 5.2.4. Examples

20 5.3. Start-Up Sequence: Power-Up and I

C-Controlling

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PRELIMINARY DATA SHEET

Contents, continued

Page Section Title

21 6. Programming the Demodulator and NICAM Decoder Section

21 6.1. Short-Programming and General Programming of the Demodulator Part 22 6.2. Demodulator Write Registers: Table and Addresses 22 6.3. Demodulator Read Registers: Table and Addresses 23 6.4. Demodulator Write Registers for Short-Programming: Functions and Values 23 6.4.1. Demodulator Short-Programming 24 6.4.2. AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono 25 6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values 25 6.5.1. Register ‘AD_CV’

27 6.5.2. Register ‘MODE_REG’ 28 6.5.3. FIR Parameter 30 6.5.4. DCO Registers 31 6.6. Demodulator Read Registers: Functions and Values 32 6.6.1. Autodetection of Terrestrial TV Audio Standards 32 6.6.2. C_AD_BITS 32 6.6.3. ADD_BITS [10...3] 0038 32 6.6.4. CIB_BITS 33 6.6.5. ERROR_RATE 0057 33 6.6.6. CONC_CT (for compatibility with MSP 3410B) 33 6.6.7. FAWCT_IST (for compatibility with MSP 3410B) 33 6.6.8. PLL_CAPS 33 6.6.9. AGC_GAIN 33 6.7. Sequences to Transmit Parameters and to Start Processing 35 6.8. Software Proposals for Multistandard TV Sets 35 6.8.1. Multistandard Including System B/G with NICAM/FM-Mono only 35 6.8.2. Multistandard Including System I with NICAM/FM-Mono only 35 6.8.3. Multistandard Including System B/G with NICAM/FM-Mono and German DUAL-FM 35 6.8.4. Satellite Mode 35 6.8.5. Automatic Search Function for FM Carrier Detecti on

hex

MSP 34x0D

37 7. Programming the DSP Section (Audio Baseband Processing)

37 7.1. DSP Write Registers: Table and Add ress es 39 7.2. DSP Read Registers: Table and Addresses 40 7.3. DSP Write Registers: Functions and Values 40 7.3.1. Volume – Loudspeaker and Headphone Channel 41 7.3.2. Balance – Loudspeaker and Headphone Channel 41 7.3.3. Bass – Loudspeaker and Head pho ne Chann el 42 7.3.4. Treble – Loudspeaker and Headphone Channel 42 7.3.5. Loudness – Loudspea ke r and Head pho ne Chann el 43 7.3.6. Spatial Effects – Lo uds pe ak er Channel 44 7.3.7. Volume – SCART1 and SCART2 Channel 44 7.3.8. Channel Source Modes 45 7.3.9. Channel Matrix Modes 45 7.3.10. SCART Prescale 46 7.3.11. FM/AM Prescale 46 7.3.12. FM Matrix Modes (see also Table 4–1) 46 7.3.13. FM Fixed Deemphasis

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Contents, continued

Page Section Title

46 7.3.14. FM Adaptive Deemphasis 47 7.3.15. NICAM Prescale 47 7.3.16. NICAM Deemphasis 47 7.3.17. I 47 7.3.18. ACB Register 48 7.3.19. Beeper 48 7.3.20. Identification Mode 48 7.3.21. FM DC Notch 48 7.3.22. Mode Tone Control 48 7.3.23. Automatic Volume Correction (AVC) 49 7.3.24. Subwoofer Channel 50 7.3.25. Equalizer Loudspeaker Channel 50 7.4. Exclusions for the Audio Baseband Features 50 7.5. Phase Relationship of Analog Outputs 50 7.6. DSP Read Registers: Functions and Values 50 7.6.1. Stereo Detection Register 51 7.6.2. Quasi-Peak Detector 51 7.6.3. DC Level Register 51 7.6.4. MSP Hardware Version Code 51 7.6.5. MSP Major Revision Code 51 7.6.6. MSP Product Code 51 7.6.7. MSP ROM Version Code

S1 and I2S2 Prescale

52 8. Differences between MSP 3400C, MSP 3400D, MSP 3410B, and MSP 3410D

55 9. Specifications

55 9.1. Outline Dimensions 57 9.2. Pin Connections and Short Descriptions 60 9.3. Pin Configurations 64 9.4. Pin Circuits (pin numbers refer to PLCC68 package) 66 9.5. Electrical Characteristics 66 9.5.1. Absolute Maximum Ratings 67 9.5.2. Recommended Operating Conditions 71 9.5.3. Characteristics

77 10. Application Circuit

79 11. Appendix A: MSP 34x0D Version History

80 12. Data Sheet History

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PRELIMINARY DATA SHEET MSP 34x0D

Multistandard Sound Processors

Release Notes: The hardware description in this document is valid for the MSP 34x0D version B3 and following versions. Revision bars indicate significant changes to the previous edition.

1. Introduction

The MSP 34x0D is designed as a single-chip Multistandard Sound Processor for applications in analog and digital TV sets, satellite receivers, video recorders, and PC cards.

The MSP 34x0D, again, improves function integration: The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip. It covers all European TV standards (some examples are shown in Table3–1).

The MSP 3400D is fully pin and software-compatible to the MSP 3410D, but is not able to decode NICAM. It is also compatible to the MSP 3400C.

The IC is produced in submicron CMOS technology, combined with high-performance digital signal processing. The MSP 34x0D is available in the following packages: PLCC68, PSDIP64, PSDIP52, PQFP80, and PLQFP64.

Note: The MSP 3410D version is fully downward-compatible to the MSP 3410B, the MSP 3400B, and the MSP 3400C. To achieve full software-compatibility with these types, the demodulator part must be programmed as described in the data sheet of the MSP 3410B.

1.1. Common Features of MSP 34x0D

– AVC: Automatic Volume Correction – Subwoofer Output – 5-band graphic equalizer (as in MSP 3400C) – Enhanced spatial effect (pseudostereo/basewidth

enlargement as in MSP 3400C)

– headphone channel with balance, bass, treble, loud-

ness

– balance for loudspeaker and headphone channels

in dB units (optional)

– D/A converters for SCART2 out – improved oversampling filters (as in MSP 3400C) – Four SCART inputs – Full SCART in/out matrix without restrictions – SCART volume in dB units (optional)

– Additional I

S input (as in MSP 3400C)

– New FM identification (as in MSP 3400C) – Demodulator short programming – Autodetection for terrestrial TV sound standards – Improved carrier mute algorithm – Improved AM demodulation – ADR together with DRP 3510A – Dolby Pro Logic together with DPL 351xA – Reduction of necessary controlling – Less external components – Significant reduction of radiation

1.2. Specific Features of MSP 3410D

– All NICAM standards – Precise bit-error rate indication – Automatic switching from NICAM to FM/AM or vice-

versa

– Improved NICAM synchronization algorithm

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MSP 34x0D PRELIMINARY DATA SHEET

Loudspeaker OUT

Subwoofer OUT

Headphones OUT

SCART1 OUT

SCART2 OUT

MSP 34x0D

ADR

SI2C

Sound IF 1 Sound IF 2 MONO IN SCART1 IN SCART2 IN SCART3 IN SCART4 IN

2. Basic Features of the MSP 34x0D

2.1. Demodulator and NICAM Decoder Section

The MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound. Alternatively, two-carrier FM systems according to the German or Kor ean terrestrial specs or the satellite specs can be processed with the MSP 34x0D.

Digital demodulation and decoding of NICAM-coded TV stereo sound, is done only by the MSP 3410.

The MSP 34x0D offers a powerful feature to calculate the carrier fie ld strength which can be used for automatic standard detection (te rrestrial) and search algorithms (satellite). The IC may be used in TV sets, as well as in satellite tu ners and video rec orders. It offers profitable multistandard ca pabil ity, including the following advantages:

– two selectable analog inputs (TV and SAT-IF

sources)

– Automatic Gain Control (AGC) for analog IF input.

Input range: 0.10–3V

– integrated A/D converter for sound-IF inputs – all demodulation and filtering is performed on chip

and is individually programmable

– easy realization of all digital NICAM standards (B/G,

I, L, and D/K) with MSP 3410.

– FM demodulation of all terrestrial standards (incl.

identification decoding )

– FM demodulation of all satellite standards – no external filter hardware is required – only one crystal clock (18.432 MHz) is necessary – FM carrier level calculation for automatic search

algorithms and carrier mute function

– high-deviation FM-Mono mode (max. deviation:

approx.

±360 kHz)

2.2. DSP Section (Audio Baseband Processing)

– flexible selection of audio sources to be processed

– two digital input and one output interface via I

Sbus for external DSP processors, featuring surround sound, ADR etc.

– digital interface to process ADR (ASTRA Digital

Radio) together with DRP 3510A

– performance of all deemphasis systems including

adaptive Wegener Panda 1 without external components or controlling

– digitally performed FM identification decoding and

dematrixing

– digital baseband processing: volume, bass, treble,

5-band equalizer, loudness, pseudostereo, and basewidth enlargement

– simple controlling of volume, bass, treble, equalizer

etc.

2.3. Analog Section

– four selectable analog pairs of audio baseband

inputs (= four SCART inputs) input level:

≤2V

input impedance:

RMS

≥25 kΩ

– one selectable analog mono input (i.e. AM sound):

input level:

≤2V

input impedance:

RMS

≥15 kΩ

– two high-quality A/D converters, S/N-Ratio: ≥85 dB – 20 Hz to 20 kHz bandwidth for

SCART-to-SCART copy facilities

– MAIN (loudspeaker) and AUX (headphones): two

pairs of fourfold oversampled D/A-converters output level per channel: max. 1.4 V

RMS

output resistance: max. 5 kΩ S/N-ratio: ≥85 dB at maximum volume max. noise voltage in mute mode:

≤10 µV

(BW: 20 Hz ...16 kHz)

– two pairs of fourfold oversampled D/A converters

supplying two selectable pairs of SCART outputs. output level per channel: max. 2 V output resistance: max. 0.5 k S/N-Ratio:

≥85 dB (20 Hz ... 16 kHz)

Ω,

RMS

Fig. 2–1: Main I/O signals of the MSP 34x0D

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PRELIMINARY DATA SHEET MSP 34x0D

3. Application Fields of the MSP 34x0D

In the following sections, a brief overview of the two main TV sound standards, NICAM 728 and German FM-Stereo, demonstrates the complex requirements of a multistandard audio IC.

3.1. NICAM plus FM/AM-Mono

According to the British, Scandinavian, Spanish, and French TV standards, high-quality stereo sound is transmitted digitally. The systems allow two high-quality digital sound channel s to be added to the already existing FM/AM channel. The sound coding follows the format of the so-calle d Near Instanta neous Companding System (NICAM 728). Transmission is performed using Differential Quadrature Phase Shift Keying (DQPSK). Table 3–2 provides some specifications of the sound coding (NI CAM); Table 3–3 offers an overview of the modulation parameters.

In the case of NICAM /FM (AM) mode, there are three different audio channels available: NICAM A, NICAM B, and FM/AM-Mono. NICAM A and B may belong either to a stereo or to a dual-lang uage transmission. Information about operation mode and the quality of the NICAM si gnal can be read by the CCU via the control bus. In the cas e of low quality (h igh biterror rate), the CCU may decide to switch to the analog FM/AM-Mono sound. Alternatively, an automatic NICAM-FM/AM switching may be applied.

3.2. German 2-Carrier System (Dual-FM System)

Since September 1981, stereo and dual-sound programs have been transmitted in Germany using the 2-carrier system. Sound transmission consists of the already existing first sound carrier and a second sound carrier additionally containing an identification signal. More details of this standard are given in Tables 3–1 and 3–4. For D/K and M-Korea, very similar sys tems are used.

Table 3–1: TV standards

TV System Position of Sound

Carrier /MHz

B/G 5.5/5.7421875 FM-Stereo PAL Germany B/G 5.5/5.85 FM-Mono/NICAM PAL Scandinavia, Spain L 6.5/5.85 AM-Mono/NICAM SECAM-L France I 6.0/6.552 FM-Mono/NICAM PAL UK D/K 6.5/6.2578125 D/K1

6.5/6.7421875 D/K2

6.5/5.85 D/K-NICAM

M M-Korea

Satellite Satellite

Note: NICAM demodulation cannot be done with the MSP 3400D

4.5

4.5/4.724212

6.5

7.02/7.2

Sound Modulation

FM-Stereo FM-Mono/NICAM

FM-Mono FM-Stereo

Color System Country

SECAM-East USSR

Hungary

NTSC USA

Korea

PAL PAL

Europe (ASTRA) Europe (ASTRA)

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MSP 34x0D PRELIMINARY DATA SHEET

Table 3–2: Summary of NICAM 728 sound coding characteristics

Characteristics Values

Audio sampling frequency 32 kHz Number of channels 2 Initial resolution 14 bits/sample Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-sample

(1 ms) blocks Coding for compressed samples 2’s complement Preemphasis CCITT recommendation J.17 (6.5 dB attenuation at 800 Hz) Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis

network (2 kHz)

Table 3–3: Summary of NICAM 728 sound modulation parameters

Specification I B/G L D/K

Carrier frequency of digital sound

Transmission rate 728 kbit/s Type of modulation Differentially encoded quadrature phase shift keying (DQPSK) Spectrum shaping

Roll-off factor

Carrier frequency of analog sound component

Power ratio between vision carrier and analog sound carrier

Power ratio between analog and modulated digital sound carrie r

6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz

by means of Roll-off filters 1.0

1.0 0.4 0.4 0.4

6.0 MHz FM mono

10 dB 13 dB 10 dB 16 dB 13 dB

10 dB 7 dB 17 dB 11 dB Hungary Poland

5.5 MHz FM mono

6.5 MHz AM mono 6.5 MHz FM-Mono

terrestrial cable

12 dB 7 dB

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PRELIMINARY DATA SHEET MSP 34x0D

Table 3–4: Key parameters for B/G, D/K, and M 2-carrier sound system

Sound Carriers Carrier FM1 Carri er FM2

B/G D/K M B/G D/K M Vision/sound power ratio 13 dB 20 dB Sound bandwidth 40 Hz to 15 kHz Preemphasis 50 Frequency deviation

µs75µs50µs75µs

±50 kHz ±25 kHz ±50 kHz ±25 kHz

Sound Signal Components

Mono transmission mono mono Stereo transmission (L+R)/2 (L+R)/2 R (L

−R)/2

Dual-sound transmission language A language B

Identification of Transmission Mode on Carrier FM2

Pilot carrier frequency in kHz 54.6875 55.0699 Type of modulation AM Modulation depth 50 % Modulation frequency mono: unmodulated

33 34 39 MHz 59MHz

stereo: 117.5 Hz dual: 274.1 Hz

According to the mixing characteristics

149.9 Hz

276.0 Hz

of the sound IF mixer, the sound IF filter may be omitted.

SAW Filter Sound IF Filter

Sound

Tuner

Vision Demodulator

Composite Video

IF Mixer

SCART Inputs

Fig. 3–1: Typical MSP 34x0D application

Mono

SCART1

SCART2

SCART3 SCART4

MSP 34x0D

Dolby Pro Logic Processor DPL35xxA

I2S2ADRI2S1

ADR Decoder DRP3510A

Loudspeaker

Subwoofer

Headphone

SCART1

SCART2

SCART Outputs

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MSP 34x0D PRELIMINARY DATA SHEET

4. Architecture of the MSP 34x0D

Fig. 4–1 shows a simplified block diagram of the IC. Its architecture is split into three main functional blocks:

1. demodulator and NICAM decoder section

2. digital signal processing (DSP) section performing audio baseband processing

3. analog section containing two A/D-converters, nine D/A-converters, and SCART Switching Facilities.

4.1. Demodulator and NICAM Decoder Section

4.1.1. Analog Sound IF – Input Section

The input pins AN A_IN1+, ANA_IN2+, and ANA_IN offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x0D. By means of bit [8] of AD_CV (see Table6–5 on page 25), either terrestrial or satellite so und IF si gna ls c an b e s el ec ted . T h e a nalog-to-digital conversion of the preselected sound IF signal is done by an A/D converter whose output is used to control an analog autom atic gai n cir cuit (AGC) providing an optimal level for a wide range of input levels. It is possible to switch between automatic gain control and a fixed (setable) in put gain. In the optimal case, the input range of the A/D converter is completely covered by the sound IF source. So me combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, filtering is recommended. It was found, that the high-pass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ and the IF impedance (as s hown in the application dia gram) are sufficient in most cases.

−

Sound IF

ANA_IN1+ ANA_IN2+

Mono

MONO_IN

SC1_IN_L

SCART1

SC1_IN_R

SC2_IN_L

SCART2

SC2_IN_R

SC3_IN_L

SCART3

SC3_IN_R

ADR-Bus I2S_DA_IN1

Demodulator

& NICAM

Decoder

A/D A/D

I2S_DA_OUT

I2S_DA_IN2 I2S_WS

I2S Interface

I2S1/2L/R

FM1/AM FM2 NICAM A NICAM B

SUBWOOFER

IDENT

DSP

HEADPHONE L

HEADPHONE R

SCARTL

SCARTR

I2S_CL XTAL_OUTAUD_CL_OUT

I2S_L/R LOUD-

SPEAKER L LOUD-

SPEAKER R

D/A D/A D/A

D/A D/A

SCART1_L

SCART1_R

SCART2_L

SCART2_R

D/A D/A

XTAL_IN

Crystal PLL

D_CTR_OUT0/1 DACM_L

Loudspeaker

DACM_R

DACM_SUB

Subwoofer

DACA_L

Headphone

DACA_R

SC1_OUT_L

SCART 1

SC1_OUT_R

SC2_OUT_L

SCART 2

SC2_OUT_R

SC4_IN_L

SCART4

SC4_IN_R

SCART Switching Facilities

Fig. 4–1: Architecture of the MSP 34x0D

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PRELIMINARY DATA SHEET MSP 34x0D

4.1.2. Quadrature Mixers

The digital input coming from the integrated A/D converter may contain audio information at a frequency range of theoretically 0 to 9 MHz corresp onding to the selected standards. By means of two programmable quadrature mixers, two different audio sources, for example NICAM and FM-Mono, may be shifted into baseband position. In the following, the two main channels are provided to process either:

– NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2)

simultaneously or, alternatively:

– FM-Mono (Ch2) – FM2 (MSP-Ch1) and FM1 (MSP-Ch2).

Two programmable registers, to be divided up into a low and a high part, determine frequency of the oscillator, which corresponds to the frequency of the desir ed audio carrier.

4.1.3. Low-pass Filtering Block for Mixed Sound IF Signals

Data shaping and/or FM bandwidth limitation is performed by a linear phase fin ite impuls e r es po nse (FIR ) filter. Just like the oscillators’ frequency, the filter coefficients are programmable and are written into the IC by the CCU via the control bus. Thus, for example, different NICAM versions can easily be i mplemented. Two not necessarily different sets of coefficients are required, one for MSP-Ch1 (NICAM or FM2) and one for MSP-Ch2 (FM1 = FM-mono). In a corresponding table several coefficient sets are proposed.

VREFTOP

ANA_IN1+

ANA_IN2+

ANA_IN-

FRAME

NICAMA

DCO2

AD_CV[7:1]

AGC

AD_CV[8]

Pins Internal signal lines (see fig. 4–2)

Demodulator Write Registers

DCO1

Oscillator

FIR1

Mixer

Lowpass

MSP sound IF channel 1 (MSP-Ch1: FM2, NICAM)

MSP sound IF channel 2 (MSP-Ch2: FM1, AM)

Mixer

Oscillator

DCO2

Lowpass

FIR2

Phase and AM Discrimination

Amplitude

Phase and AM Discrimination

MODE_REG[6]

Phase

Amplitude

Differentiator

Phase

DQPSK Decoder

Differentiator

Carrier Detect

AD_CV[9]

Carrier Detect

MSP3410D only

NICAM

Decoder

MODE_REG[8]

Mute

Mute Lowpass

Lowpass

Mixer

ADR

NICAMA

NICAMB

FM2

IDENT

FM1/AM

Fig. 4–2: Architecture of demodulator and NICAM decoder section

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MSP 34x0D PRELIMINARY DATA SHEET

4.1.4. Phase and AM Discrimination

The filtered sound IF signals are demodulated by means of the phase and amplitude discriminator block. On the output, the phase and amplitude is available for further processing. AM signals are derived from the amplitude informati on, whereas the phase informa tion serves for FM and NICAM (DQPSK) demodulation.

4.1.5. Differentiators

FM demodulation is completed by differentiating the phase information output.

4.1.6. Low-pass Filter Block for Demodulated Signals

The demodulated FM an d AM signals are further lowpass filtered and decimated to a final sampling frequency of 32 kHz. The usable bandwidt h of the final baseband signals is about 15 kHz.

4.1.7. High-Deviation FM Mode

By means of MODE_REG [9], the maximum FM deviation can be extended to approximately Since this mode can be applied only for the MSP sound IF channel 2, the correspondi ng matr ices in the baseband processing must be set to sound A. Apart from this, the coefficient sets 380 kHz FIR2 or 500 kHz FIR2 must be chosen for the FIR2. In relat ion to the normal FM mode, the audio level of the high-deviation mode is reduced by 6 dB. The FM prescaler should be adjusted accordi ngly. In h igh-deviation FM mode, neither FM-Stereo nor FM iden tification nor NICAM processing is possible simultaneously.

±360 kHz.

4.1.8. FM Carrier Mute Function in the Dual-Carrier FM Mode

To prevent noise effects or FM identific ation problems in the absence of one of the two FM carriers, the MSP 34x0D offers a carrier detection feature, which must be activated by means of AD_CV[9]. If no FM carrier is available at th e MSPD channel 1, the co rresponding channel FM2 is muted. If no FM carrier is available at the MSPD channel 2, the corresponding channel FM1 is muted.

4.1.9. DQPSK Decoder

In case of NICAM mode, the phase samples are decoded according the DQPSK-coding scheme. The output of this block contains the original NICAM bitstream.

4.1.10. NICAM Decoder

Before any NICAM decoding can star t, the MSP must lock to the NICAM frame structure by searching and synchronizing to the so-called frame alignment words (FAW).

To recon struct the original digital so und samples, the NICAM bitstream has to be descrambled, deinterleaved, and rescaled. Also, bit-error detection an d correction (concealment) is performed in this block.

To facilitate the Central Control Unit CCU to switch the (e.g.) TV set to the actual sou nd mode, control information on the NICAM mode and bit error rate are supplied by the NICAM decoder. It can be read ou t via th e

C bus.

I An automatic switching facility (AUTO_FM) between

NICAM and FM/AM reduces the amount of CCU instructions in case of bad NICAM reception.

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PRELIMINARY DATA SHEET MSP 34x0D

4.2. Analog Section

4.2.1. SCART Switching Facilities

The analog input and output sections include full matrix switching facilities, which are shown in Fig. 4–3. To design a TV set with four pairs of SCART inputs and two pairs of SCART outputs, no external switching hardware is required.

The switches are control led by the ACB bits define d in the audio processi ng interface (see section 7.3 .18. on page 47).

SCART_IN

SC1_IN_L/R

SC2_IN_L/R

SC3_IN_L/R

SC4_IN_L/R

MONO_IN

Mute

ACB[5,9,8]

ACB[6,11,10]

to Audio Baseband Processing (DSP_IN)

SCARTL/R

selected SCART inputs to SCART outputs in the TV set’s stand-by mode.

In case of power-on start or starting from st and -by, the IC switches automatically t o the default configuration, shown in Fig. 4–3. This action takes place after the

C transmission into the DSP part. By transmitting

first I the ACB register first, the individual default setting mode of the TV set can be defined.

4.3. DSP Section (Audio Baseband Processing)

All audio baseband fu nctions are performed by digital signal processing (DSP). The DSP functions are grouped into three proce ss i ng p arts: input pr epr oces s ing, channel source selection, and channel postprocessing (see Fig.4–5 and section 7.).

The input preprocessing is intended to prepare the various signals of all input sourc es in order to form a standardized signal at the input to the channel sel ector. The signals can be adjusted in volume, are processed with the appropriate deemphasis, and are dematrixed if necess ary.

SCART_OUT

SC1_OUT_L/R

Mute

ACB[7,13,12]

SCART_OUT

from Audio Baseband Processing (DSP_OUT)

SC2_OUT_L/R

SCART1_L/R

SCART2_L/R

Mute

Fig. 4–3: SCART switching facilities (see 7.3.18.). Switching positions show the default configuration after power-on reset

Having prepared the signals that way, the channel selector makes it possible to distribute all possible source signals to the desired output channels.

The ability to ro ute in an exter nal c opro cessor for special effects, like surround processing and sound field processing, is of special importance. Routing can be done with each input source and output channel via

S inputs and outputs.

the I All input and outp ut si gnals can be pr ocess ed si multa-

neously with the exception that FM2 cannot be processed at the same time as NICAM. FM ide ntification and adaptive deemphasis are al so not possible simultaneously. Note, that the NICAM input signals are only available in the MSP 3410D version.

4.3.1. Dual-Carrier FM Stereo/Bilingual Detection

For the terrestrial dual-FM carrier systems, audio information can be transmitted in three modes: mono, stereo, or bilingual. To obtain information about the current audio operation mode, the MSP 34x0D detects the socalled identification signal. Information is supplied via the Stereo Detection Register to an external CCU .

4.2.2. Stand-by Mode

If the MSP 34x0D is switched off by first pulling STANDBY Q low, and th en disconnecting the 5 V, but keeping the 8 V power supply (‘Stand-by’-mode), the

IDENT

Demodu-

lation

Stereo

Detection

Filter

Bilingual Detection

Filter

Level

Detect

Level

Detect

Stereo

Detection

−

switches S1, S2, and S3 (see Fig. 4–3) main tain their position and function. Thi s facilitates the copying from

Fig. 4–4: Stereo/bilingual detection

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14 Micronas

MSP 34x0D PRELIMINARY DATA SHEET

Analog Inputs

Demodulated IF Inputs

I2S Bus Inputs

NICAMA

SCARTL

SCARTR

DC level readout FM1

FM1/AM

FM2

NICAMA

NICAMB

I2S1L

I2S1R

I2S2L

I2S2R

Internal signal lines (see Fig. 4–2 and Fig. 4–3)

Adaptive

Deemphasis

50/75 µs

J17

DC level readout FM2

Deemphasis

J17

SCART

Prescale

FM/AM

Prescale

NICAM

Prescale

I2S1

Prescale

I2S2

Prescale

FM-Matrix

Channel Source Select

Loudspeaker

Channel

Matrix

Headphone

Channel

Matrix

SCART1

Channel

Matrix

SCART2

Channel

Matrix

I2S

Channel

Matrix

Quasi-Peak

Channel

Matrix

AVC

Bass/

Treble

Equalizer

Bass/

Treble

Quasi-Peak

Detector

Beeper

Quasi peak readout L

Quasi peak readout R

Loudness

Comple-

mentary

Highpass

Lowpass

Spatial Effects

Balance

Level

Adjust

Balance

Volume

Loudspeaker L

Loudspeaker R

Subwoofer

Headphone L

Headphone R

SCART1_L

SCART1_R

SCART2_L

SCART2_R

I2SL

I2SR

Loudspeaker Outputs

Headphone Outputs

SCART Outputs

I2S Outputs

Fig. 4–5: Audio baseband processing (DSP firmware)

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PRELIMINARY DATA SHEET MSP 34x0D

Table 4–1: Some examples for recommended channel assignments for demodulator and audio processing part

Mode MSP Sound IF-

Channel 1

B/G-Stereo FM2 (5.74 MHz): R FM1 (5.5 MHz): (L+R)/2 B/G Stereo Speakers: FM Stereo B/G-Bilingual FM2 (5.74 MHz): Sound B FM1 (5.5 MHz): Sound A No Matrix Speakers: FM

NICAM-I-ST/ FM-mono

Sat-Mono not used FM (6.5 MHz): mono No Matrix Speakers: FM Sound A Sat-Stereo 7.2 MHz: R 7.02 MHz: L No Matrix Speakers: FM Stereo Sat-Bilingual 7.38 MHz: Sound C 7.02 MHz: Sound A No Matrix Speakers: FM

Sat-High Dev. Mode

NICAM (6.552 MHz) FM (6.0 MHz): mono No Matrix Speakers: NICAM

don’t care 6.552 MHz No Matrix Speakers: FM

4.4. Audio PLL and Crystal Specifications

The MSP 34x0D requires a 18.432MHz (12 pF, parallel) crystal. The clock supply of the whole system depends on the MSP 34x0D operation mode:

1. FM-Stereo, FM-Mono: The system clock runs free on the crystal’s

18.432 MHz.

2. NICAM: An integrated clock PLL uses the 364 kHz baud rate, accomplished in the NICAM demodulator block to lock the system clock to the bit rate, respectively, 32-kHz sampling rat e of the NICAM transmitter. As a result, the whole audio syst em is supplied with a controlled 18.432 MHz clock.

S slave operation:

3. I In this case, the system clock is locked to a synchronizing signal (I2S_CL, I2S_WS) supplied by the coprocessor chip.

MSP Sound IFChannel 2

FMMatrix

ChannelSelect

H. Phone: FM

Channel Matrix

Speakers: Sound A H. Phone: Sound B

Speakers: Stereo H. Phone: Sound A

Speakers: Sound A H. Phone: Sound B=C

Speakers: Sound A H. Phone: Sound A

4.5. ADR Bus Interface

For the ASTRA Digital Radio System (ADR), the MSP 34x0D performs preprocess ing, as ther e are car rier selection an d filteri ng. Via the 3-line AD R bus, the resulting signals are transferred to the DRP 3510A, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 34x0D should be provided on a feature connector:

– AUD_CL_OUT – I2S_DA_IN1 or I2S_DA_IN2 – I2S_DA_OUT – I2S_WS – I2S_CLK – ADR_CL – ADR_WS

Remark on using the crystal:

– ADR_DA

External cap acitors at each crys tal pin to ground are required (see General Crystal Recommendations on page 69).

4.6. Digital Control Output Pins

The static level of two output pins of the MSP 34x0D (D_CTR_OUT0/1) is switchable between HIGH and LOW by means of the I trolling of external hardware-controlled switches or other devices via I

C bus. This enables the con-

C bus (see section 7.3.18. on page

47).

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MSP 34x0D PRELIMINARY DATA SHEET

4.7. I2S Bus Interface

By means of this standardized interface, additional feature processors can be connected to the MSP 34x0D. Two possible format s ar e supp or te d: Th e standard mode (MODE _REG[4]=0) select s the SONY format, where the I2S_WS signal ch anges at the word boundaries. The so-called PHILIPS format, which is characterized by a change of th e I2S_WS signal one I2S_CL period before the word boundaries, is selected by setting MODE_REG[4]=1.

The MSP 34 x0D no rma lly ser ves as th e master on the

S interface. Here, the clock and word strobe lines are

I driven by the MSP 34x0D. By setting MODE_REG[3]=1, the MSP 34x0D is switched to a slave mode. Now, these lines are input to the MSP 34x0D and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICA M operation is not possible in th is m ode .

S bus interface consists of five pins:

The I

1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32 kHz) are transmitted.

2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.

3. I2S_CL: Gives the timing for the transmission of I

S serial

data (1.024 MHz).

4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.

A precise I

S timing diagram is shown in Fig. 4–6.

(Data: MSB first)

I2S_WS

SONY Mode

PHILIPS Mode

I2S_CL

I2S_DAIN

I2S_DAOUT

R LSB L MSB

R LSB

L MSB

Detail C

I2S_CL

I2S_WS as INPUT

PHILIPS/SONY Mode programmable by MODE_REG[4]

Detail A

16 bit left channel

Detail B

1/F

I2SCL

I2SWS1

I2SWS2

I2SWS

Detail C

SONY Mode

PHILIPS Mode

L LSB

R MSB

L LSB

R MSB

Detail A,B

I2S_CL

I2S_DA_IN

16 bit right channel

16 bit right channel16 bit left channel

I2S1

R LSB L LSB

I2S2

I2S_WS as OUTPUT

Fig. 4–6: I

I2S5

S bus timing diagram

I2S6

I2S_DA_OUT

I2S3

I2S4

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PRELIMINARY DATA SHEET MSP 34x0D

5. I2C Bus Interface: Device and Subaddresses

As a slave receiver, the MSP 34x0D can be controlled

C bus. Access to internal memory locations is

via I achieved by subaddressing. The demodulator and the DSP processor par ts have two separate subaddressing register banks.

In order to allow for more MSP 34x0D ICs to be connected to the control bus, an ADR_SEL pin has be en implemented. With ADR_SEL pulled to HIGH, LOW, or left open, the MSP 34x0D responds to changed device addresses. Thus, three identical devices can be selected.

By means of the RESET bit in the CONTROL register, all devices with the same device address are reset.

The IC is selected by asserting a special device address in the addre ss part of an I

C transmission . A device address pair is def ined as a write add ress (80, 84, or 88

) and a read address (81, 85, or 89

hex

(see Table 5–1). Writin g is don e by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the device write addr ess, followed by the subaddress byte and two addres s bytes. Without sendi ng a stop condition, reading of the addressed data is completed by sending the device read a ddress (81, 85, or

) and reading two bytes of data (see Fig. 5–1:

hex

C Bus Protocol” and section 5.2. “Proposal for

“I MSP 34x0D I

C Telegrams”).

Due to the internal architecture of the MSP 34x 0D, the IC cannot react immediately to an I

C request. The typical response time is about 0.3 ms for the DSP processor part and 1 ms for the demodulator part if NICAM processing is active. If the receiver (MSP) can’t receive another complete byte of data until it has performed some other function; for example, servicing an internal interrupt, it can hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by ’Wait’ in section 5.1. The maximum wait period of the MSP during normal operation mode is less than 1 ms.

C bus error caused by MSP hardware problems:

I In case of any internal error, the MSPs wait period is extended to 1.8 ms. Afterwards, the MSP does not acknowledge (NAK) the device address. The data line will be left HIGH by the MSP and the clock line will be released. The master can then generate a STOP condition to abort the transfer.

)

By means of NAK, the master is able to recognize the error state and to reset the IC via I

C bus. While transmitting the reset protoc ol (see section 5.2.4. on page

19) to ‘CONTROL’, the master must ignore the not- acknowledge bits (NAK) of the MSP.

A general timing diagram of the I

C Bus is shown in Fig. 5 –2 on page 19.

Table 5–1: I

C Bus Device Addresses

ADR_SEL Low High Left Open Mode Write Read Write Read Write Read

MSP device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex

Table 5–2: I2C Bus Subaddresses

Name Binary Value Hex Value Mode Function

CONTROL 0000 0000 00 W software reset TEST 0000 0001 01 W only for internal use WR_DEM 0001 0000 10 W write address demodulator RD_DEM 0001 0001 11 W read address demodulator WR_DSP 0001 0010 12 W write address DSP RD_DSP 0001 0011 13 W read address DSP

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MSP 34x0D PRELIMINARY DATA SHEET

Table 5–3: Control Register (Subaddress: 00 hex)

Name Subaddress MSB 14 13..1 LSB

CONTROL 00 hex 1 : RESET

0 : normal

5.1. Protocol Description

Write to DSP or Demodulator

Swrite

device

address

Wait ACK subaddr AC K addr byte

Read from DSP or Demodulator

Swrite

device

address

ACK subaddr ACK addr byte

Wait

ACK addr byte

high

000

ACK addr byte

ACK S read

low

ACK data byte

device

address

Wait

high

ACK data byte

high

low

ACK data byt e

low

ACK P

NAK P

Write to Control or Test Registers

Swrite

Note: S = I

device

address

P = I

C bus Start Condition from master

C bus Stop Condition from master

Wait ACK subaddr ACK data byte high ACK data byte low ACK P

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (

or master (

=CCU, hatched)

NAK = Not-Acknowledge Bit: HIGH on I2C_DA from master (

or from MSP indicating internal error state

Wait = I

I2C_DA

C clock line held low by the slave (=MSP) while interrupt is serviced (<1.8 ms)

1 0

S P

I2C_CL

Fig. 5–1: I

C bus protocol (MSB first; data must be stable while clock is high)

=MSP, gray)

=CCU, hatched) to indicate ‘End of Read’

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PRELIMINARY DATA SHEET MSP 34x0D

(Data: MSB first)

I2C

I2C_CL

I2C4

I2C3

I2C1

I2C_DA as input

I2C_DA as output

Fig. 5–2: I

C bus timing diagram

5.2. Proposal for MSP 34x0D I

5.2.1. Symbols

daw write device address dar read device address < start condition > stop condition aa address byte dd data byte

I2C5

C Telegrams

I2COL2

I2C6

I2COL1

I2C2

5.2.2. Write Telegrams

<daw 00 d0 00> write to CONTROL register <daw 10 aa aa dd dd> write data into demodulator <daw 12 aa aa dd dd> write data into DSP

5.2.3. Read Telegrams

<daw 11 aa aa <dar dd dd> read data from demodulator <daw 13 aa aa <dar dd dd> read data from DSP

5.2.4. Examples

<80 00 80 00> RESET MSP statically <80 00 00 00> clear RESET <80 12 00 08 01 20> set loudspeaker channel source

to NICAM and matrix to STEREO

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MSP 34x0D PRELIMINARY DATA SHEET

5.3. Start-Up Sequence: Power-Up and I2C-Controlling

After power-on or RESET (see Fig. 5–3), the IC is in an inactive state. The CCU has to transmit the required coefficient set for a given operation via the

C bus. Initialization should start with the demodulator

I part. If required for any reason, the audio processin g part can be loaded before the demodulator part.

DVSUP AVSUP

4.5 V

RESETQ

0.7×DVS UP

0.45...0.55

Internal Reset

t/ms

Low-to-High Threshold

×DVSUP

High-to-Low Threshold

t/ms

Reset Delay >2 ms

High

Low

t/ms

Note: The reset should not reach high level before the oscillator has

Power-Up Reset: Threshold and Timing (Note: 0.7×DVSUP means 3.5 Volt with DVSUP=5.0 Volt)

started. This requires a reset delay of >2 ms

Fig. 5–3: Power-up sequence

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PRELIMINARY DATA SHEET MSP 34x0D

6. Programming the Demodulator and NICAM Decoder Section

6.1. Short-Programming and General

Programming of the Demodulator Part

The demodulator pa rt of the MSP 34x0D can b e programmed in two different modes:

1. Demo du lat or Sh ort-P r o gramming provides a com-

fortable way to set up the demodulator for many terrestrial TV sound standards with one single I

C bus transmission. The coding is listed in section 6.4.1. If a parameter does not coincide with the individual programming concept, it simply can be overwritten by using the General Programming Mode. Some bits of the registers AD_CV (see section 6.5.1. on page 25) and MODE_REG (see section 6.5.2. on page 27) are not affected by the short-programming. They must be transmitted once if their reset status does not fit. The Demodulator Short-Programming is not compatible to MSP 3410B and MSP 3400C.

Autodetection for terrestrial TV standards is part of the Demodulator Short-Programming. This feature enables the detection and set-up of the actual TV sound standard wi thin 0.5 s. Since the detected standard is readable by the contro l processor, the Autodetection feature is mainly re commended for the primar y set-up of a TV set: after having once de termined the corresponding TV channels, their sound standards can be stored and later on programmed by the Demodulator Short -Programming (see s ection 6.4.1. on page 23 and section 6.6.1. on page 32).

2. General Programming ensures the so ftware-compatibility to other MS Ps. It offers a very flexible way to apply all of the M SP 34x0 D demodulator facilities. All registers except 0020

(Demodulator Short-Pro-

hex

gramming) have to be written with values corresponding to the individual requirements. For satellite applications, with their many variations, this mode must be selected.

All transmission s on the control bus are 16 bits wi de. However, data for the de modulator par t have only 8 or 12 significant bits. These data have to be inserted LSB-bound and filled with zero bits into the 16-bit transmission word. Table 4–1 explains how to assign FM carriers to the MSP Sound IF channels and the corresponding matrix modes in the audio processing part.

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MSP 34x0D PRELIMINARY DATA SHEET

6.2. Demodulator Write Registers: Table and Addresses

Table 6–1: Demodulator Write Registers; Subaddress: 10

Demodulator Write Registers

Demodulator ShortProgramming

AUT O_FM/AM 0021 Only for NICAM: Automatic switching between NICAM and FM/AM in case

Write Registers n ec es sa ry for General Programming Mode only AD_CV 00BB input selection, configuration of AGC, Mute Function and selection of

MODE_REG 0083 mode register FIR1

FIR2 DCO1_LO

DCO1_HI DCO2_LO

DCO2_HI

Address (hex)

0020 Write into this register to apply Demodulator Short Programming (see sec-

0001 0005

0093 009B

00A3 00AB

Function

tion 6.4.1. on page 23). If the internal setting coincidences with the individual requirements no more of the remaining Demodulator Write Registers have to be transferred.

of bad NICAM reception (see section 6.4.2. on page 24)

A/D converter, FM Carrier Mute on/off

filter coefficients channel 1 (6 filter coefficients channel 2 (6

increment channel 1 low part increment channel 1 high part

increment channel 2 low part increment channel 2 high part

; these registers are not readable!

hex

× 8 bit) × 8 bit), + 3 × 8 bit offset (total 72 bits)

PLL_CAPS 001F switchable PLL capacitors to tune open-loop frequency; to use only if

NICAM of MODE_REG = 0 ; normally not of interest for the customer

6.3. Demodulator Read Registers: Table and Addresses

Table 6–2: Demodulator Read Registers; Subaddress: 11

Demodulator Read Registers

Result of Autodetection

C_AD_BITS 0023 NICAM Sync bit, NICAM C bits, and three LSBs of additional data bits ADD_BITS 0038 NICAM: bit [10:3] of additional data bits CIB_BITS 003E NICAM: CIB1 and CIB2 control bits ERROR_RATE 0057 NICAM error rate, updated with 182 ms CONC_CT 0058 only to be used in MSPB compatibility mode

Address (hex)

007E (see Table 6–13)

Function

; these registers are not writable!

hex

FAWCT_IST 0025 only to be used in MSPB compatibility mode PLL_CAPS 021F Not for customer use. AGC_GAIN 021E Not for customer use.

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PRELIMINARY DATA SHEET MSP 34x0D

6.4. Demodulator Write Registers for Short-Programming: Functions and Values

In the following, the functions of some registers are explained and their (default) values are defined:

6.4.1. Demodulator Short-Programming

Table 6–3: MSP 34x0D Demodulator Short-Programming

Demodulator Short-Programming 0020

hex

TV Sound Standard Internal Setting Description Code

(hex)

AD_CV

(see Table 6–5)

MODE_

REG

(see Table 6–8)

DCO1 (MHz)

DCO2 (MHz)

FIR1/2 Coefficients

Identification Mode

Autodetection 0001 Detects and sets one of the standards listed below, if available. Results are to be

read out of the demodulator read register “Result of Autodetection” (section 6.6.1.)

M Dual-FM 0002 AD_CV- FM M1 4.72421 4. 5

Reset, then Standard M

see T able 6–11:

B/G Dual-FM 0003 AD_CV-FM M1 5.74218 5.5 D/K1 Dual-FM 0004 AD_CV-FM M1 6.25781 6.5

Terrestrial TV Standards

Reset, then Standard B/G

D/K2 Dual-FM 0005 AD_CV-FM M1 6.74218 6.5

0006/ 0007

reserved for future dual-FM standards

AUTO_

FM/AM B/G NICAM FM 0008 AD_CV-FM M2 5.85 5.5 L NICAM AM 0009 AD_CV-AM M3 5.85 6.5 I NICAM FM 000A AD_CV-FM M2 6.552 6.0

see T able 6–11: Terrestrial TV Standards

D/K NICAM FM 000B AD_CV-FM M2 5.85 6.5

>000B reserved for future NICAM Standards

corresponds to the actual setting of AUTO_FM (Address = 0021

bits of AD_CV or MODE_REG, which are not affected by the short-programming, must be transmitted

hex

)

separately if their reset status does not fit.

Note: All parameters in the DSP section (Audio Baseband Processing), except the identification mode register,

are not affected by the Demodulator Short-Programming. They still have to be defined by the control processor.

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MSP 34x0D PRELIMINARY DATA SHEET

6.4.2. AUTO_FM/AM: Automatic Switching

between NICAM and FM/AM-Mono

In case of bad NICAM transmission or loss of the NICAM carrie r, the MSPD offers a comfor table mod e to switch back to the FM/AM-Mono signal. If automatic switching is active, the MSP internally evaluates the ERROR_RATE. All output channels which are assigned to the NICAM source are switched back to the FM/AM-Mono source without any further CCU instruction, if the NICAM carrier fails or the ERROR_RATE exceeds the definable threshold.

Note, that the channel matrix of the corresponding output channels must be set according to the NICAM mode and need not be changed in the FM/AM fall-back case. An appropriate hysteresis algorithm avoids oscillating effects. The MSB of the Register C_AD_BITS (Addr: 0023 FM/AM Status (see section 6.6.2. on page 32).

) informs about the actual NICAM

hex

There are two possibilities to define the threshold deciding for NICAM or FM/AM-Mono (see Table 6–4):

1. default value of the MSPD (internal threshold = 700, i.e. switch to FM/AM if ERROR_RATE > 700)

2. definable by the customer (recommendable range: threshold = 50...2000, i.e. Bits [10...1] = 25...1000).

Note: The auto_FM feature is only active if the NICAM bit of MODE_REG is set.

Table 6–4: Coding of automatic NICAM FM/AM switching (reset status: mode 0)

Mode Auto_FM [11...0]

Addr. = 0021

0 default

1 Bit [0] = 1

2 Bit [0] = 1

3 Bit [11] = [0] = 1

Bit [0] = 0 Bits [11...1] = 0

Bit [11...1] = 0

Bit [10...1] = 25..1000 int Bit [11] = 0

Bit [10...1] = 0

hex

= threshold/2

Selected Sound at the NICAM Channel Select

always NICAM none Compatible to MSP 3410B,

NICAM or FM/AM, depending on ERROR_RATE

always FM/AM none Forced FM-Mono mode, i.e.

Threshold Comment

700 dec automatic switching with

set by customer

i.e. automatic switching is disabled

internal threshold

automatic switching with external threshold

automatic switching is disabled

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PRELIMINARY DATA SHEET MSP 34x0D

6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values

6.5.1. Re gister ‘AD_CV’

Table 6–5: AD_CV Register (reset status: all bits are “0”)

AD_CV 00BB

hex

Set by Short-Programming

Bit Meaning Settings AD_CV-FM AD_CV-AM

AD_CV [0] not used must be set to 0 0 0 AD_CV [6...1] Reference level in case of Auto-

101000 100011 matic Gain Control = on (see Table 6–6). Constant gain factor when Automatic Gain Control = off (see Table 6–7)

AD_CV [7] Determination of Automatic Gain or

Constant Gain

AD_CV [8] Selection of Sound IF source 0 = ANA_IN1+

0 = constant gain 1 = automatic gain

not affected not affected

1 = ANA_IN2+

AD_CV [9] MSP Carrier Mute Function

(Must be switched off in High Deviation Mode)

AD_CV [15

...10] not used must be set to 0 000000 000000

0 = off: no mute 1 = on: mute as described in section 4.1.8. on page 12

Table 6–6: Reference values for active AGC (AD_CV[7] = 1)

Application Input Signal Contains AD_CV [6...1]

Ref. Value

AD_CV [6...1] (dec)

Range of Input Signal at pin ANA_IN1+ and ANA_IN2+

Terrestrial TV Dual-Carr. FM NICAM/FM NICAM/AM

2 FM Carriers 1 FM and 1 NICAM Carrier 1 AM and 1 NICAM Carrier

101000 101000 100011

40 40 35

0.10

− 3V

0.10 − 3V

0.10 − 1.4 V

pp pp

recommended:

− 0.8 V

NICAM only

1 NICAM Carrier only

SAT 1 or more

0.10

010100

0.05 − 1.0 V

100011 35 0.10 − 3V

pp pp

FM Carriers

ADR FM a. ADR carriers see DRP 3510A data sheet

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result.

Due to the robustness of the internal processing, the IC works up to and even more than 3 V

, if norm conditions

of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may appear.

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MSP 34x0D PRELIMINARY DATA SHEET

Table 6–7: AD_CV parameters for constant input gain (AD_CV[7]=0)

Step AD_CV [6...1]

Constant Gain

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110

Gain Input Level at pin ANA_IN1+ and ANA_IN2+

3.00 dB

maximum input level: 3 V

(FM) or 1 Vpp (NICAM)

3.85 dB

4.70 dB

5.55 dB

6.40 dB

7.25 dB

8.10 dB

8.95 dB

9.80 dB

10.65 dB

11.50 dB

12.35 dB

13.20 dB

14.05 dB

14.90 dB

15 16 17 18 19 20

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result.

001111 010000 010001 010010 010011 010100

Due to the robustness of the internal processing, the IC works up to and even more than 3 V

15.75 dB

16.60 dB

17.45 dB

18.30 dB

19.15 dB

20.00 dB

maximum input level: 0.14 V

, if norm conditions

of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may appear.

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PRELIMINARY DATA SHEET MSP 34x0D

6.5.2. Re gister ‘MODE_REG’

The register ‘MODE_REG’ contains the control bits determining the operation mode of the MSP 34x0D; Table 6–8 explains all bit positions.

Table 6–8: Control word ‘MODE_REG’; reset status: all bits are “0”

MODE_REG 0083

hex

Set by

Short-Programming

Bit Function Comment Definition M1 M2 M3

[0] not used 0 : strongly recommended 0 0 0 [1] DCTR_TRI Digital control out

0/1 tri-state

[2] I2S_TRI I

S outputs tri-state

(I2S_CL, I2S_WS,

0 : active 1 : tri-state

XXX

I2S_DA_OUT)

[3] I

S Mode

[4] I2S_WS Mode WS due to the Sony or

[5] AUD_CL_OUT Switch

Master/Slave mode of the I

S bus

Philips Format

Audio_Clock_Output

0 : Master 1 : Slave

0 : Sony 1 : Philips

0 : on 1 : tri-state

XXX

to tri-state

[6] NICAM

Mode of MSP-Ch1 0 : FM

011

1 : Nicam [7] not used 0 : strongly recommended 0 0 0 [8] FM AM Mode of MSP Ch2 0 : FM

001

1 : AM [9] HDEV High Deviation Mode

(channel matrix must be

0 : normal

1 : high deviation mode

000

sound A) [11...10] not used 0 : strongly recommended 00 00 00 [12] MSP Ch1 Gain see also Tab le 6–11 0 : Gain = 6 dB

000

1 : Gain = 0 dB

[13] FIR1 Filter Coeff.

Set

[14] ADR Mode of MSP Ch1/

[15] AM Gain Gain for AM

In case of NICAM operation, I2S slave mode is not possible. In case of I

S slave mode, no synchronization to NICAM is allowed.

6.5.3. FIR Parameter

The following data values (see Table 6–10) are to be transferred 8 bits at a time embedded LSB-bound in a 16-bit word.

The loading sequences mu st be obeyed. To change a

−:− High-Deviation FM

Table 6–10: Loading sequence for FIR coefficients

FIR1 0001 No. Symbol Name Bits Value

NICAM/FM2_Coeff. (5) 8

(MSP Ch1: NICAM/FM2)

hex

coefficient set, the compl ete block FIR1 or FIR2 must be transmitted.

Note: For compatibility with MSP 3410B, IMREG1 and IMREG2 have to be transmitted. The value for

2 NICAM/FM2_Coeff. (4) 8 3 NICAM/FM2_Coeff. (3) 8 4 NICAM/FM2_Coeff. (2) 8

IMREG1 and IMREG2 is 004. Due to the partitioning to 8-bit units, the values 04

hex

, 40

, and 00

hex

arise.

5 NICAM/FM2_Coeff. (1) 8 6 NICAM/FM2_Coeff. (0) 8

see Table 6–11

FIR2 0005 No. Symbol Name Bits Value

1IMREG1 8 04 2 IMREG1 / IMREG2 8 40 3IMREG2 8 00 4 FM/AM_Coef (5) 8 5 FM/AM_Coef (4) 8 6 FM/AM_Coef (3) 8 7 FM/AM_Coef (2) 8 8 FM/AM_Coef (1) 8 9 FM/AM_Coef (0) 8

(MSP Ch2: FM1/AM )

hex

see Table 6–11

28 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

Table 6–11: 8-bit FIR coefficients (decimal integer) for MSP 34x0D (reset status: all coefficients are “0”)

Coefficients for FIR1 0001

B/G-, D/KNICAM-FM

and FIR2 0005

hex

Terrestrial TV Standards

I-

NICAM-FML-NICAM-AM

B/G-, D/K-, M-Dual FM

FM Satellite

FIR filter corresponds to a band-pass with a bandwidth of B = 130 to 500 kHz

130

180 kHz

200 kHz

kHz

280 kHz

380 kHz

500 kHz

frequency

Autosearch

Coef(i) FIR1 FIR2 FIR1 FIR2 FIR1 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2

2 3 10 48

−2323−2 −43 7393−8 −1 −1 −1

−818 418−8 −12 18 53 18 18 −8 −9 −1 −1

−10 27 −627−10 −927 6428274−16 −8 −8

−4 48 10 23 48 119 47 48 36 5 2 2

4 50 66 40 66 50 79 66 101 55 66 78 65 59 59 5 86 72 94 72 86 126 72 127 64 72 107 123 126 126

Mode-

0 0 0 0 111111 0

REG[12]

Mode-

0 0 0 1 111111 0

REG[13]

For compatibility, except for the FIR2 AM and the autosearch sets, the FIR filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP data sheet.

Micronas 29

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MSP 34x0D PRELIMINARY DATA SHEET

6.5.4. DCO Registers

For a chosen TV standard, a corresponding set of 24-bit registers det ermining the mixing frequencies of the quadrature mixers, has to be written in to the IC. In Table 6–12, some examples of DCO registers are listed. It is necess ary to divide them up int o low part and high part. The formula for the calculation of the registers for any chosen IF frequency is as follows:

INCR

= int(f / fs ⋅ 224)

dec

with: int = integer function

f = IF frequency in MHz

= sampling frequency (18.432 MHz)

Conversion of INCR into hex format and separation of the 12-bit low and high parts lead to the required register values (DCO1_HI or _LO for MSP Ch1, DCO2_HI or LO for MSP Ch2).

Table 6–12: DCO registers for the MSP 34x0D (reset status: DCO_HI/LO = “0000”)

DCO1_LO 0093

Freq. [MHz] DCO_HI

hex

, DCO1_HI 009B

hex

DCO_LO

hex

; DCO2_LO 00A3

hex

Freq. [MHz] DCO_HI

, DCO2_HI 00AB

hex

4.5 03E8 0000

5.04

5.5

5.58

5.7421875

0460 04C6 04D8 04FC

0000 038E 0000 00AA

5.76

5.85

5.94

0500 0514 0528

hex

DCO_LO

0000 0000 0000

hex

6.0

6.2

6.5

6.552

0535 0561 05A4 05B0

0555 0C71 071C 0000

6.6

6.65

6.8

05BA 05C5 05E7

0AAA 0C71 01C7

7.02 0618 0000 7.2 0640 0000

7.38 0668 0000 7.56 0690 0000

30 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

6.6. Demodulator Read Registers: Functions and Values

All registers except C_AD_ BITS are 8 bits wide. They can be read out of the RAM of the MSP 34x0D.

All transmissions take place in 16-bit words. The valid 8 bit data are the 8 LSBs of the received data word.

To enable appr opriate switching of the channel select matrix of the baseband p rocess ing part, the NICAM or FM identification parameters must be read and evaluated by the CCU. The FM iden tification registers are described in section 7.2. on page 39. To handle the NICAM sound and to observe the NICAM quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the CCU. Additional data bits and CIB bits, if sup plied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS.

Observing th e presence and qual ity of NICAM can be delegated to the MSP 3410D, if the automatic switching feature (AUTO_FM, section 6.6.1. on page 32) is applied.

Table 6–13: Result of Autodetection

Code (Data) hex

Result of Autodetect 007E

Detected TV Sound Standard Note: After detection, the detected standard is set automatically according to Table 6–3.

hex

>07FF autodetect still active 0000 no TV sound standard was detected; select sound standard manually 0002 M Dual FM, even if only FM1 is available 0003 B/G Dual FM, even if only FM1 is available 0008 B/G FM NICAM, only if NICAM is available

L_AM NICAM, whenever a 6.5-MHz carrier is detected, even if NICAM is not available. If also D/K might be possible, a decision has to be made according to the video mode:

Video = SECAM_EAST

0009

Video = SECAM_L necessary

→ no more activities

CAD_BITS[0] = 0 CAD_ BITS[ 0] = 1

To be set by means of the short programming mode:

D/K1 or D/K2 (see section 6.6.1.)

D/K-NICAM (standard 00B

hex

) 000A I-FM-NICAM, even if NICAM is not available Note: Similar as for the Demodulator Short-Programming, the Autodetection does not affect most of the para-

meters of the DSP section (Audio Baseband Processing): The following exceptions are to be considered:

− identification mode: Autodetection resets and sets the corresponding identification mode

− Prescale FM/AM and FM matrix and Deemphasis FM are undefined after Autodetection

Micronas 31

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MSP 34x0D PRELIMINARY DATA SHEET

6.6.1. Autodetection of T errestrial TV A udio Standar ds

By means of Autodetect, the MS P 34x0D offers a simple and fast (<0.5 s) facility to detect the actual TV audio standard. The algorithm checks for the FMMono and NICAM carriers of all common TV sound standards. The following notes must be considered when applying the Autodetect feature:

1. Since there is no way to distinguish between AM and FM carrier, a carrier detected at 6.5 MHz is interpreted as an AM carrier. If video detection results in SECAM East, the MSPD result “9” of Autodetect must be reinterpreted as “B

” in case of

hex

CAD_BITS[0] = 1, or as “4” or “5” by using the demodulator short programming mode. A simple decision can be made between the two D/K FM stereo standards by setting D/K1 and D/K2 using the shor t programming mode a nd checking the iden tification of both versions (s ee Table 6–13 on page 31).

2. During active Autodetect, no I

C transfers besides reading the autodetect result are recommended. Results exceeding 07F F

indicate an active auto-

hex

detect.

3. The results are to be underst ood as static information, i.e. no evaluation of FM or NICAM identification concernin g the dynamic mode (ster eo, bilingual, or mono) are done.

4. Before switching to Autodetect, the audio processing part sh ould be muted. Do not forget to demute after ha ving received the result.

6.6.2. C_AD_BITS

Table 6–14: NICAM operation modes as defined by

the EBU NICAM 728 specification

C4 C3 C2 C1 Operation Mode

0 0 0 0 Stereo sound (NICAM A/B),

independent mono sound (FM 1)

0 0 0 1 Two independent mono signals

(NICAM A, FM1)

0 0 1 0 Three independent mono

channels (NICAM A, NICAM B,

FM1) 0 0 1 1 Data transmission only; no audio 1 0 0 0 Stereo sound (NICAM A/B), FM1

carries same channel 1 0 0 1 One mono signal (NICAM A).

FM1 carries same channel as

NICAM A 1 0 1 0 Two independent mono channels

(NICAM A, NICAM B). FM1

carries same channel as

NICAM A 1 0 1 1 Data transmission only; no audio x 1 x x Unimplemented sound coding

option (not yet defined by EBU

NICAM 728 specification)

AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM

NICAM operation mode con trol bits a nd A[2...0] of th e additional data bits.

Format:

MSB C_AD_B ITS 0023

11...76543210

Auto

... A[2] A[1] A[0] C4 C3 C2 C1 S

_FM

hex

LSB

Important: “S” = Bit[0] indicates correct NICAM syn-

chronization (S=1). If S=0, the MSP 3410D has not yet synchronized correctly t o frame and sequence, or has lost sync hron iz ati on. The remain in g r ea d registers are therefore not valid. The MSP 3410D mutes the NICAM output automatically and tries to synchronize again as long as MODE_REG[6] is set.

The operation mode is coded by C4...C1 as shown in Table 6–14.

6.6.3. ADD_BITS [10...3] 0038

hex

Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system.

Format:

MSB ADD_BITS 0038

76543210

A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3]

hex

LSB

6.6.4. CIB_BITS

Cib bits 1 and 2 (see NICAM 728 specifications). Format:

MSB CIB_BITS 003E

76543210 xxxxxxCIB1CIB2

hex

LSB

32 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

6.6.5. ERROR_RATE 0057

hex

Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The initial and maximum value of ERROR_RATE is 2047. This value is also active, if the NICAM bit of MODE_REG is not se t. Sinc e the value i s achieved by filtering, a certain transition time (appr. 0.5 sec) is unavoidable. Acceptable audio may have error_rates up to a value of 700

. Individual evaluation of this

dec

value by the CCU and an appropriate threshold may define the fallback mode from NICAM to FM/AM-Mono in case of poor NICAM reception.

The bit error rate per second (B ER) can be calculat ed by means of the following formula:

BER = ERROR_RATE

× 12.3 × 10

−6

If the automatic switching feature is applied (AUTO_FM; section 6.4.2. on page 24), reading of ERROR_RATE can be omitted.

6.6.6. CONC_CT (for compatibility with MSP 3410B)

This register contains the actual number of bit errors of the previous 728-bit data frame. Evaluation of CONC_CT is no longer recommended.

6.6.7. FAWCT_IST (for compatibility with MSP 3410B)

6.6.9. AGC_GAIN

It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this regi ster is not of inter est for the customer.

AGC_GAIN 021E

max. amplification

hex

0001 0100 14

hex

(20 dB) min. amplification

0000 0000 00

hex

(3 dB)

6.7. Sequences to Transmit Parameters and to Start Processing

After having been switched on, the MSP h as to be ini tialized by transmitting the parameters according to the LOAD_SEQ_1/2 (see Table 6–15 on page 34). The data are immedia tely active after trans mission i nto the MSP. It is no longer necessary to transmit LOAD_REG_1/2 or LOAD_REG_1 as it was for MSP 34x0B. Nevertheless, transmission of LOAD_REG_1/2 or LOAD_REG_1 does no harm.

For NICAM operation, the following steps listed in ‘NICAM_WAIT, _READ, and _CHECK’ in Table 6–15 must be taken.

For compatibility with MS P 3410B thi s value equal s 12 as long as NICAM quality is sufficient. It decreases to 0 if NICAM reception gets poor. Evaluation of FAWCT_IST is no longer recommended.

6.6.8. PLL_CAPS

It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer.

PLL_CAPS 021F

minimum frequency 0111 1111 7F nominal frequency 0101 0110 56

hex

RESET

maximum frequency 0000 0000 00

hex

For FM-Stereo operation, th e evaluation of the id entifi cation signal must be performed. For a positive identification check, the MSP 3410D sound ch annels have to be switched corresponding to the detected operation mode.

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MSP 34x0D PRELIMINARY DATA SHEET

Table 6–15: Sequences to initialize and start the MSP 34x0D

LOAD_SEQ_1/2: General Initialization General Programming Mode Demodulator Short Programming

Write into MSP 34x0D:

1. AD_CV

2. FIR1

3. FIR2

Write into MSP 34x0D: For example: Addr: 0020

, Data 0008

hex

Alternatively, for terrestrial reception, the Autodetect feature can be applied.

4. MODE_REG

5. DCO1_LO

6. DCO1_HI

7. DCO2_LO

8. DCO2_HI

AUDIO PROCESSING INIT

Initialization of Audio Baseband Processing section, which may be customer-dependent (see section 7. on page 37).

NICAM_WAIT: Automatic start of the NICAM Decoder if Bit[6] of MODE_REG is set to 1

1. Wait at least 0.25 s NICAM_CHECK: Read NICAM specific information and check for presence, operation mode, and quality of

NICAM signal. Read out of MSP 3410D:

1. C_AD_BITS

2. CONC_CT or ERROR_RATE; if AUTO_FM is active, reading of CONC_CT or ERROR_RATE can be omitted. Evaluation of C_AD_BITS and CONC_CT or ERROR_RATE in the CCU (see section 6.6. on page 31).

If necessary, switch the corresponding sound channels within the audio baseband processing section. FM_WAIT: Automatic start of the FM identification process if Bit[6] of MODE_REG is set to 0.

1. Ident Reset

2. Wait at least 0.5 s FM_IDENT_CHECK: Read FM specific information and check for presence, operation mode, and quality of dual-

carrier FM. Read out of MSP 34x0D:

1. Stereo detection register (DSP register 0018

, high part)

hex

Evaluation of the stereo detection register (see section 7.6.1. on page 50). If necessary, switch the corresponding sound channels within the audio baseband processing section.

LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2 Write into MSP 34x0D:

Write into MSP 34x0D:

1. FIR1 (6 x 8 bit)

2. MODE_REG (12 bit)

For example: Addr: 0020

, Data: 0003

hex

3. DCO1_LO (12 bit)

4. DCO1_HI

PAUSE: Duration of “Pause” determines the repetition rate of the NICAM or the FM_IDENT check. Note: If downward-compatibility to the MSP 34x0B is required, the MSP 34x0D may be programmed

according to the MSP 34x0B data sheet.

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PRELIMINARY DATA SHEET MSP 34x0D

6.8. Software Proposals for Multistandard TV Sets

To familiarize the reader with the programming scheme of the MSP 34x0D demodulator part, three examples in the shape o f flow diagrams are shown in the following sections.

6.8.1. Multistandard Including System B/G with NICAM/FM-Mono only

Fig. 6 –1 shows a flow diagram for the CCU software, applied for the MSP 3410D in a TV set, which facilitates NICAM and FM-Mono sound. For the instructions, please refer to Table 6–15.

If the program is changed, resulting in another program within the Scandinavian Sy stem B/G, no parameters of the MSP 3410D need be modified. To facilitate the check for NICAM, the CCU has only to continue at the ’NICAM_WAIT’ instruction. During the NICAM identification process, the MSP 3410D must be switched to the FM-Mono sound.

START

6.8.3. Multistandard Including System B/G with NICAM/FM-Mono and German DUAL-FM

Fig. 6 –3 shows a flow diagram for the CCU software, applied for the MSP 3410D in a TV set which su pports all standards according to system B/G. For the instructions used in the diagram, please refer to Table 6–15.

After having switched on the TV set and having initi alized the MSP 3410D (LOAD_SEQ_1/2), FM-Mono sound is available.

Fig. 6 –3 sh ows that to check for any stereo or bilingual audio information, the TV sound standards 0008 (B/G-NICAM) and 0003

must simply be set alter-

hex

nately. If successful, the MSP 3410D must switch to the desired audio mode.

6.8.4. Satellite Mode

Fig. 6 –2 shows the simple flow diagram to be used for the MSP 34x0D in a satellite receiver. For FM-Mono operation, the corres pondi ng FM carr ie r sho uld preferably be processed at the MSP channel 2.

LOAD_SEQ_1/2

Set

Sound Standard

0008

hex

Audio Processing

Init

NICAM_WAIT

NICAM_CHECKPause

Fig. 6–1: CCU software flow diagram: standard B/G NICAM/FM-Mono only with Demodulator Short Programming Mode

6.8.2. Multistandard Including System I with NICAM/FM-Mono only

This case is id entica l to the afore-mentioned . The o nly difference consists in select ing the UK TV soun d standard, which is coded with 000A

of register 0020

hex

START

MSP-Channel 1 FM2-Parameter

MSP-Channel 2 FM1-Parameter

Audio Pro cessing

Init

STOP

Fig. 6–2: CCU software flow diagram: SAT mode

6.8.5. Automatic Search Function for FM Carrier Detection

The AM demodulati on ability of the MSP 34x0D offers the possibility to calculate the “field strength” of the momentarily selected FM carrier, which can be read out by the CCU. In SAT receivers, this feature can be used to make automatic FM carrier search possible.

Therefore, the MSPD has to be switched to AM mode (MODE_REG[8]), FM prescale must be set to

=+127

hex

switched off. The sound IF frequ ency range must now

, and the FM DC notch must be

dec

be “scanned” in the MSPD channe l 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz).

Micronas 35

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MSP 34x0D PRELIMINARY DATA SHEET

LOAD_SEQ_1/2

NICAM_WAIT

LOAD_SEQ_1

IDENT_CHECK

FM_

LOAD_SEQ_1

NICAM_CHECK

NICAM

Pause

Audio Processing Init

FM_WAIT

START

Yes

Stereo/Biling.

Mono

Set

Sound Standard

0008

hex

Set

Sound Standard

0003

hex

Set

Sound Standard

0008

hex

After each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to FM), which must be examined for relative maxima by the CCU. This results in either continuing search or switching the MSP 34x0D back to FM demodulation mode.

During the search p rocess, the FIR2 must be loaded with the coefficient set “AUTOSEARCH”, which enables small bandwidth, resulting in appr opriate field strength characteristics. The absolute field strength value (can be read out o f “quasi peak detec tor output FM1”) also gives information on whether a main FM carrier or a subcarrier was detected, and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 matically.

µs or adaptive) can be switched auto-

Due to the fact that a constant demodulation frequency offset of a few kHz, leads to a DC level in the demodulated signal, further fine tun in g o f the found carrier can be achieved by evaluating the “DC Level Readout FM1”. Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM demodulation mode.

For a detailed description of the automatic search function, please refer to the corresponding MSP 34xxD Windows software.

Note: The automatic search is still possible by evaluating only the DC Level Readout FM1 (DC Notch On) as it is described with the MSP 34x0B, but the above mentioned method is faster. If this DC Level method is applied with the MS P 34x0D, it is rec omm end ed to set MODE_REG[15] to 1 (AM gain = 12 dB) and to use the new Autosearch FIR2 coefficient set as given in Table 6–11.

Fig. 6–3: CCU software flow diagram: standard B/G with NICAM or FM-Stereo with Demodulator Short Programming

36 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

7. Programming the DSP Section (Audio Baseband Processing)

7.1. DSP Write Registers: Table and Addresses

Table 7–1: DSP Write Registers; Subaddress: 12

DSP Write Register Address High/

; if necessary, these registers are readable as well.

hex

Adjustable Range, Operational Modes Reset Mode

Low

Volume loudspeaker channel 0000 Volume / Mode loudspeaker ch annel L 1/8 dB Steps, Reduce Volume / Tone Control 00 Balance lo udspeaker channel [L/R] 0001

H [+12 dB ... −114 dB, MUTE] MUTE

hex

H [0...100 / 100% and vv][−127 .. 0 / 0 dB and vv] 100% / 100%

hex

Balance Mode loudspeaker L [Linear mode / logarithmic mode] linear mode Bass loudspeaker channel 0002 Treble loudspeaker channel 0003 Loudness loudspeaker channel 0004

H [+20 dB ... −12 dB] 0 dB

hex

H [+15 dB ... −12 dB] 0 dB

hex

H [0 dB ... +17 dB] 0 dB

hex

Loudness Filter Characteristic L [NORMAL, SUPER_BASS] NORMAL Spatial effect strength loudspeaker ch. 0005

H[−100%...OFF...+100%] OFF

hex

Spatial effect mode/customize L [SBE, SBE+PSE] SBE+PSE Volume headphone channel 0006 Volume / Mode headphone channel L 1/8 dB Steps, Reduce Volume / Tone Control 00

H [+12 dB ... −114 dB, MUTE] MUTE

hex

Volume / SCART1 channel 0007

H[00

hex

... 7F

],[+12 dB ... −114 dB, MUTE] 00

hex

Volume / Mode SCART1 channel L [Linear mode / logarithmic mode] linear mode Loudspeaker channel source 0008

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

Loudspeaker channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA Headphone channel source 0009

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

Headphone channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA SCART1 channel source 000A

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

SCART1 channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA I2S channel source 000B

S channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA

I Quasi-peak detector source 000C

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

H [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM

hex

Quasi-peak detector matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA Prescale SCART 000D Prescale FM/AM 000E

H[00

hex

H[00

hex

... 7F ... 7F

]00

hex

]00

hex

FM matrix L [NO_MAT, GSTEREO, KSTEREO] NO_MAT Deemphasis FM 000F

H[50µs, 75 µs, J17, OFF] 50 µs

hex

Adaptive Deemphasis FM L [OFF, WP1] OFF Prescale NICAM 0010

H[00

hex

... 7F

]00

hex

Micronas 37

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MSP 34x0D PRELIMINARY DATA SHEET

Table 7–1: DSP Write Registers; Subaddress: 12

hex

DSP Write Register Address High/

Low

Prescale I2S2 0012 ACB Register (SCART Switching

0013

Facilities and Digital Control Output

H[00

hex

H/L Bits [15...0] 00

hex

Pins) Beeper 0014 Identification Mode 0015 Prescale I

S1 0016 FM DC Notch 0017 Mode Tone Control 0020 Equalizer loudspeaker ch. band 1 0021 Equalizer loudspeaker ch. band 2 0022 Equalizer loudspeaker ch. band 3 0023 Equalizer loudspeaker ch. band 4 0024

H/L [00

hex

L [B/G, M] B/G

hex

H[00

hex

L [ON, OFF] ON

hex

H [BASS/TREBLE, EQUALIZER] BASS/TREB

hex

H [+12 dB ... −12 dB] 0 dB

hex

H [+12 dB ... −12 dB] 0 dB

hex

H [+12 dB ... −12 dB] 0 dB

hex

H [+12 dB ... −12 dB] 0 dB

hex

; if necessary, these registers are readable as well., continued

Adjustable Range, Operational Modes Reset Mode

hex

... 7F

]10

hex

]/[00

hex

... 7F

hex

]10

]0/0

hex

Equalizer loudspeaker ch. band 5 0025 Automatic Volume Correction 0029 V olume Subwoof e r chann el 002C Subwoofer Channel Corner Frequency 002D

H [+12 dB ... −12 dB] 0 dB

hex

H [off, on, decay time] off

hex

H [0 dB ... −30 dB, mute] 0 dB

hex

H [50 Hz ... 400 Hz] 00

hex

Subwoofer: Complementary High-pass L [off, on] off Balance headphone channel [L/R] 0030

H [0...100 / 100% and vv][−127...0 / 0 dB and vv] 100% /100%

hex

Balance Mode headphone L [Linear mode / logarithmic mode] linear mode Bass headphone channel 0031 Treble headphone channel 0032 Loudness headphone channel 0033

H [+20 dB ... −12 dB] 0 dB

hex

H [+15 dB ... −12 dB] 0 dB

hex

H [0 dB ... +17 dB] 0 dB

hex

Loudness filter characteristic L [NORMAL, SUPER_BASS] NO RMAL V o lum e SCART2 channel 0040

H[00

hex

... 7F

],[+12 dB ... −114 dB, MUTE] 00

hex

Volume / Mode SCART2 channel L [Linear mode / logarithmic mode] linear mode SCART2 channel source 0041

H [FM, NICAM, SCART, I2S1, I2S2] FM

hex

SCART2 channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA

38 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

7.2. DSP Read Registers: Table and Addresses

Table 7–2: DSP Read Registers; Subaddress: 13

; these registers are not writable.

hex

DSP Read Register Address High/Low Output Range

Stereo detection register 0018 Quasi-peak readout left 0019 Quasi-peak readout right 001A DC level readout FM1/Ch2-L 001B DC level readout FM2/Ch1-R 001C MSP hardware version code 001E

hex

MSP major revision code L [00 MSP product code 001F

hex

MSP ROM version code L [00

H[80 H&L [0000 H&L [0000 H&L [8000 H&L [8000 H[00

H[00

hex

... 7F

... 7FFF

hex

... 7FFF

hex

... 7FFF

hex

... 7FFF

hex

... FF ... FF ... 0A ... FF

] 8 bit two’s complement

hex

] 16 bit two’s complement

hex

] 16 bit two’s complement

hex

] 16 bit two’s complement

hex

] 16 bit two’s complement

hex

]

hex

]

hex

]

hex

]

hex

Micronas 39

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MSP 34x0D PRELIMINARY DATA SHEET

7.3. DSP Write Registers: Functions and Values

Write registers are 16 bit wide, whereby the MSB is denoted bit [15]. Transmissions via I

C bus have to take place in 16-bit words. Some of the d efined 16-bit words are divided into low [7...0] and high [15...8] byte, or in an other manner, thus holding two different control entities. All write registers are readable. Unused parts of the 16-bit registers must be zero. Addresses not given in this table must not be written at any time!

7.3.1. Volume – Loudspeaker and

Headphone Channel

Volume

0000

hex

[15...4]

Loudspeaker Volume

0006

hex

[15...4]

Headphone

+12 dB 0111 1111 0000 +11.875 dB 0111 1110 1110 7EE +0.125 dB 0111 0011 0010 732 0 dB 0111 0011 0000 730

−0.125 dB 0111 0010 1110 72E

−113.875 dB 0000 0001 0010 012

−114 dB 0000 0001 0000 010

Mute 0000 0000 0000 000

7F0

hex

RESET

Fast Mute 1111 1111 1110 FFE

Bit[4] must always be set to 0

hex

The highest given positive 12-bit number (7F0hex) yields in a maximum po ssible gain of 12 dB. Decreasing the volume register by 2 LSBs d ecreases the volume by 0.125 dB. Volume settings lower than the given minimum mute the output. With lar g e s cale i npu t signals, positive volume settings may lead to signal clipping.

The MSPD loudspe aker and headph one volume function is divided up into a digital and an analog section.

With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any aud ible DC plops. Going back from Fast Mute should be done to the volume step which was in existence before Fast Mute was activated.

The Fast Mute facility is activated by the I2C command. After 75 ms (typically), the signal is completely ramped down.

Clipping Mode

0000

hex

[3..0]

Loudspeaker Clipping Mode

0006

hex

[3..0]

Headphone

Reduce Volume 0000 0

hex

RESET Reduce Tone Control 0001 1 Compromise Mode 0010 2

hex

If the clipping mode is set to “Reduce Volume”, the following clipping procedure is used: To prevent severe clipping effects with bass, treble, or equa lizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB.

If the clipping mode is “Reduce Tone Control”, the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB.

If the clipping mode is “Compromise M ode”, the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduc ed half and half, where amplification together with volume exceeds 12 dB.

Example: Vol.:

+6 dB

Bass: +9 dB

Treble: +5 dB

Red. Volume 3 9 5 Red. Tone Con. 6 6 5 Compromise 4.5 7.5 5

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PRELIMINARY DATA SHEET MSP 34x0D

7.3.2. Balance – Loudspeaker and

Headphone Channel

Positive balance settings reduce the left channel wi thout affecting the right channel; negative settings reduce the r ight channe l leaving th e left c hannel u naffected. In linear mode, a step by 1 LSB dec reases or increases the balance by about 0.8 % (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB.

Balance Mode

0001

hex

[3..0]

Loudspeaker Balance Mode

0030

hex

[3..0]

Headphone

linear 0000 0

hex

RESET

logarithmic 0001 1

hex

Linear Mode

Logarithmic Mode Balance Loudspeaker

0001

hex

Channel [L/R] Balance Headphone

0030

hex

Channel [L/R]

Left

−127 dB, Right 0 dB 0111 1111 7F

Left −126 dB, Right 0 dB 0111 1110 7E Left −1 dB, Right 0 dB 0000 0001 01 Left 0 dB, Right 0 dB 0000 0000 00

RESET

Left 0 dB, Right

−1 dB 1111 1111 FF

Left 0 dB, Right −127 dB 1000 0001 81 Left 0 dB, Right −128 dB 1000 0000 80

7.3.3. Ba ss – Loudspeaker and

Headphone Channel

hex

Balance Loudspeaker

0001

hex

Channel [L/R] Balance Headphone

0030

hex

Channel [L/R]

Left muted, Right 100 % 0111 1111 7F Left 0.8 %, Right 100 % 0111 1110 7E Left 99.2 %, Right 100 % 0000 0001 01 Left 100 %, Right 100 % 0000 0000 00

RESET Left 100 %, Right 99.2 % 1111 1111 FF Left 100 %, Right 0.8 % 1000 0010 82 Left 100 %, Right muted 1000 0001 81

hex

Bass Loudspeaker 0002 Bass Headphone 0031

hex

H H

+20 dB 0111 1111 7F +18 dB 0111 1000 78 +16 dB 0111 0000 70 +14 dB 0110 1000 68 +12 dB 0110 0000 60 +11 dB 0101 1000 58 +1 dB 0000 1000 08 +1/8 dB 0000 0001 01 0 dB 0000 0000 00

RESET

−1/8 dB 1111 1111 FF

−1 dB 1111 1000 F8

−11 dB 1010 1000 A8

hex

−12 dB 1010 0000 A0

hex

Micronas 41

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MSP 34x0D PRELIMINARY DATA SHEET

With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a cl ipped output s ignal. Therefore, it is no t recommended to set bass to a value t hat, in conjunction with volume, would result in an overall positive gain.

Loudspeaker channel: Bass and Equalizer cannot work simultaneou sly (see section 7.3.22.: Mode Tone Control). If Equal izer is used, Bass and Treble coefficients must be set to zero and vice versa.

7.3.4. T reble – Loudspeaker and

Headphone Channel

Treble Loudspeaker 0003 Treble Headphone 0032

hex

+15 dB 0111 1000 78 +14 dB 0111 0000 70 +1 dB 0000 1000 08 +1/8 dB 0000 0001 01 0 dB 0000 0000 00

H H

hex

RESET

−1/8 dB 1111 1111 FF

hex

7.3.5. Loudness – Loudspeaker and

Headphone Channel

Loudness

0004

hex

Loudspeaker Loudness

0033

hex

Headphone

+17 dB 0100 0100 44 +16 dB 0100 0000 40 +1 dB 0000 0100 04 0 dB 0000 0000 00

RESET

Mode Loudness

0004

hex

Loudspeaker Mode Loudness

0033

hex

Headphone

Normal (consta nt volum e at 1 kHz )

Super Bass (constant

0000 0000 00 RESET

0000 0100 04

volum e at 2 kHz )

hex

−1 dB 1111 1000 F8

−11 dB 1010 1000 A8

−12 dB 1010 0000 A0

hex

With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a cl ipped output s ignal. Therefore, it is no t recommended to set tr eble to a value that, in conj unction with volume, would result in an overall positive gain.

Loudspeaker channel: Treble and Equalizer cannot work simultaneou sly (see section 7.3.22.: Mode Tone Control). If Equal izer is used, Bass and Treble coefficients must be set to zero and vice versa.

Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set ac cording to th e actual volume setting. Because loudness introduces gain, it is not recommended to se t loudness to a value that, in conjunction with volume, would result in an overall positive gain.

By means of ‘Mode Loudness’, the corn er frequency for bass amplification c an be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.

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PRELIMINARY DATA SHEET MSP 34x0D

7.3.6. Spatial Effects – Loudspeaker Channel There are several spatial effect modes available:

Spatial Effect Strength

0005

hex

Loudspeaker

Enlargement 100% 0111 1111 7F Enlargement 50% 0011 1111 3F Enlargement 1.5% 0000 0001 01 Effect off 0000 0000 00

RESET Reduction 1.5% 1111 1111 FF Reduction 50% 1100 0000 C0 Reduction 100% 1000 0000 80

Spatial Effect Mode

0005

hex

[7...4]

Loudspeaker

Stereo Basewidth Enlargement (SBE) and

0000 0

RESET Pseudo Stereo Effect (PSE). (Mode A)

Stereo Basewidth

0010 2 Enlargement (SBE) only. (Mode B)

hex

Mode A (low byte = 00

) is compatible to the formerly

hex

used spatial effect. Here, the kind of spatial effect depends on the s ource mo de. If the in comi ng si gnal i s in mono mode, Pseudo Ster eo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is acti ve. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recommended for small TV s ets where loudsp eaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input sign als, Pseudo Stereo Effect is active, which reduces the center image.

In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on.

It is worth mentioning, that all spatial effects affect amplitude and phas e response. With the lower 4 bits, the frequency res pons e can be c us tom ized. A value of 0000

yields a flat response for center signals (L = R)

bin

but a high pass function of L or R onl y sign al s. A value of 0110

has a flat respons e for L or R only signals

bin

but a low-pass function for center signals. By using 1000

, the frequency response is automatically

bin

adapted to the sound material by ch oosing an op timal high-pass gain.

Spatial Effect

0005

hex

Customize Coefficient Loudspeaker

max. high-pass gain 0000 0

RESET 2/3 high-pass gain 0010 2 1/3 high-pass gain 0100 4 min. high-pass gain 0110 6 automatic 1000 8

[3...0]

hex

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MSP 34x0D PRELIMINARY DATA SHEET

7.3.7. Volume – SCART1 and SCART2 Channel 7.3.8. Channel Source Modes

Volume Mode SCART1 0007 Volume Mode SCART2 0040

hex

[3...0] [3...0]

linear 0000 0

RESET

logarithmic 0001 1

Linear Mode Volume SCART1 0007 Volume SCART2 0040

hex

H H

OFF 0000 0000 00

RESET

0dB gain

0100 0000 40 (digital full scale (FS) to 2V

+6 dB gain (−6dBFS to 2V

RMS

output)

0111 1111 7F

output)

hex

Loudspeaker Source 0008 Headphone Source 0009 SCART1 Source 000A SCART2 Source 0041 I2S Source 000B Quasi-Peak

000C

hex

H H H H H H

Detector Source

FM/AM 0000 0000 00

RESET NICAM 0000 0001 01 none

(MSPB/C: SBUS12)

none

(MSPB/C: SBUS34)

0000 0011 03

0000 0100 04 SCART 0000 0010 02 I2S1 0000 0101 05 I2S2 0000 0110 06

hex

Logarithmic Mode Volume SCART1 0007 Volume SCART2 0040

hex

[15...4] [15...4]

+12 dB 0111 1111 0000 7F0 +11.875 dB 0111 1110 1110 7EE +0.125 dB 0111 0011 0010 732 0 dB 0111 0011 0000 730

−0.125 dB 0111 0010 1110 72E

−113.875 dB 0000 0001 0010 012

−114 dB 0000 0001 0000 010

Mute 0000 0000 0000 000

RESET

hex

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PRELIMINARY DATA SHEET MSP 34x0D

7.3.9. Channel Matrix Modes

Loudspeaker Matrix 0008 Headphone Matrix 0009 SCART1 Matrix 000A SCART2 Matrix 0041 I2S Matrix 000B Quasi-Peak

000C

hex

Detector Matrix

SOUNDA / LEFT / MSP-IF-CHANNEL2

SOUNDB / RIGHT /

0000 0000 00 RESET

0001 0000 10

MSP-IF-CHANNEL1 STEREO 0010 0000 20 MONO 0011 0000 30 SUM / DIFF 0100 0000 40

7.3.10. SCART Prescale

Volume Prescale

000D

hex

SCART

L L L L L

0 dB gain (2 V

RMS

to digital full scale) +14 dB gain

(400 mV

RMS

input to

input

RESET 0001 1001 19

0111 1111 7F

OFF 0000 0000 00

hex

digital full scale)

hex

AB_XCHANGE 0101 0000 50 PHASE_CHANGE_B 0110 0000 60 PHASE_CHANGE_A 0111 0000 70 A_ONLY 1000 0000 80 B_ONLY 1001 0000 90

hex

The sum/difference mode can be used together with the quasi-peak detector to deter mine the sound m aterial mode. If the difference signal on channe l B (right) is near to zero, and the sum signal on chann el A (left) is high, the incomi ng aud io si gna l i s mon o. If there is a significant level on the difference signa l, the incoming audio is stereo.

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MSP 34x0D PRELIMINARY DATA SHEET

7.3.11. FM/AM Prescale For the High Deviation Mode, the FM prescaling val-

hex

to 30

hex

Volume Prescale FM

000E

hex

(Normal FM Mode)

OFF 0000 0000 00

RESET

Maximum Volume (28 kHz deviation

0111 1111 7F

recommended FIRbandwidth: 130 kHz)

Deviation 50 kHz

0100 1000 48 recommended FIRbandwidth: 200 kHz

hex

ues can be used in the range from 14 Please conside r the internal re duction of 6 dB for this mode. The FIR-bandwidth should be selected to 500 kHz.

Given deviations will result in internal digital fullscale signals. Appropriate clipping headroom has to be set by the customer. This can be done by decreasing the listed values by a specific factor.

In the mentioned SIF-level range, the AM-output level remains stable and independent of the actual SIF-level. In this case, only the AM degree of audio signals above 40 Hz determines the AM-output level.

Deviation 75 kHz

0011 0000 30 recommended FIRbandwidth: 200 or 280 kHz

Deviation 150 kHz

0001 1000 18 recommended FIRbandwidth: 380 kHz

Maximum deviation 192 kHz

0001 0011 13 recommended FIR-

bandwidth: 380 kHz Prescale for adaptive

0001 0000 10 deemphasis WP1 recommended FIRbandwidth: 130 kHz

Volume Prescale FM

000E

hex

(High Deviation Mode)

OFF 0000 0000 00

RESET Deviation 150 kHz

0011 0000 30 recommended FIRbandwidth: 380 kHz

Maximum deviation 384 kHz

0001 0100 14 recommended FIR-

bandwidth: 500 kHz

hex

7.3.12. FM Matrix Modes (see also Table 4–1)

FM Matrix 000E

hex

NO MATRIX 0000 0000 00

hex

RESET GSTEREO 0000 0001 01 KSTEREO 0000 0010 02

hex

NO_MATRIX is used for terrestrial mono or satellite stereo sound. GSTEREO dematrixes [(L+R)/2, R] to [L, R] and is used for Germa n dual carrier stereo system (Standard B/G). KSTEREO dematrixes [(L+R)/2,

−R)/2] to [L, R] and is used for the Korean dual car-

(L rier stereo system (Standard M).

7.3.13. FM Fixed Deemphasis

Deemphas is FM 000F

µs 0000 0000 00

hex

RESET 75

µs 0000 0001 01

J17 0000 0100 04 OFF 0011 1111 3F

hex

Volume Prescale AM 000E

hex

7.3.14. FM Adaptive Deemphasis

OFF 0000 0000 00

hex

RESET

SIF input level:

0.1 V

0.8 V

− 0.8 Vpp 1) 2)

− 1.4 Vpp

0111 1100 7C

<7C

hex

Note: For AM, the bit MODE_REG[15] must be 1

FM Adaptive Deemphas is WP1

OFF 0000 0000 00

WP1 0011 1111 3F

000F

hex

RESET

hex

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PRELIMINARY DATA SHEET MSP 34x0D

7.3.15. NICAM Prescale

Volume Prescale

0010

hex

NICAM

OFF 0000 0000 00

hex

RESET 0 dB gain 0010 0000 20 +12 dB gain 0111 1111 7F

hex

7.3.16. NICAM Deemphasis

A J17 Deemphasis is always applied to the NICAM signal. It is not switchable.

7.3.17. I

S1 and I2S2 Prescale

Prescale I2S1 0016 Prescale I2S2 0012

hex

H H

OFF 0000 0000 00 0 dB gain 0001 0000 10

hex

RESET +18 dB gain 0111 1111 7F

hex

7.3.18. ACB Register

Definition of SCART Switching Facilities

(see Fig. 4–3 on page 13)

ACB Register 0013

hex

DSP IN

Selection of Source: * SC1_IN_L/R

MONO_IN SC2_IN_L/R SC3_IN_L/R SC4_IN_L/R Mute

xx xx00 xx00 0000 xx xx01 xx00 0000 xx xx10 xx00 0000 xx xx11 xx00 0000 xx xx00 xx10 0000 xx xx11 xx10 0000

SC1_OUT_L/R Selection of Source: * SC3_IN_L/R

SC2_IN_L/R MONO_IN SCART1_L/R via D/A SCART2_L/R via D/A SC1_IN_L/R SC4_IN_L/R Mute

xx 00xx x0x0 0000 xx 01xx x0x0 0000 xx 10xx x0x0 0000 xx 11xx x0x0 0000 xx 00xx x1x0 0000 xx 01xx x1x0 0000 xx 10xx x1x0 0000 xx 11xx x1x0 0000

SC2_OUT_L/R Selection of Source: * SCART1_L/R via D/A

SC1_IN_L/R MONO_IN SCART2_L/R via D/A SC2_IN_L/R SC3_IN_L/R SC4_IN_L/R Mute

00 xxxx 0xx0 0000 01 xxxx 0xx0 0000 10 xxxx 0xx0 0000 00 xxxx 1xx0 0000 01 xxxx 1xx0 0000 10 xxxx 1xx0 0000 11 xxxx 1xx0 0000 11 xxxx 0xx0 0000

[13...0]

Definition of Digital Control Output Pins

ACB Register 0013

hex

D_CTR_OUT0

low (RESET) high

x1 D_CTR_OUT1

low (RESET) high

[15..14]

* = RESET position, which becomes active at the

time of the first write transmission on the control bus to the audio processing part (DSP). By writing to the ACB register first, the RESET state can be redefined.

Note: If “MONO_IN” is selected at the DSP_IN selec- tion, the channel matrix mode of the corresponding output channel(s) must be set to “sound A”.

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MSP 34x0D PRELIMINARY DATA SHEET

7.3.19. B eeper

Beeper Volume 0014

hex

OFF 0000 0000 00

hex

RESET

Maximum Volume (full

0111 1111 7F

hex

digital scale FDS)

Beeper Frequency 0014

hex

16 Hz (lowest) 0000 0001 01 1 kHz 0100 0000 40 4 kHz (highest) 1111 1111 FF

hex

A square wave beeper can be added to the loudspeaker channel and the headphone channel. The addition point is just before loudness and volume adjustment.

7.3.20. Identification Mode

7.3.21. FM DC Notch

The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to spee d up th e automatic search function (see sectio n 6.8.5. on page

35). In nor mal FM mode, th e FM DC N otch shoul d be switched on.

FM DC Notch 0017

hex

ON 0000 0000 00

hex

Reset

OFF 0011 1111 3F

hex

7.3.22. Mode Tone Control

Mode Tone Control 0020

hex

Bass and Treble 0000 0000 00

hex

RESET

Equalizer 1111 1111 FF

hex

Identification Mode 0015

Standard B/G (German Stereo)

Standard M

0000 0000 00 RESET

0000 0001 01

hex

(Korean Stereo) Reset of Ident-Filter 0011 1111 3F

hex

To shorten the resp ons e time of t he identification algorithm after a program change between two FM-Stere o capable programs, the reset of the ident-filter can be applied.

Sequence:

1. Program change

2. Reset ident-filter

3. Set identification mode back to standard B/G or M

4. Read stereo detection register

By means of ‘Mode Tone Control’, Bass/Treble or Equalizer may be activated.

7.3.23. Automatic Volume Correction (AVC)

AVC On/Off 0029

AV C off and Reset

of int. variables

hex

0000 0 RESET

AVC on 1000 8

AVC Decay Time 0029

8 sec. (long) 4 sec. (middle) 2 sec. (shor t) 20 ms (very short)

hex

1000 8 0100 4 0010 2 0001 1

[15...12]

hex

[11...8]

hex hex hex hex

Different sound sources (e.g. terrest rial ch annels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisement during movies, as well, usually has a different (highe r) volume level than the movie itself. The Automatic Volume Correction (AVC) solves this problem and equalizes the volume levels.

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PRELIMINARY DATA SHEET MSP 34x0D

The absolute value o f the inc oming si gnal is fed into a filter with 16 ms attack time and selectable decay time. The decay time must be adjusted as shown in the table above. This attack/decay filter block works similar to a peak hold function. The volume correction value with its quasi continuou s step width is calculated using the attack/decay filter output.

The Automatic Volume Correction functions with an internal reference level of input signals with a volume level of

−18 dBr. This means that

−18 dBr will not be

affected by the AVC. If the input signals vary in a range

−24 dB to 0 dB, the AVC maintains a fixed output

of level of

−18 dBr.

Fig. 7 –1 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr co rresponds to full scale input / output. This is

– SCART in-, output 0 dBr – Loudspeaker and Aux output 0 dBr = 1.4 V

= 2.0 V

rms

output level [dBr]

7.3.24. Subwoof er Channel

The subwoofer channel is created by combining the left and right channels directly behind the tone control filter block. A third order low-pass filter with programmable corner frequency and volume adjustment according to the main channel output is performed to the bass signal. Additionally, at the loudspeaker channels, a complementary high-pass filter can be switched on.

Subwoofer Channel

002C

hex

Volume Adjust

0 dB 0000 0000 00

hex

RESET

−1 dB 1111 1111 FF

−29 dB 1110 0011 E3

−30 dB 1110 0010 E2

Mute 1000 0000 80

Subwoofer Channel

002D

hex

Corner Frequency

−12

−18

−24

−30 −24 −18 −12 −6 +6

input level

[dBr]

Fig. 7–1: Simplified AVC characteristics

To reset the internal variables, the AVC should be switched off and on during any channel or source change. For standard applications, the recommend ed decay time is 4 sec.

Note: AVC should not be used in any Dolby Pro Logic mode, except PANORAMA, where no other than the loudspeaker output is active.

50 Hz ... 400 Hz e.g. 50 Hz = 5

400 Hz = 40

dec

Subwoofer: Comple-

RESET 00 0000 0101 05 0010 1000 28

002D

hex

mentary High-pass

HP off 0000 0000 00

RESET

HP on 0000 0001 01

hex hex hex

hex

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MSP 34x0D PRELIMINARY DATA SHEET

7.3.25. Equalizer Loudspeaker Channel

Band 1 (below 120 Hz) 0021 Band 2 (Center: 500 Hz) 0022 Band 3 (Center: 1.5 kHz) 0023 Band 4 (Center: 5 kHz) 0024 Band 5 (above 10 kHz) 0025

hex

+12 dB 0110 0000 60 +11 dB 0101 1000 58 +1 dB 0000 1000 08 +1/8 dB 0000 0001 01 0 dB 0000 0000 00

RESET

−1/8 dB 1111 1111 FF

−1 dB 1111 1000 F8

−11dB 1010 1000 A8

7.5. Phase Relationship of Analog Outputs

H H H H

The analog output signals: Lo udspeaker, headphone, and SCART2 all have the same phases. The user does not need to change output phases when using these analog outputs dir e ctl y. The SCART1 output has opposite phase.

Using the I

S-outputs for other DSP s or D/A convert-

ers, care must be taken to adjust for the correct phase.

If the attached coproce ssor is one of the MSP family, the following schematics h elp to determine the phase

hex

relationship.

I2S_in I2S_out

Loudspeaker Headphone

Audio

Baseband

Processing

SCART2 SCART1

−12 dB 1010 0000 A0

hex

With positive equalizer settin gs, internal overflow may occur even with overall volume less than 0 dB. This will lead to a cl ipped output s ignal. Therefore, it is no t recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain.

Equalizer must not be us ed simultaneously with Bass and Treble (Mode Tone Contro l must be set to FF to use the Equalizer). If Bass and T reble are used, Equalizer coefficients must be set to zero.

7.4. Exclusions for the Audio Baseband Features

In general, all functions can be switched independently of the others. Exceptions:

1. NICAM cannot be processed simultaneously with the FM2 channel.

2. FM adaptive deemphasis WPI cannot be processed simultaneously with the FM-identification.

Mono SCART1…3

SCART1…2

Fig. 7–2: Phase diagram of the MSP 34x0D

7.6. DSP Read Registers: Functions and Values

All readable registers are 16-bit wide. Transmissions

via I

C bus have to take place in 16-bit words. Single data entries are 8 bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities.

These registers are not writable.

7.6.1. Stereo Detection Register

Stereo Detection

0018

hex

Stereo Mode Reading

(two’s complement) MONO near zero STEREO positive value (ideal

reception: 7F

hex

)

BILINGUAL negative value (ideal

reception: 80

hex)

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PRELIMINARY DATA SHEET MSP 34x0D

7.6.2. Quasi-Peak Detecto r

Quasi-Peak

0019

hex

H+L

Readout Left Quasi-Peak

001A

hex

H+L

Readout Right

Quasi peak readout [0000

... 7FFF

hex

] values are 16 bit two’s complement

The quasi peak r eadout register can be used to read out the quasi peak level of any input source, in order to adjust all inputs to the same normal listening level. The refresh rate is 32 kHz. The feature is base d on the filter time constants:

attack time: 1.3 ms decay time: 37 ms

7.6.3. DC Level Register

DC Level Readout

001B

hex

H+L

FM1 (MSP-Ch2) DC Level Readout

001C

hex

H+L

FM2 (MSP-Ch1)

DC Level [8000

... 7FFF

hex

] values are 16 bit two’s complement

The DC level register measures the DC component of the incoming FM sign als (FM1 and FM2). This can be used for seek functions in satelli te receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice-versa. For further proc essing, the DC content of the demodulated FM signals is suppressed. Th e time constant

τ, defining the transitio n time of th e DC Level

7.6.5. MSP Major Revision Code

Major Revision 001E

MSP 34x0D 04

hex

The MSP 34x0D is the fourth generation of ICs in the MSP family.

7.6.6. MSP Product Code

Product 001F

hex

MSP 3400D 0000 0000 00 MSP 3410D 0000 1010 0A

hex

By means of the MSP product code, the control pro cessor is able to decide whether or not NICAM-controlling should be accomplished.

7.6.7. MSP ROM Version Code

ROM Version 001F

Major software revision [00 MSP 34x0D

− B4 0010 0100 24

hex

... FF

hex

]

hex

A change in the ROM version code defines internal software optimizations, that may have influence on the chip’s behavior, e.g. new features may have been included. While a software change is intended t o create no compatibility problems, customers that would like to use the new functions, can identify new MSP 34x0D versions according to this number. To avoid compatibility problems with MSP 34x0B, an offset of 20

is added to the ROM version code of the

hex

chip’s imprint.

7.6.4. MSP Hardware Version Code

Hardware Version 001E

Hardware Version [00 MSP 34x0D

− B402

hex

... FF

hex

]

A change in the ha rdware version code defines har dware optimizations that may have influence on the chip’s behavior. The readout of this reg is ter i s identical to the hardware version code in the chip’s imprint.

Micronas 51

Page 52

MSP 34x0D PRELIMINARY DATA SHEET

8. Differences between MSP 3400C, MSP 3400D, MSP 3410B, and MSP 3410D

Feature MSP 3400C MSP 3400D−B4 MSP 3410B−F7 MSP 3410D−B4 Hardware

NICAM No No Yes Yes S-Bus Output No No S_DA_OUT No S-Bus Input S_DA_IN No S_DA_IN No Second I2S Data Input I2S_DA_IN2 I2S_DA_IN2 No I2S_DA_IN2 ADR Interface ADR_CL,

Second SCART D/A Converter No Yes No Yes

Demodulator

Demodulator Short Programming No Yes No Yes Autodetection for terr. TV Sound Standards No Yes No Yes Automatic switching from NICAM to FM and vv. No Yes No Yes ADCV[10] Carrier Mute Level Carrier Mute

ADCV[11] Carrier Mute Level Carrier Mute

MODE_REG[1]: Tri-state digital outputs 0: active

MODE_REG[2]: Tri-state digital outputs

MODE_REG[6]: NICAM no function no function 0: FM

S outputs

ADR_WS, ADR_DA

Level

1: tri-state 0: active

1: tri-state

ADR_CL, ADR_WS, ADR_DA

not used FIFO Watchdog

not used not used not used

0: active 1: tri-state

No ADR_CL,

On/Off

enable Pay-TV 0: active

disable NICAM Descrambler

1: NICAM

ADR_WS, ADR_DA

not used

1: tri-state 0: active

1: tri-state 0: FM

1: NICAM

MODE_REG[7]: FM1FM2 no function no function 0: NICAM

MODE_REG[10]: S-Bus Setting no function no function NICAM/FM on

MODE_REG[11]: S-Bus Mode no function no function Mode of internal

MODE_REG[12]: 6 dB gain in

MSP-Ch1

MODE_REG[13]: FIR filter coeff. set for

MSP-Ch1

MODE_REG[14] Mode of ADR Interface 0: normal mode

0: on 1: off

0: use FIR1 1: use FIR2

1: ADR/SaRa

0: on 1: off

0: use FIR1 1: use FIR2

0: normal mode 1: ADR/SaRa

1: FM

S-Bus

S-Bus always on 0: on

always FIR1 0: use FIR1

No 0: normal mode

no function

1: off

1: use FIR2

1: ADR/SaRa

52 Micronas

Page 53

PRELIMINARY DATA SHEET MSP 34x0D

Feature MSP 3400C MSP 3400D−B4 MSP 3410B−F7 MSP 3410D−B4 Demodulator

1: 12 dB

0: 0 dB 1: 12 dB

No 0: 0 dB

1: 12 dB

MODE_REG[15]: Gain for AM-Demodulation 0: 0 dB

FAWCT_SOLL (DEMOD W Addr. 107 FAWCT_ER_TOL (DEMOD W Addr. 10F AUDIO_PLL (DEMOD W Addr. 2D7 LOAD_REG_1/2 (DEMOD W Addr. 56 LOAD_REG_1 (DEMOD W Addr. 60 SEARCH_NICAM (DEMOD W Addr. 78 SELF_TEST (DEMOD W Addr. 792

FAWCT_IST (DEMOD R Addr.

25hex

CONC_CT (DEMOD R Addr. 58

ERROR_RATE (DEMOD R Addr. 57 Reading out RMS value of AGC I

) Not necessary Not necessary Yes Not necessary

hex

) Not necessary Not necessary Yes Not necessary

hex

) Not necessary Not necessary Yes Not necessary

hex

) Not necessary Not necessary Yes Not necessary

hex

) Not necessary Not necessary Yes Not necessary

hex

) No Not necessary Yes Not necessary

hex

) No not compatible,

hex

)NoNoYesYes, but not

) No No Yes Yes, but not

hex

)NoNoNoYes

hex

C Addr.

001E

hex

Reading out internal PLL capacitance switches I2C Addr.

001F

hex

not for cu stome r use,

I2C Addr. 021E

hex

I2C Addr. 021F

hex

values as described in Mubi-Software

not compatible, not for customer use,

necessary

recommended

not possible I2C Addr.

021E

hex

not possible I2C Addr.

021F

hex

Audio Baseband Processing

Improved oversampling filters for all

Yes Yes No Yes

D/A converters Mode Loudness Loudspeaker channel

(DSP W Addr. 0004

hex

Spatial Effect Loudspeaker

Prescale I Prescale I

(DSP W Addr. 05

S2 (DSP W Addr. 0012

S1 (DSP W Addr. 0016

hex

FM DC Notch switchable

(DSP W Addr. 0017

hex

Mode Tone Control Loudspeaker channel

(DSP W Addr. 0020

hex

5 Band Equalizer (DSP W Addr.

0021

hex

− 0025

hex

)

Balance Headphone channe l

(DSP W Addr. 0030

This feature will be implemented in MSP 3400C from version C7 on.

hex

:normal

hex

:Super

hex

Bass

Mode/

Customize H) Yes H) Yes

Yes Yes No Yes )

:Bass/

hex

Treble

:Equalizer

hex

[+12 ...−12 dB] [+12 ...−12 dB] not implemented [+12 ...−12 dB]

Yes H)

:normal

hex

:Super

hex

Bass

Mode/ Customize

: normal

hex

: Super

hex

Version ≥ F7

00 04

always 0 Mode/

Customize Yes No Yes Yes No Yes

:Bass/

00 FF

hex

Treble

: Equalizer

hex

always Bass/ Treble

Yes No Yes

:normal

hex

:Super

hex

Bass

:Bass/

hex

Treble

:Equalizer

hex

Micronas 53

Page 54

MSP 34x0D PRELIMINARY DATA SHEET

Feature MSP 3400C MSP 3400D−B4 MSP 3410B−F7 MSP 3410D−B4 Audio Baseband Processing

Bass for Loudspeaker and Headphone chan.

(DSP W Addr. 0002/ 0031

hex

Treble for Loudspeaker and He ad pho ne cha n.

(DSP W Addr. 0003/ 0032

hex

Loudness Headphone channel

(DSP W Addr. 0033

hex

Yes [+20 ...−12 dB]

Yes [+15 ...−12 dB]

Yes

Yes [+20 ...−12 dB]

Yes [+15 ...−12 dB]

No Yes

[+20 ...−12 dB]

No Yes

[+15 ...−12 dB]

Yes No Yes

Mode Loudness Headphone channel

(DSP W Addr. 0033

SCART1/2 Volume in dB

(DSP W Addr. 0007/ 0040 Scart 2 Volume (DSP W Addr. 0040 Scart 2 Source (DSP W Addr. 0041 Scart 2 Matrix (DSP W Addr. 0041

hex

H) No Yes No Yes

hex

H) No Yes No Yes

hex

L) No Yes No Yes

hex

:normal

hex

: Super

hex

Bass

Yes (SCART1)

:normal

hex

: Super

hex

Bass

No 00

Yes No Yes

Full SCART I/O Matrix without restrictions No Yes No Yes Balance of loudspeaker and headphone

Yes

Yes No Yes

channels in dB units

(DSP W Addr. 0016/ 0012

hex

) Subwoofer output No Yes No Yes Automatic Volume Correction (AVC) No Yes No Yes

This feature will be implemented in MSP 3400C from version C7 on.

:normal

hex

: Super

hex

Bass

54 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

9. Specifications

9.1. Outline Dimensions

0.1± 0.1±

619

x 45 °1.1

0.9

16 x 1.27 = 20.32

0.1±

1.27

1.2 x 45°

4327

0.125±

25.125

1.6 9

0.125±

Fig. 9–1:

68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g Dimensions in mm

3364

1.9

4.05

4.75

SPGS0016-4/3

±0.15

0.48

0.711

0.07±

0.22

23.4

0.1

0.1±

24.22

0.1±

24.22

2752

1.27

0.1± 0.1±

16 x 1.27 = 20.32

SPGS7004-3/5E

SPGS0015-1/2E

1.9

±0.1

3.8

0.3

±0.4

4.8

0.3

2.5

132

±0.1

57.7

(1)

±0.4

1.29

3.2

1.778 31 x 1.778 = 55.118

±0.05

±0.1

0.457

±0.1

Fig. 9–2:

64-Pin Plastic Shrink Dual Inline Package

(PSDIP64)

Weight approximately 9.0 g Dimensions in mm

126

±0.1

0.27

19.3 18

±0.06

20.1

±0.1

±0.5

±0.1

±0.05

1.778 25 x 1.778 = 44.47

±0.1

0.457

±0.2

0.4

±0.1

±0.2

3.2

0.3

0.24

0.27

15.6 14

±0.06

±0.1

0°...15°

Fig. 9–3:

52-Pin Plastic Shrink Dual Inline Package

(PSDIP52)

Weight approximately 5.5 g Dimensions in mm

Micronas 55

Page 56

MSP 34x0D PRELIMINARY DATA SHEET

23 x 0.8 = 18.4

±0.03

4164

0.17

0.8

23.2

17.2

1.8

10.3

9.8

Fig. 9–4:

80-Pin Plastic Quad Flat Pack

(PQFP80)

Weight approximately 1.61 g Dimensions in mm

3348

1.75

116

1.75 12

0.22

1.8

0.145

1.4

0.1

1.28

2.70

±0.2

0.1

15 x 0.5 = 7.5

0.5

15 x 0.5 = 7.5

241

1.5

0.8

15 x 0.8 = 12.0

SPGS0025-1/1E

Fig. 9–5:

64-Pin Plastic Low-Profile Quad Flat Pack

(PLQFP64)

Weight approximately 0.35 g Dimensions in mm

D0025/2E

56 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

9.2. Pin Connections and Short Descriptions

NC = not connected (leave vacant for future compatibility reasons) TP = Test Pin (leave vacant; pin is used for production test only) LV = leave vacant X = obligatory; connect as described in application circuit diagram

Pin No. Pin Name Type Connection Short Description

PLCC 68-pin

PSDIP 64-pin

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

(if not used)

1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2

−−−−NC LV Not connected

3 15 13 8 7 ADR_DA OUT LV ADR data output 4 14127 6 I2S_DA_IN1 IN LV I 5 13116 5 I2S_DA_OUTOUTLV I 6 12105 4 I2S_WS IN/OUTLV I 711943I2S_CL IN/OUTLV I 810832I2C_DA IN/OUTX I 99721I2C_CL IN/OUTX I 10 8

− 1 64 NC LV Not connected

S1 data input

S data output

S word strobe

S clock

C data

C clock

11 7 6 80 63 STANDBYQ IN X Standby (low-active) 12657962ADR_SEL IN X I

C Bus address select 13 5 4 78 61 D_CTR_OUT0 OUT LV Digital control output 0 14 4 3 77 60 D_CTR_OUT1 OUT LV Digital control output 1 15 3

− 76 59 NC LV Not connected

16 2 17

−−−−NC LV Not connected

− 75 58 NC LV Not connected

18 1 2 74 57 AUD_CL_OUT OUT LV Audio clock output

(18.432 MHz) 19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL_OUT OUT X Crystal oscillator 21 62 51 71 54 XTAL_IN IN X Crystal oscillator 22 61 50 70 53 TESTEN IN X Test pin 23 60 49 69 52 ANA_IN2+ IN AVSS via

56 pF / LV

24 59 48 68 51 ANA_IN− IN AVSS via

56 pF / LV

IF input 2

(can be left vacant only if

IF input1 is also not in use)

IF common

(can be left vacant only if

IF input1 is also not in use)

25 58 47 67 50 ANA_IN1+ IN LV IF input 1

Micronas 57

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MSP 34x0D PRELIMINARY DATA SHEET

Pin No. Pin Name Type Connection Short Description

PLCC 68-pin

26 57 46 66 49 AVSUP X Analog power supply 5V

−−−65 − AVSUP X Analog power supply 5V

−−−64 − NC LV Not connected

−−−63 − NC LV Not connected

27 56 45 62 48 AVSS X Analog ground

−−−61 − AVSS X Analog ground

28 55 44 60 47 MONO_IN IN LV Mono input

−−−59 − NC LV Not connected

29 54 43 58 46 VREFTOP X Refe rence voltage

PSDIP 64-pin

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

(if not used)

IF A/D converter 30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right 31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51

− 55 43 ASG1 AHVSS Analog Shield Ground 1

33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48

− 52 40 ASG2 AHVSS Analog Shield Ground 2

36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 39 44 40 43 41

−−46 − NC LV or AHVSS Not connected

− 49 37 ASG4 AHVSS Analog Shield Ground 4

− 48 36 SC4_IN_R IN LV SCART 4 input, right

− 47 35 SC4_IN_L IN LV SCART 4 input, left

42 42 36 45 34 AGNDC X Analog reference

voltage 43 41 35 44 33 AHVSS X Analog ground

−−−43 − AHVSS X Analog ground

−−−42 − NC LV Not connected

−−−41 − NC LV Not connected

44 40 34 40 32 CAPL_M X Volume capacitor MAIN 45 39 33 39 31 AHVSUP X Analog power supply 8V 46 38 32 38 30 CAPL_A X Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART 1 output, left

58 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

Pin No. Pin Name Type Connection Short Description

PLCC 68-pin

PSDIP 64-pin

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

(if not used)

48 36 30 36 28 SC1_OUT_R OUT LV SCART 1 output, right 49 35 29 35 27 VREF1 X Reference ground 1

high voltage part 50 34 28 34 26 SC2_OUT_L OUT LV SCART 2 output, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART 2 output, right 52

−−32 − NC LV

Not connected 53 32

− 31 24 NC LV Not connected

54 31 26 30 23 DACM_SUB LV Subwoofer output 55 30

− 29 22 NC LV Not connected

56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 X Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right

−−−23 − NC LV Not connected

−−−22 − NC LV Not connected

61 24 20 21 16 RESETQ IN X Power-on reset 62 23 63 22

− 20 15 NC LV Not connected

− 19 14 NC LV Not connected

64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 IN LV I

S2 data input

66 19 17 16 11 DVSS X Digital ground

−−−15 − DVSS X Digital ground

−−−14 − DVSS X Digital ground

67 18 16 13 10 DVSUP X Digital power supply 5V

−−−12 − DVSUP X Digital power supply 5V

−−−11 − DVSUP X Digital power supply 5V

68 17 15 10 9 ADR_CL OUT LV ADR clock

Due to compatibility with MSP 3410D-B4 and older versions, it is possible to connect with ground as well.

Micronas 59

Page 60

MSP 34x0D PRELIMINARY DATA SHEET

9.3. Pin Configurations

ADR_WS

ADR_DA

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

I2C_DA

I2C_CL

9876543216867666564636261

STANDBYQ

ADR_SEL D_CTR_OUT0 D_CTR_OUT1

AUD_CL_OUT

XTAL_OUT

XTAL_IN TESTEN

ANA_IN2+

ANA_IN−

ANA_IN1+

11 12 13 14

17 18

19 20 21 22 23 24 25

AVSUP CAPL_M

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

MSP 34x0D

ADR_CL

DVSUP

DVSS

I2S_DA_IN2

RESETQ

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP

AVSS

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

SC2_IN_R

SC2_IN_L

Fig. 9–6: 68-pin PLCC package

AHVSS

AGNDC

SC4_IN_L

SC4_IN_R

ASG4

SC3_IN_L

SC3_IN_R

ASG2

60 Micronas

Page 61

PRELIMINARY DATA SHEET MSP 34x0D

VREF2

DACM_R

DACM_L

DACM_SUB

1AUD_CL_OUT 2NC 3NC 4D_CTR_OUT1 5D_CTR_OUT0 6ADR_SEL 7STANDBYQ 8NC 9I2C_CL 10I2C_DA 11I2S_CL 12I2S_WS 13I2S_DA_OUT 14I2S_DA_IN1 15ADR_DA 16ADR_WS 17ADR_CL 18DVSUP 19DVSS

MSP 34x0D

20I2S_DA_IN2 21NC 22NC 23NC 24RESETQ 25DACA_R 26DACA_L 27 28 29 30 31 32

38 37 36 35 34 33

TP64 XTAL_OUT63 XTAL_IN62 TESTEN61 ANA_IN2+60 ANA_IN−59 ANA_IN+58 AVSUP57 AVSS56 MONO_IN55 VREFTOP54 SC1_IN_R53 SC1_IN_L52 ASG151 SC2_IN_R50 SC2_IN_L49 ASG248 SC3_IN_R47 SC3_IN_L46 ASG445 SC4_IN_R44 SC4_IN_L43 AGNDC42 AHVSS41 CAPL_M40 AHVSUP39 CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R

AUD_CL_OUT D_CTR_OUT1 D_CTR_OUT0

ADR_SEL

STANDBYQ

I2C_DA

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

I2S_DA_IN2

RESETQ

DACA_R

DACA_L

DACM_R

DACM_L

DACM_SUB

Fig. 9–8: 52-pin PSDIP package

I2C_CL

I2S_CL

DVSUP

DVSS

VREF2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

MSP 34x0D

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN− ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R

Fig. 9–7: 64-pin PSDIP package

Micronas 61

Page 62

MSP 34x0D PRELIMINARY DATA SHEET

SC2_IN_L ASG2

AVSUP AVSUP

ANA_IN1+

ANA_IN−

ANA_IN2+

TESTEN XTAL_IN

XTAL_OUT

AUD_CL_OUT

NC D_CTR_OUT1 D_CTR_OUT0

ADR_SEL

STANDBYQ

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

65 66 67 68 69 70 71 72 73

74 75 76 77 78 79 80

1 2 3 4 5 6 7 8 9 101112131415161718192021222324

MSP 34x0D

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

AGNDC

AHVSS

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R ASG3 NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L

NC I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

Fig. 9–9: 80-pin PQFP package

DVSUP

DVSUP DVSUP

DACA_R

RESETQ

I2S_DA_IN2

DVSS

62 Micronas

Page 63

PRELIMINARY DATA SHEET MSP 34x0D

AVSUP

ANA_IN1+

ANA_IN-

ANA_IN2+

TESTEN

XTAL_IN

XTAL_OUT

AUD_CL_OUT

NC D_CTR_OUT1 D_CTR_OUT0

ADR_SEL

STANDBYQ

SC2_IN_L

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49 50 51 52 53 54 55

56 57 58 59 60 61 62 63 64

12345678910111213141516

MSP 34x0D

ASG2

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

AGNDC

AHVSS

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

Fig. 9–10: 64-pin PLQFP package

RESETQ

I2S_DA_IN2

DVSS

DVSUP

ADR_CL

Micronas 63

Page 64

MSP 34x0D PRELIMINARY DATA SHEET

DVSUP

GND

DVSUP

GND

9.4. Pin Circuits (pin numbers refer to PLCC68 package)

Fig. 9–11: Output Pins 1, 3, 5, 13, 14, and 68 (ADR_WS, ADR_CL, ADR_DA, I2S_DA_OUT, D_CTR_OUT0/1)

Fig. 9–12: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL)

3−30 pF

−30 pF

500 k

2.5 V

Fig. 9–15: Output/Input Pins 18, 20, and 21 (AUD_CL_OUT, XTALIN/OUT)

ANAIN1+ ANAIN2+

ANAIN

−

VREFTOP

Fig. 9–13: Input Pins 4, 11, 12, 61, 62, and 65 (STANDBYQ, ADR_SEL, RESETQ, TESTEN, I2S_DA_IN1, I2S_DA_IN2)

Fig. 9–14: Input/Output Pins 6 and 7 (I2S_WS, I2S_CL)

Fig. 9–16: Input Pins 23-25, and 29 (ANA_IN2+, ANA_IN-, ANA_IN1+, VREFTOP)

0...2 V

Fig. 9–17: Capacitor Pins 44 and 46 (CAPL_M, CAPL_A)

24 k

≈ 3.75 V

Fig. 9–18: Input Pin 28 (MONO_IN)

64 Micronas

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PRELIMINARY DATA SHEET MSP 34x0D

40 k

≈ 3.75 V

Fig. 9–19: Input Pins 30, 31, 33, 34, 36, 37, 40, and 41 (SC1-4_IN_L/R)

AHVSUP

0...1.2 mA

3.3 k

Fig. 9–20: Output Pins 56, 57, 59, 60, and 54 (DACA_L/R, DACM_L/R, DACM_SUB)

125 k

≈ 3.75 V

Fig. 9–21: Pin 42 (AGNDC)

26 pF

120 k

300

≈ 3.75 V

Fig. 9–22: Output Pins 47, 48, 50, and 51 (SC_1/2_OUT_L/R)

Micronas 65

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MSP 34x0D PRELIMINARY DATA SHEET

9.5. Electrical Characteristics

9.5.1. Absolute Maximum Ratings

Symbol Parameter Pin Name Min. Max. Unit

SUP1

SUP2

SUP3

TOT

Idig

Iana

SUP23

Ambient Operating Temperature − 070

°C

Storage Temperature −−40 125 °C First Supply Voltage AHVSUP −0.3 9.0 V Second Supply Voltage DVSUP −0.3 6.0 V Third Supply Voltage AVSUP −0.3 6.0 V Voltage between AVSUP

and DVSUP

AVSUP , DVSUP

−0.5 0.5 V

Package Power Dissipation PLCC68 without Heat Spreader PSDIP64 without Heat Spreader PSDIP52 without Heat Spreader PQFP80 without Heat Spreader PLQFP64 without Heat Spreader

Input Voltage, all Digital Inputs −0.3 V

1200 1300 1200 1000 960

SUP2

+0.3 V

Input Current, all Digital Pins −−20 +20 mA Input Voltage, all Analog Inputs SCn_IN_s,

−0.3 V

SUP1

+0.3 V

MONO_IN

Iana

Input Current, all Analog Inputs SCn_IN_s,

−5+5mA

MONO_IN

Oana

Output Current, all SCART Outputs SCn_OUT_s Output Current, all Analog Outputs

DACp_s

3) 4 ), 5) 4), 5)

3) 4) 4)

except SCART Outputs

Cana

PLQFP64: 65 °C

positive value means current flowing into the circuit

“n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”

The analog outputs are short circuit proof with respect to First Supply Voltage and ground.

Total chip power dissipation must not exceed absolute maximum rating.

Output Current, other pins connected to capacitors

CAPL_p, AGNDC

4) 4)

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating onl y. Functional operation of the device at these or any oth er condi tions beyond those indic ated i n the “Rec ommended Operating Conditions/Character istics” of this specificati on is not i mplied. Ex posure to abs olute maximum ratings conditions for extended periods may affect device reliability.

66 Micronas

Page 67

PRELIMINARY DATA SHEET MSP 34x0D

9.5.2. Recommended Operating Conditions

= 0 to 70 °C)

(at T

Symbol Parameter Pin Nam e Min. Typ. Max. Unit

V V V V

SUP1

SUP2

SUP3

RLH

First Sup ply Voltage AHVSUP 7.6 8.0 8.7 V Second Supply Voltage DVSUP 4.75 5.0 5.25 V Third Supply Voltage AVSUP 4.75 5.0 5.25 V RESET Input Low-to-High

Transition Voltage

RHL

RESET Input High-to-Low Transition Voltage

(see also Fig. 5–3 on page 20) V V V V

DIGIL

DIGIH

DIGIL

DIGIH

Digital Input Low Voltage ADR_SEL 0.2 V

Digital Input High Voltage 0.8 V

Digital Input Low Voltage STANDBYQ 0.2 V

Digital Input High Voltage

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later t

STBYQ1

STANDBYQ Setup Time before

Turn-off of Second Supply Voltage

C-Bus Recommendations

RESETQ 0.7 0.8 DVSUP

0.45 0.55 DVSUP

SUP2

STANDBYQ,

0.8

0.5 1 µs

SUP2

DVSUP

V V t

I2C5

I2C6

I2C1

I2C2

I2C3

I2C4

I2C

I2CIL

I2CIH

I2C-BUS Input Low Voltage I2C_CL,

0.3 V

SUP2

I2C_DA

I2C-BUS Input High Voltage 0.6 V

I2C-Data Setup Time Before

55 ns

SUP2

Rising Edge of Clock

I2C-Data Hold Time after Falling

55 ns

Edge of Clock

I2C START Condition Setup Time 120 ns

I2C STOP Condition Setup Time 120 ns

I2C-Clock Low Pulse Time I2C_CL 500 ns

I2C-Clock High Pulse Time 500 ns

I2C-BUS Frequency 1.0 MHz

Micronas 67

Page 68

MSP 34x0D PRELIMINARY DATA SHEET

Symbol Parameter Pin Name Min. Typ. Max. Unit I2S-Bus Recommendations

I2SIH

I2SIL

I2S1

I2S2

I2SCL

I2SWS

I2SIDL

I2S-Data Input High Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

I2S-Data Input Low Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

I2S-Data Input Setup Time before Rising Edge of Clock

I2S-Data Input Hold Time after Falling Edge of Clock

I2S-Clock Input Frequency when MSP in I

I2S-Clock Input Ratio when MSP in I

I2S-Word Strobe Input Frequency when MSP in I

I2S-Input Low Voltage when MSP in I

S-Slave-Mode

S-Slave Mode MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

I2S_DA_IN1/2

I2S_DA_IN1/2,

0.25

0.2

0.75

0.5 20 ns

SUP2

I2S_CL

0ns

I2S_CL 1.024 MHz

0.9 1.1

I2S_WS 32.0 kHz

I2S_CL, I2S_WS

0.25

0.2

SUP2

I2SIDH

I2SWS1

I2SWS2

I2S-Input High Voltage when MSP in I

S-Slave Mode MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

I2S-Word Strobe Input Setup Time before Rising Edge of Clock when MSP in I

S-Slave-Mode I2S-Word Strobe Input Hold Time

after Falling Edge of Clock when MSP in I

S-Slave-Mode

0.75

0.5

SUP2

60 ns

0ns

68 Micronas

Page 69

PRELIMINARY DATA SHEET MSP 34x0D

Symbol Parameter Pin Name Min. Typ. Max. Unit General Crystal Recommendations

Crystal Parallel Resonance Fre-

18.432 MHz

quency at 12 pF Load Capacitance

Crystal Series Resistance 8 25 Ω Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF External Load Capacitance

XTAL_IN, XTAL_OUT

PSDIP 1.5 PLCC 3.3 P(L)QFP 3.3

Crystal Recommendations for Master-Slave Applications

TOL

TEM

Accuracy of Adjustment −20 +20 ppm Frequency Variation

−20 +20 ppm

versus Temperature

Motional (Dynamic) Capacitance 19 24 fF Required Open Loop Clock

Frequency (T

amb

= 25°C)

AUD_CL_OUT 18.431 18.433 MHz

Crystal Recommendations for FM / NICAM Applications (No Master-Slave Mode possible)

TOL

TEM

Accuracy of Adjustment −30 +30 ppm Frequency Variation vs. Temp. −30 +30 ppm

pF pF pF

Motional (Dynamic) Capacitance 15 fF Required Open Loop Clock

Frequency (T

= 25 °C)

amb

AUD_CL_OUT

18.4305 18.4335

MHz

Crystal Recommendations for FM Applications (No Master-Slave Mode possible)

TOL

TEM

Accuracy of Adjustment −100 +100 ppm Frequency Variation

−50 +50 ppm

versus Temperature

Amplitude Recommendation for Operation with External Clock Input (C

XCA

External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-

External Clock Amplit ude XTAL_IN 0.7 V

after reset = 22 pF)

load

quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB

. The sug-

gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”. To define the capacitor size, reset the MSP without transmitting any further I

C telegrams. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible.The higher the capacity, the lower the resulting clock frequency.

Micronas 69

Page 70

MSP 34x0D PRELIMINARY DATA SHEET

Symbol Parameter Pin Name Min. Typ. Max. Unit Analog Input and Output Recommendations

AGNDC

AGNDC Filter Capacitor AGNDC −20% 3.3 µF Ceramic Capacitor in Parallel

inSC

DC-Decoupling Capacitor in front of SCART Inputs

inSC

inMONO

LSC

VMA

FMA

SCART Input Level 2.0 V Input Level, Mono Input MONO_IN 2.0 V SCART Load Resistance SCn_OUT_s SCART Load Capacitance 6.0 nF Main/AUX Volume Capacitor CAPL_M,

Main/AUX Filter Capacitor DACM_s,

Recommendations for Analog Sound IF Input Signal

VREFTOP

VREFTOP Filter Capacitor VREFTOP −20% 10 µF Ceramic Capacitor in Parallel

IF_FM

Analog Input Frequency Range

SCn_IN_s

CAPL_A

DACA_s

−20% 100 nF

−20% 330 +20% nF

10 kΩ

RMS

10 µF

−10% 1 +10% nF

−20% 100 nF

09MHz

IF_FM

IF_AM

FMNI

AMNI

FM1/FM2

SUP

Analog Input Range FM/NICAM 0.1 0.8 3 V Analog Input Range AM/NICAM 0.1 0.45 0.8 V

Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG:

Ratio: NICAM Carrier/AM Carrier

−20

−23

−7

−10

0 0

−25 −11 0 dB

dB dB

(unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite 7 dB Ratio: FM1/FM2

German FM System Ratio: Main FM Carrier/

ANA_IN1+, ANA_IN2+, ANA_IN-

7dB

15 −−dB

Color Carrier Ratio: Main FM Carrier/

15 −−dB

Luma Components Pass-band Ripple −−±2dB Suppression of Spectrum

15 − dB

Above 9.0MHz

MAX

“n” means “1”, “2” or “3”, “s” means “L” or “R”

Maximum FM Deviation (approx.) normal mode high deviation mode

±192 ±360

kHz

70 Micronas

Page 71

PRELIMINARY DATA SHEET MSP 34x0D

9.5.3. Characteristics

= 0 to 70 °C, f

at T

= 60 °C, f

at T

CLOCK

= 18.432 MHz, V

CLOCK

= 18.432 MHz, V

SUP1

= 7.6 to 8.7 V, V

SUP1

= 8 V, V

SUP2

= 4.75 to 5.25 V for min./max. values

SUP2

= 5 V for typical values, TJ = Junction Temperature

MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

CLOCK

JITTER

xtalDC

Startup

SUP1A

SUP1S

SUP2A

SUP3A

Clock Input Frequency XT AL_IN 18.432 MHz Clock High to Low Ratio 45 55 % Clock Jitter (verification not

50 ps

provided in production test) DC-Voltage Oscillator 2.5 V Oscillator Start-up Time at

Slew-rate of 1 V /1 µs

First Supply Current (active)

Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at −30 dB

First Supply Current (standby mode) at T

= 27 °C

Second Supply Current (active) MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

Third Supply Current (active) MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

XTAL_IN, XTAL_OUT

AHVSUP

DVSUP

AVSUP

0.4 2 ms

9.6

6.3

17.1

11.2

24.6

16.1mAmA

3.5 5.6 7.7 mA STANDBYQ = low

86 50

15 20

95 70

25 35

110 85

35 45

mA mA

ACLKAC

ACLKDC

outHF_ACL

ACL

Audio Clock Output AC Voltage AUD_CL_OUT 1.2 1.8 V Audio Clock Output DC Voltage 0.4 0.6 V HF Output Resistance 140 Ω Open Circuit Gain AUD_CL_OUT,

Digital Control Outputs

DCTROL

DCTROH

C-Bus

I2COL

I2COH

I2COL1

I2COL2

S-Bus

I2SOL

I2SOH

I2SCL

Digital Output Low Voltage D_CTR_OUT0, Digital Output High Voltage 4.0 V I

I2C-Data Output Low Voltage I2C_DA 0.4 V I I2C-Data Output High Current 1.0 µAV I2C-Data Output Hold Time

after Falling Edge of Clock I2C-Data Output Setup Time

before Rising Edge of Clock

I2S-Output Low Voltage I2S_WS, I2S-Output High Voltage 4.0 V I I2S-Clock Output Frequency I2S_CL 1024 kHz NICAM-PLL closed

XTAL_OUT

D_CTR_OUT1

I2C_DA, I2C_CL

I2S_CL, I2S_DA_OUT

SUP3

0.5

0.4 V I

15 ns

100 ns f

0.4 V I

load = 40 pF I

= 0.2 mA

max

= 1 mA

DCTR

= −1 mA

DCTR

= 3 mA

I2COL

= 5 V

I2COH

= 1 MHz

I2C

= 1 mA

I2SOL

= −1 mA

I2SOH

I2SWS

I2S1/I2S2

I2S-Word Strobe Output Frequency I2S_WS 32.0 kHz NICAM-PLL closed I2S-Clock High/Low-Ratio I2S_CL 0.9 1.0 1.1

Micronas 71

Page 72

MSP 34x0D PRELIMINARY DATA SHEET

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

I2S3

I2S4

I2S5

I2S6

I2S-Data Setup Time before Rising Edge of Clock

I2S-Data Hold Time after Falling Edge of Clock

I2S-Word Strobe Setup Time before Rising Edge of Clock

I2S-Word Strobe Hold Time after Falling Edge of Clock

Analog Ground

AGNDC0

AGNDC Open Circuit Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

outAGN

AGNDC Output Resistance 70 125 180 kΩ 3 V ≤ V

Analog Input Resistance

inSC

inMONO

SCART Input Resistance from T

= 0 to 70 °C

MONO Input Resistance from T

= 0 to 70 °C

Audio Analog-to-Digital-Converter

AICL

Effective Analog Input Clipping Level for Analog-to-DigitalConversion

I2S_CL,

200 ns CL = 30 pF

I2S_DA_OUT

180 ns CL = 30 pF

I2S_CL,

200 ns CL = 30 pF

I2S_WS

180 ns CL = 30 pF

AGNDC

3.63

3.67

SCn_IN_s

25 40 58 kΩ f

MONO_IN 152435k

SCn_IN_s,

2.00 2.25 V

MONO_IN

3.73

3.77

3.83

3.87VV

Ω f

RMS

≥10 MΩ

load

AGNDC

= 1 kHz, I = 0.05 mA

signal

= 1 kHz, I = 0.1 mA

signal

= 1 kHz

signal

≤ 4 V

SCART Outputs

outSC

OUTSC

SCtoSC

rSCtoSC

outSC

SCART Output Resistance at T

= 27 °C

from T

= 0 to 70 °C

Deviation of DC-Level at SCART Output from AGNDC Voltage

Gain from Analog Input to SCART Output

Frequency Response from Analog Input to SCART Output bandwidth: 0 to 20000 Hz

Effective Signal Level at SCART-Output during full-scale digital input signal from DSP

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”

SCn_OUT_s

SCn_IN_s

MONO_IN

→

SCn_OUT_s

200 200

330 460

500

Ω Ω

signal

−70 +70 mV

−1.0 +0.5 dB f

−0.5 +0.5 dB with respect to 1 kHz

1.8 1.9 2.0 V

RMS

signal

= 1 kHz, I = 0.1 mA

= 1 kHz

72 Micronas

Page 73

PRELIMINARY DATA SHEET MSP 34x0D

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

Main and AUX Outputs

outMA

outDCMA

Main/AUX Output Resistance at T

= 27 °C

from T

= 0 to 70 °C

DC-Level at Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at

−30 dB

DACp_s

)

2.1

3.3 4.6

5.0

k kΩ

Ω

= 1 kHz, I = 0.1 mA

signal

1.80 2.04612.28 V mV

outMA

Effective Signal Level at Main/ AUX-Output during full-scale digital input signal from DSP for Analog Volume at 0 dB

Analog Performa nce

SNR Signal-to-Noise Ratio

from Analog Input to DSP MONO_IN,

from Analog Input to SCART Output

from DSP to SCART Output SCn_OUT_s

from DSP to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at

−30 dB

THD Total Harmonic Distortion

from Analog Input to DSP MONO_IN,

SCn_IN_s

MONO_IN, SCn_IN_s → SCn_OUT_s

DACp_s

SCn_IN_s

1.23 1.37 1.51 V

85 88 dB Input Level = −20 dB with

93 96 dB Input Level = −20 dB,

85 88 dB Input Level = −20 dB,

85 78

88 83

0.01 0.03 % Input Level = −3 dBr with

RMS

dB dB

= 1 kHz

signal

resp. to V equally weighted 20 Hz ...16 kHz

= 1 kHz,

sig

equally weighted

AICL

, f

20 Hz ...20 kHz

= 1 kHz,

sig

equally weighted 20 Hz ...15 kHz

Input Level = f

= 1 kHz,

sig

equally weighted 20 Hz ...15 kHz

resp. to V equally weighted 20 Hz ...16 kHz

AICL

−20 dB,

, f

= 1 kHz,

sig

= 1 kHz,

sig

from Analog Input to SCART Output

from DSP to SCART Output SCn_OUT_s

from DSP to Main or AUX Output DACA_s,

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

DSP measured at I2S-Output

DSP Input at I2S-Input

MONO_IN, SCn_IN_s

→

SCn_OUT_s

DACM_s

0.01 0.03 % Input Level = −3dBr,

= 1 kHz,

sig

0.01 0.03 % Input Level = −3dBr,

equally weighted 20 Hz ...20 kHz

= 1 kHz,

sig

equally weighted 20 Hz ...16 kHz

0.01 0.03 % Input Level = −3dBr,

= 1 kHz,

sig

equally weighted 20 Hz ...16 kHz

Micronas 73

Page 74

MSP 34x0D PRELIMINARY DATA SHEET

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

XTALK Crosstalk attenuation

− PLCC68

− PSDIP64

between left and right channel within SCART Input/Output pair (L

SCn_IN

→ SCn_OUT

SC1_IN or SC2_IN

SC3_IN

DSP

→ DSP PLCC68

→ SCn_OUT

between left and right channel within Main or AUX Output pair

DSP

→ DACp

between SCART Input/Output pairs D = disturbing program

O = observed program D: MONO/SCn_IN

→ SCn_OUT PLCC68

O: MONO/SCn_IN D: MONO/SCn_IN

→ SCn_OUT or unsel. PLCC68

O: MONO/SCn_IN D: MONO/SCn_IN

O: DSP

→ SCn_OUT

→ SCn_OUT PLCC68

D: MONO/SCn_IN → unselected PLCC68 O: DSP

→ SC1_OUT PSDIP64

→R, R→L)

PLCC68

PSDIP64

→ DSP PLCC68

PSDIP64

PLCC68

PSDIP64

PLCC68

PSDIP648075

→ SCn_OUT

→ DSP

PSDIP64

80 80

100 100

100 95

100 100

dB dB

Input Level = f

= 1 kHz, unused ana-

sig

log inputs connected to ground by Z < 1 k

−3dB,

Ω

equally weighted 20 Hz ...20 k Hz

equally weighted 20 Hz ...16 k Hz

(equally weighted 20 Hz ...20 k Hz same signal source on left and right disturbing channel, effect on each observed output channel

Crosstalk between Main and AUX Output pairs

DSP

→ DACp

PLCC68

PSDIP649590

XTALK Crosstalk from Main or AUX Output to SCART Output

and vice-versa

D = disturbing program O = observed program

D: MONO/SCn_IN/DSP O: DSP

→ DACp

D: MONO/SCn_IN/DSP O: DSP

→ DACp

D: DSP

→ DACp PLCC68

O: MONO/SCn_IN D: DSP

→ DACM PLCC68

O: DSP

→ SCn_OUT

“n” means “1”, “2”, “3”, or “4”; “p” means “M” or “A”

DSP measured at I2S-Output

DSP Input at I2S-Input

→ SCn_OUT PLCC68

→ SCn_OUT

PSDIP64

85 80

90 85

100 95

dB dB

(equally weighted 20 Hz ...16 k Hz)

same signal source on left and right disturbing channel, effect on each observed output channel

(equally weighted 20 Hz ...20 k Hz) same signal source on left and right disturbing channel, effect on each observed output channel

SCART output load resistance 10 k

Ω

SCART output load resistance 30 k

Ω

74 Micronas

Page 75

PRELIMINARY DATA SHEET MSP 34x0D

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

PSRR: rejection of noise on AHVSUP at 1 kHz

AGNDC AGNDC 80 dB

S/N

THD

S/N

THD

NICAM

From Analog Input to DSP MONO_IN,

SCn_IN_s

From Analog Input to SCART Output

MONO_IN, SCn_IN_s

SCn_OUT_s From DSP to SCART Output SCn_OUT_s From DSP to MAIN/AUX Output DACp_s FM Input to Main/AUX/SCART

Output Total Harmonic Distortion + Noise

of FM demodulated signal on Main/

DACp_s1),

SCn_OUT_s

DACp_s

SCn_OUT_s AUX/SCART output

Signal to Noise ratio of NICAM baseband signal on Main/AUX/

DACp_s

SCn_OUT_s SCART outputs

Total Harmonic Distortion + Noise of NICAM baseband signal on

DACp_s

SCn_OUT_s Main/AUX/SCART output

70 dB

60 dB 80 dB

73 dB 1 FM-carrier 5.5 MHz,

µs, 1 kHz, 40 kHz devi-

ation; RMS, unweighted 0

0.1 %

to 15 kHz (for S/N); full input range, FM-Prescale = 46 Vol = 0 dB

→ Output Level 1 V

DACp_s

72 dB NICAM: −6dB, 1kHz,

RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7F Output level 1 V DACp_s

0.1 % 2.12 kHz, Modulator input level = 0 dBref SPM = 8

; SPM = 3

SPM = 8

;

h RMS

RMS

BER

S/N

NICAM: Bit Error Rate − 110−7FM+NICAM,

Signal to Noise ratio of AM baseband signal on Main/AUX/SCART

DACp_s

SCn_OUT_s

48 dB SIF input range:

outputs

THD

Total Harmonic Distortion + Noise of AM demodulated signal on Main/

DACp_s

SCn_OUT_s

0.3 %

AUX/SCART output

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “Loudspeaker (M ain)’’ or ‘‘Headphone (AUX)’’ SPM: Short Programming Mode

norm conditions

0.1

−0.8 V

1 kHz, RMS unweighted

; AM = 70 %,

(S/N); 0 to 15 kHz, FM/AM-Prescale = 3C Vol = 0 dB

0.5 V FM+NICAM, norm condi-

→ Output level:

at DACp_s

RMS

hex

tions; SPM = 9

Micronas 75

Page 76

MSP 34x0D PRELIMINARY DATA SHEET

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

IFIN

VREFTOP

ANA_IN

XTALK BW

Input Impedance ANA_IN1+,

ANA_IN2+, ANA_IN

−

DC voltage at VREFTOP

VREFTOP MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later

DC voltage on IF inputs ANA_IN1+,

1.5

6.8

2.4

2.56

9.1

2.6

2.66

2.5

11.4

2.7

2.76VV

1.3 1.5 1.7 V

kΩ kΩ

ANA_IN2+,

ANA_IN

−

Crosstalk attenuation ANA_IN1+,

40 dB f ANA_IN2+, ANA_IN

3 dB Bandwidth 10 MHz

−

AGC AGC Step Width 0.85 dB dV

FMOUT

NICAMOUT

Tolerance of output voltage of FM demodulated signal

Tolerance of output voltage of NICAM baseband signal

FM Frequency Response on Main/ AUX/SCART Outputs,

DACp_s1), SCn_OUT_s

DACp_s

SCn_OUT_s

−1.5 +1.5 dB 1 FM-carrier, 50 µs, 1 kHz,

−1.5 +1.5 dB 2.12 kHz, Modulator input

−1.0 +1.0 dB 1 FM-carrier 5.5 MHz,

Bandwidth 20 to 15000 Hz

NICAM

NICAM Frequency Response on Main/AUX/SCART Outputs,

DACp_s

SCn_OUT_s

−1.0 +1.0 dB Modulator input

Bandwidth 20 to 15000 Hz

Gain AGC = 20 dB Gain AGC = 3 dB

= 1 MHz

signal

Input Level =

−2dBr

40 kHz deviation; RMS

level = 0dBref

µs, Modulator input

level =

−14.6 dBref; RMS

level =

−12 dB dBref; RMS

SEP

NICAM

XTALK

NICAM

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

FM Channel Separation (Stereo) DACp_s1),

SCn_OUT_s

NICAM Channel Separation (Stereo)

DACp_s1), SCn_OUT_s

FM Crosstalk Attenuation (Dual) DACp_s1),

SCn_OUT_s

NICAM Crosstalk Attenuation (Dual)

DACp_s1), SCn_OUT_s

50 dB 2 FM-carriers

5.5/5.74 MHz, 50 1 kHz, 40 kHz deviation; RMS

80 dB

80 dB 2 FM-carriers

5.5/5.74 MHz, 50 1 kHz, 40 kHz deviation; RMS

80 dB

µs,

76 Micronas

Page 77

PRELIMINARY DATA SHEET MSP 34x0D

10. Application Circuit

5 V

DVSS

AHVSS

5 V

DVSS

Tuner 2

Tuner 1

330 nF

330 nF 330 nF

IF2 IN

Signal GND

IF1 IN

56 pF 56 pF 56 pF

ANA_IN1+ (58) 25

28 (55) MONO_IN

31 (52) SC1_IN_L 30 (53) SC1_IN_R

32 (51) ASG1 34 (49) SC2_IN_L

33 (50) SC2_IN_R 35 (48) ASG2

37 (46) SC3_IN_L 36 (47) SC3_IN_R

38 (45) ASG4 40 (43) SC4_IN_L 39 (44) SC4_IN_R

11 (7) STANDBYQ

12 (6) ADR_SEL

8 (10) I2C_DA 9 (9) I2C_CL

1 (16) ADR_WS 68 (17) ADR_CL 3 (15) ADR_DA

6 (12) I2S _WS 7 (11) I2S _CL 4 (14) I2S _DA_IN1 65 (20) I2S_DA_IN2 5 (13) I2S _DA_OUT

µF

(59) 24

−

ANA_IN

ANA_IN2+ (60) 23

VREFTOP (54) 29

MSP 34x0D

if ANA_IN2+ not used

100 nF

3.3 µF100 nF

AGNDC (42) 42

C see section 9.5.2.

+8.0 V

MHz

18.432

XTAL_IN (62) 21

10 µF 10 µF

CAPL_M (40) 44

XTAL_OUT (63) 20

DACM_L (29) 56

DACM_R (28) 57

DACM_SUB (31) 54

DACA_L (26) 59

DACA_R (25) 60

SC1_OUT_L (37) 47

SC1_OUT_R (36) 48

SC2_OUT_L (34) 50

SC2_OUT_R (33) 51

D_CTR_OUT0 (5) 13

D_CTR_OUT1 (4) 14

AUD_CL_OUT (1) 18

TESTEN (61) 22

CAPL_A (38) 46

1 nF

100 Ω

1 µF

Loudspeaker

Headphones

22 µF

AVSS

Alternative circuit for ANA_IN1/2+ for more attenuation of video components:

100 p 56 p

ANA_IN1/2+

1 kΩ

ResetQ (from CCU, see section.

5.3. )

61 (24) RESETQ

100 nF

67 (18) DVSUP

26 (57) AVSUP

66 (19) DVSS

100 nF

5 V 5 V 8.0 V

DVSS

27 (56) AVSS

AVSS

45 (39) AHVSUP

100 nF

43 (41) AHVSS

AHVSS

49 (35) VREF1

58 (27) VREF2

Micronas 77

Page 78

MSP 34x0D PRELIMINARY DATA SHEET

Note: Pin numbers refer to the PLCC68 package; numbers in brackets refer to the PSDIP64 package.

*Application Note:

All ground pins sh ould be con nected to one low-resistive ground plane.

All supply pins should be connected separately with short and low-resisti ve lines to the power supply.

Decoupling capacitors fr om DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most impor tant. We recommend using more than o ne capacitor. By choosing different values, the frequency range of acti ve decoupling ca n be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 est value should be placed ne arest to the DVSUP and DVSS pins.

µF. The capacitor with the low-

The ASG pins should be conn ected as close ly as possible to the MSP to ground. I f they are lead with the SCART input lines as shielding li ne, they should NOT be connected to ground at the SCART connector.

78 Micronas

Page 79

PRELIMINARY DATA SHEET MSP 34x0D

11. Appendix A: MSP 34x0D Version History A1

First hardware release, which is completely compatible to MSP 3410B.

Hardware as A1 with additional features:

– Automatic NICAM-FM switching – Demodulator Short Programming – Automatic Standard Detection

Hardware as A2 with additional features:

– Automatic Volume Correction (AVC) – Subwoofer Output – improved Automatic Standard Detection – extended Short Programming Mode – automatic reset and selection of identification for

Demodulator Short Programming

Hardware and firmware as B3: – Carrier Mute Function not recommended in High-

Deviation Mode

– additional package PLQFP64 – digital input specification changed as of version C5

and later (see section 9.5. on page 66)

– max. analog high supply voltage AHVSUP 8.7 V – supply currents changed as of version C5 and later

(see section 9.5.3. on page 71)

– Pin ASG3 no longer supported

Micronas 79

Page 80

MSP 34x0D PRELIMINARY DATA SHEET

12. Data Sheet History

1. Preliminary data sheet: “MSP 3400D, MSP 3410D Multistandard Sound Processors, Nov. 30, 1998, 6251-482-1PD. First release of the preliminary data sheet.

2. Preliminary data sheet: “MSP 3400D, MSP 3410D Multistandard Sound Processors, May 14, 1999, 6251-482-2PD. Second release of the preliminary data sheet. Major changes:

– specification for version C5 added

(see Appendix A: Version History)

– section 9.: specification for PLQFP64 package

added

Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com

Printed in Germany Order No. 6251-482-2PD

All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infr ingements or other right s of third parties whic h may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its conte nt, at any t ime, withou t obligatio n to noti fy any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH .

80 Micronas

Page 81

MSP 34xxD

Preliminary Data Sheet Supplement

Subject: Data Sheet Concerned:

Supplement: Edition:

MSP 34xxD Family Compatibility Differences:

The MSP-family (MSP 3410D, MSP 3400D, MSP 3415D, MSP 3405D, MSP 3417D, MSP 3407D) is currently avail-

able in different technologies (0.8 µ, 0.5 µ, and 0.45 µ). The specific differences of the various implementations are listed in the attached table.

Compatibility Differences All MSP 34xxD Data Sheets:

6251-482-2PD, 6251-475-2PD, 6251-486-2PD No. 3/ 6251-526-3PDS Oct. 11, 2000

Micronas page 1 of 1

Page 82

Micronas

Compatibility Differences between 0.5/0.45µ and 0.8µ MSPD Devices

H1, H3

H2, H4

MSP 3415D / MSP 3405DMSP 3410D / MSP 3400D

Version Code

Technology

Mask Iteration Code

B4 A2 A1

0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ

67, 6B, 6G 8C and 94

G1, G4

6C, 6D 8D

B3 B2

G2, G5

Feature Documented in

Datasheet Reference

MSP 3400D, MSP 3410D Edit. May 1999

MSP 3405D, MSP 3415D Edit Oct. 1999

General Hardware

Power Consumption Datasheet 910 mW 640 mW 600 mW 910 mW 640 mW 600 mW 910 mW 640 mW 600 mW

Total Electromagnetic Radiation (EMR) - - -

typical

AGNDC0

Digital Input Pin characteristics

(I2S_IN1/2, I2S_WS/CL, StANDBYQ)

VREFTOP

Maximum V

typical

sup1

Datasheet 3.73 V 3.73 V 3.73 V Datasheet 2.6 V 2.6 V 2.6 V Datasheet 8.4 V 8.4 V 8.4 V

Datasheet - - -

due to less Power Consumption

less

due to less Power Consumption

3.77 V

2.66 V

8.7 V

modified specifications

(see datasheet)

less

3.77 V 3.77 V

2.66 V 2.66 V

8.7 V 8.7 V

modified specifications

(see datasheet)

Demodulator

Carrier Mute - - -

AM-Frequency Response

Automatic Standard Detection - - -

- - -

slightly slower, but more stable:

64ms mute, 500 ms demute

more flat more flat

faster, more stable and with mute-

function

slightly slower, but more stable:

64ms mute, 500 ms demute

faster, more stable and with mute-

function

Baseband Processing

J17-Deemphasis for FM-Input channels

I2S-Bus

Frequency response of 50/75µs Deemphasis - - -

DC_Level (DSP-Reg.: 1B

/1C

)

hex

Datasheet

Supplement

Datasheet not available

available available available

- - -

not available

(75µs instead of J17)

available available not available

more flat more flat more flat

Level increased by

appr. 15% 1*)

not available

(75µs instead of J17)

Level increased by

appr. 15% 1*)

MSP 3417D / MSP 3407DMSP-Type

6E, 6F 8F

MSP 3407D, MSP 3417D Edit Jan. 2000

due to less Power Consumption

modified specifications

(see datasheet)

slightly slower, but more stable:

64ms mute, 500 ms demute

faster, more stable and with mute-

not available

(75µs instead of J17)

Level increased by

appr. 15% 1*)

G3, G6,

less

more flat

function

Date: 11.10.00 Page 1 of 2 Pages

Page 83

Micronas

H1, H3

H2, H4

Version Code

Technology

Mask Iteration Code

B4 A2 A1

0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ 0.8µ 0.5µ 0.45µ

67, 6B, 6G 8C and 94

G1, G4

Feature Documented in

D/A-Outputs

S/N-ratio

- - -

improved

Pinning

SCART2_Out pin Datasheet connected

DAC-Headphone pins Datasheet connected

Audio_Clock_Out Datasheet connected

The following pins refer to PQFP80:

Pin 52 Datasheet ASG2 ASG2 ASG2 ASG2

Pin 32 Datasheet ASG3 ASG3 Pin 14 Datasheet not connected DVSS DVSS not connected DVSS DVSS

Pin 16 Datasheet DVSS not connected not connected DVSS not connected not connected

connected not connected connected

connected

not connected

(s. Datasheet P.59)

*1) In spite of increased DC-level controller-algorithms for automatic Sat-Carrier detection should run properly

MSP 3415D / MSP 3405DMSP 3410D / MSP 3400D

6C, 6D 8D

not connected

(s. Datasheet P.51)

MSP 3417D / MSP 3407DMSP-Type

B3 B2

G2, G5

improved improved

not connected

6E, 6F 8F

not connected not connected

not connected

MSP 34x7D not available in 80-PQFP

MSP 34x7D not available in 80-PQFP MSP 34x7D not available in 80-PQFP

MSP 34x7D not available in 80-PQFP

G3, G6,

Date: 11.10.00 Page 2 of 2 Pages

Datasheet MSP3400D, MSP3410D Datasheet (Micronas Intermetall)

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

2.1. Demodulator and NICAM Decoder Section

2.2. DSP Section (Audio Baseband Processing)

2.3. Analog Section

4.1. Demodulator and NICAM Decoder Section

4.1.1. Analog Sound IF – Input Section

4.1.2. Quadrature Mixers

4.1.3. Low-pass Filtering Block for Mixed Sound IF Signals

4.1.4. Phase and AM Discrimination

4.1.5. Differentiators

4.1.7. High-Deviation FM Mode

4.1.8. FM Carrier Mute Function in the Dual-Carrier FM Mode

4.1.9. DQPSK Decoder

4.1.10. NICAM Decoder

4.2. Analog Section

4.2.1. SCART Switching Facilities

4.3. DSP Section (Audio Baseband Processing)

4.3.1. Dual-Carrier FM Stereo/Bilingual Detection

4.2.2. Stand-by Mode

4.4. Audio PLL and Crystal Specifications

4.5. ADR Bus Interface

4.6. Digital Control Output Pins

4.7. I2S Bus Interface

5. I2C Bus Interface: Device and Subaddresses

5.1. Protocol Description

5.2.1. Symbols

5.2.2. Write Telegrams

5.2.3. Read Telegrams

5.2.4. Examples

6.2. Demodulator Write Registers: Table and Addresses

6.3. Demodulator Read Registers: Table and Addresses

6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values

6.5.1. Re gister ‘AD_CV’

6.5.2. Re gister ‘MODE_REG’

6.5.3. FIR Parameter

6.5.4. DCO Registers

6.6. Demodulator Read Registers: Functions and Values

6.6.1. Autodetection of T errestrial TV A udio Standar ds

6.6.2. C_AD_BITS

6.6.4. CIB_BITS

6.6.9. AGC_GAIN

6.7. Sequences to Transmit Parameters and to Start Processing

6.6.8. PLL_CAPS

6.8. Software Proposals for Multistandard TV Sets

6.8.4. Satellite Mode

6.8.5. Automatic Search Function for FM Carrier Detection

7. Programming the DSP Section (Audio Baseband Processing)

7.1. DSP Write Registers: Table and Addresses

7.2. DSP Read Registers: Table and Addresses

7.3. DSP Write Registers: Functions and Values

7.3.6. Spatial Effects – Loudspeaker Channel There are several spatial effect modes available:

7.3.7. Volume – SCART1 and SCART2 Channel 7.3.8. Channel Source Modes

7.3.9. Channel Matrix Modes

7.3.10. SCART Prescale

7.3.11. FM/AM Prescale For the High Deviation Mode, the FM prescaling val-

7.3.13. FM Fixed Deemphasis

7.3.14. FM Adaptive Deemphasis

7.3.15. NICAM Prescale

7.3.16. NICAM Deemphasis

7.3.18. ACB Register

7.3.19. B eeper

7.3.20. Identification Mode

7.3.21. FM DC Notch

7.3.22. Mode Tone Control

7.3.23. Automatic Volume Correction (AVC)

7.3.24. Subwoof er Channel

7.3.25. Equalizer Loudspeaker Channel

7.5. Phase Relationship of Analog Outputs

7.4. Exclusions for the Audio Baseband Features

7.6. DSP Read Registers: Functions and Values

7.6.1. Stereo Detection Register

7.6.3. DC Level Register

7.6.5. MSP Major Revision Code

7.6.6. MSP Product Code

7.6.7. MSP ROM Version Code

7.6.4. MSP Hardware Version Code