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MSM82C54-2JS
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Datasheet MSM82C54-2GS-K, MSM82C54-2JS, MSM82C54-2RS Datasheet (OKI)

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Page 1
E2O0019-27-X2
¡ Semiconductor MSM82C54-2RS/GS/JS
¡ Semiconductor
This version: Jan. 1998
Previous version: Aug. 1996
MSM82C54-2RS/GS/JS
CMOS PROGRAMMABLE INTERVAL TIMER
GENERAL DESCRIPTION
The MSM82C54-2RS/GS/JS is a programmable universal timer designed for use in microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current of only 10 mA (max.) when the chip is in the non-selected state. And during timer operation, the power consumption is still very low with only 10mA (max.) of current required. It consists of three independent counters, and can count up to a maximum of 10 MHz. The timer features six different counter modes, and binary count/BCD count functions. Count values can be set in byte or word units, and all functions are freely programmable.
FEATURES
• Maximum operating frequency of 10 MHz (VCC=5 V)
• High speed and low power consumption achieved by silicon gate CMOS technology
• Completely static operation
• Three independent 16-bit down-counters
• Status Read Back Command
• Six counter modes available for each counter
• Binary and decimal counting possible
• 24-pin Plastic DIP (DIP24-P-600-2.54): (Product name: MSM82C54-2RS)
• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C54-2JS)
• 32-pin Plastic SSOP (SSOP32-P-430-1.00-K): (Product name: MSM82C54-2GS-K)
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¡ Semiconductor MSM82C54-2RS/GS/JS
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
8
D
- D
7
0
Data
Bus
Buffer
Counter
#0
CLK
GATE
OUT
0
0
0
8
WR
RD
A A
Read/
Write
0
1
Logic
Counter
#1
CLK
GATE
OUT
1
1
1
CS
Control
Word
Register
Counter
#2
CLK
GATE
OUT
2
2
2
Internal Bus
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¡ Semiconductor MSM82C54-2RS/GS/JS
(
)
PIN CONFIGURATION (TOP VIEW)
24 pin Plastic DIP
32 pin Plastic SSOP
GATE
CLK
OUT
GATE
GND
CLK
OUT
GND
NC
D D D
NC
D D D D D
NC
NC
D
1
7
D
2
6
D
3
5
D
4
4
D
5
3
D
6
2
D
7
1
D
8
0
9
0
10
0
11
0
12
1 2
7
3
6
4
5
5 6
4
7
3
8
2
9
1
10
0
11
0
12 13
0
14
0
15 16
24
23
22
21
20
19
18
17
16
15
14
13
32 31 30 29 28 27 26 25 24 23
22 21 20 19 18 17
V
cc
WR
RD
CS
A
1
A
0
CLK
OUT
GATE
CLK
GATE
OUT
NC V
cc
WR RD
NC
CS
A
1
A
0
CLK OUT
GATE NC CLK GATE OUT NC
2
2
2
1
1
1
2
2
2
1
1
1
28 pin Plastic QFJ
CLK
NC
5D6D7
D
4
D
5
4
D
6
3
D
7
2
D
8
1
D
9
0
10
0
11
12
0
OUT
3
13
0
GATE
2
14
GND
NC
1
15
NC
VCCWR
28
27
16
17
1
1
OUT
GATE
RD
26
18
1
CLK
25
24
23
22
21
20
19
NC
CS
A
1
A
0
CLK
OUT
GATE
2
2
2
NC denotes "not connected".
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¡ Semiconductor MSM82C54-2RS/GS/JS
ABSOLUTE MAXIMUM RATING
Parameter Unit
Power Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
Symbol
V
CC
V
IN
V
OUT
T
STG
P
D
Condition
With
respect to GND
—
Ta = 25°C
MSM82C54-2RS
MSM82C54-2GS MSM82C54-2JS
–0.5 to +7
–0.5 to V
–0.5 to V
CC
CC
+0.5
+0.5
–55 to +150
0.7
0.90.9
RECOMMENDED OPERATING CONDITIONS
Rating
Parameter UnitSymbol
Power Supply Voltage
Operating Temperature
"L" Input Voltage V
"H" Input Voltage
Min.
V
CC
T
op
IL
V
IH
4.5
–40
–0.5
2.2
Typ.
5V
+25
—
—
Max.
V
CC
5.5
+85
+0.8
+ 0.5
DC CHARACTERISTICS
V
V
V
°C
W
°C
V
V
Parameter Unit
"L" Output Voltage
"H" Output Voltage
Input Leak Current
Output Leak Current
Standby Supply Current
Symbol
V
OL
V
OH
I
LI
I
LO
I
CCS
I
OL
I
OH
I
OH
0 £ V
0 £ V
cs ≥ V
V
≥ V
IH
V
IH £
Conditions
= 2.5 mA
= –2.5 mA
= –100 mA
£ V
IN
CC
£ V
OUT
CC
CC
CC
–0.2 V
–0.2 V
0.2 V
V
= 4.5 V to 5.5 V
CC
Ta
= –40°C to +85°C
V
CC
Min.
—
3.0
–0.4
–10
–10
—
Typ. Max.
—
—
—
—
—
—
Operating Supply Curent
I
t
CC
=100 ns, CL = O pF
CLK
—
—
0.4 V
—V
—V
10 mA
10 mA
10
mA
10 mA
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¡ Semiconductor MSM82C54-2RS/GS/JS
AC CHARACTERISTICS
= 4.5 V to 5.5 V, Ta = –40°C to +85°C)
(V
CC
Parameter
Address Set-up Times to Falling Edge of RD Chip Select Input Set-up Time to Falling Edge of RD Address Hold Time from Rising Edge of RD RD Pulse Width
Data Access Time from Falling Edge of RD
Data Access Time after Address Determination Delay Time from Rising Edge of RD to Data Floting State RD Recovery Time Address Set-up Time to Falling Edge of WR Chip Select Input Set-up Time to Falling Edge of WR Address Hold Time from Rising Edge of WR WR Pulse Width Data Determination Set-up Time to Rising Edge of WR Data Hold Time after Rising Edge of WR WR Recovery Time
CLK Cycle Time
CLK "H" Level Width
CLK "L" Level Width
CLK Rise Time
CLK Fall Time
GATE "H" Level Width
GATE "L" Level Width
GATE Input Set-up Time before Rising Edge of CLK
GATE Input Hold Time before Rising Edge of CLK
Output Delay Time after Falling Edge of CLK
Output Delay Time after Falling Edge of GATE CLK Rise Delay Time after Rising Edge of WR for Count Value
Loading
t
t
t
t t
RD
t
t
t
t
AW
t
SW
t
WA
t
WW
t
DW
t
WD
t
t
CLK
t
PWH
t
PWL
t
GW
t
t
t
t
t
ODG
t
WC
AR
SR
RA
RR
AD
DF
RV
RV
t
t
GL
GS
GH
OD
r
f
82C54-2
Min. Max.
30
0
0
95
—ns
—ns
—ns
—ns
—94
—
5
165
0
0
0
95
85
0
165
100
30
50
—
—
50
50
40
50
—
—
0
184 ns
65 ns
—ns
—ns
—ns
—ns
—ns
—ns
—ns
—ns
D.C. ns
—ns
—ns
25 ns
25 ns
—ns
—ns
—ns
—ns
100 ns
100 ns
55 ns
UnitSymbol
Conditions
ns
Read Timing
Write Timing
CL = 150 pF
Clock Gate Timing
GATE sampling delay time after rising edge of WR for count loading
CLK Fall Set-up Time to Falling Edge of WR for Counter Latch Command
t
WG
t
WO
t
CL
–5
—
–40
40 ns
240 nsOutput Delay Time after Falling Edge of WR for Mode Set
40 ns
Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
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¡ Semiconductor MSM82C54-2RS/GS/JS
TIMING CHART
WriteTiming
A
0 - 1
Read Timing
D
CS
0 - 7
WR
t
AW
t
SW
t
DW
t
WW
t
WA
t
WD
A
0 - 1
CS
RD
D
0 - 7
Recovery Timing
RD, WR
Clock & Gate Timing
t
AR
t
SR
t
RR
t
RD
t
RA
t
DF
Valid
t
AD
t
RV
WR
CLK
GATE
OUT
Mode Count
t
PWH
t
PWL
t
f
t
WO
t
t
r
WG
t
WC
t
GH
Counter
Latch
t
CLK
t
GS
t
GL
t
ODG
t
GW
t
OD
t
GS
t
GH
t
CL
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¡ Semiconductor MSM82C54-2RS/GS/JS
DESCRIPTION OF PIN FUNCTIONS
Pin Symbol
D7 - D
0
CS
RD
WR
A
, A
0
1
CLK0 -
2
GATE
-
0
2
Name
Bidirectional
Data Bus
Chip Select
Input
Read Input
Input/Output
Input/Output
Input
Input
Write Input Input
Address Input Input
Clock Input
Input
Gate Input Input
Function
Three-state 8-bit bidirectional data bus used when writing control words and count value, and reading count values upon reception of WR and RD signals from CPU.
Data transfer with the CPU is enabled when this pin is at low level. When at high level, the data bus (D
thru D7) is switched to high
0
impedance state where neither writing nor reading can be executed. Internal registers, however, remain unchanged.
Data can be transferred from MSM82C54-2 to CPU when this pin is at low level.
Data can be transferred from CPU to MSM82C54-2 when this pin is at low level.
One of the three internal counters or the control word register is selected by A
combination. These two pins are normally
0/A1
connected to the two lower order bits of the address bus.
Supply of three clock signals to the three counters incorporated in MSM82C54-2.
Control of starting, interruption, and restarting of counting in the three respective counters in accordance with the set control word contents.
OUT
- 2Counter Output Output
0
SYSTEM INTERFACING
A1A
0
A1A0CS
Counter #0
OUT GATE CLK
Output of counter output wave form in accordance with the set mode and count value.
Adress Bus
16 bits
Control Bus
Data Bus
8 bits
8 bits
0
RD WR
D
-
7
MSM82C54-2
Counter #1
OUT GATE CLK
Counter #2
OUT GATE CLK
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¡ Semiconductor MSM82C54-2RS/GS/JS
DESCRIPTION OF BASIC OPERATIONS
Data transfers between the internal registers and external data bus is outlined in the following table.
CS
0
0
0 0
0
0
0
0
1
0
RD
1
1
1 1
0
0
0
0
¥
1
WR
0
0
0 0
1
1
1
1
¥
1
A
¥
A
1
0
0
1 1
0
0
1
1
¥
0
0
1
0 1
0
1
0
Data Bus to Counter #0 Writing
Data Bus to Counter #1 Writing
Data Bus to Counter #2 Writing
Data Bus to Control Word Register Writing
Data Bus from Counter #0 Writing
Data Bus from Counter #1 Writing
Data Bus from Counter #2 Writing
1
¥
Data Bus in High Impedance Status
¥
Function
¥: denotes "not specified"
DESCRIPTION OF OPERATION
MSM82C54-2 functions are selected by control words from the CPU. In the required program sequence, the control word setting is followed by the count value setting and execution of the desired timer operation.
Control Word and Count Value Program
Each counter operating mode is set by control word programming. The control word format is outlined below.
D
7
SC1
Select Counter Read/Load Mode BCD
D
SC0
6
D
5
RL1
D
RL0
4
D
3
M2
D
2
M1
(CS=0, A
D
1
M0
, A1=1, 1, RD=1, WR=0)
0
D
BCD
0
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¡ Semiconductor MSM82C54-2RS/GS/JS
• Select Counter (SC0, SC1): Selection of set counter
SC1
0
0
1 1
SC0
0
1
0 1
Counter #0 selection
Counter #1 selection Counter #2 selection
Read Back Command
Set Contents
• Read/Load (RL1, RL0): Count value Reading/Loading format setting
RL1
0
0
1 1
RL0
0
1
0 1
Counter Latch Operation
Reading/Loading of Least Significant Byte (LSB) Reading/Loading of Most Significant Byte (MSB)
Reading/Loading of LSB followed by MSB
Set Contents
• Mode (M2, M1, M0): Operation waveform mode setting
M2 Set Contents
M1
0
0
¥
¥
M0
0
0
1 1
0
1
0 1
Mode 0 (Interruput on Terminal Count)
Mode 1 (Programmable One-Shot)
Mode 2 (Rate Generator)
Mode 3 (Square Wave Generator)
1 1
¥: denotes "not specified"
0 0
0 1
Mode 4 (Software Triggered Strobe) Mode 5 (Hardware Triggered Strobe)
• BCD: Operation count mode setting
BCD
0
1
Binary Count (16-bit Binary)
BCD Count (4-decade Binary Coded Decimal)
Set Contents
After setting Read/Load, Mode and BCD in each counter as outlined above, next set the desired count value. (In some Modes, the count value is set first. In next clock, loading is performed, then counting starts.) This count value setting must conform with the Read/Load format set in advance. Note that the internal counters are reset to 0000H during control word setting. The counter value (0000H) can’t be read. The program sequence of the MSM82C54-2 is flexible. Free sequence programming is possible as long as the two following rules are observed: (i) Write the control word before writing the initial count value in each counter. (ii) Write the initial count value according to the count value read/write format specified by the
control word.
Note: Unlike the MSM82C53-2, the MSM82C54-2 allows count value setting for another
counter between LSB and MSB settings.
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¡ Semiconductor MSM82C54-2RS/GS/JS
• Example of control word and count value setting
Counter #0: Read/Load LSB only, Mode 3, Binaty count, count value 3H
Counter #1: Read/Load MSB only, Mode 5, Binaty count, count value AA00H
Counter #2: Read/Load LSB and MSB, Mode 0, BCD count, count value 1234
MVI A, 1EH OUT n3
MVI A, 6AH OUT n3
MVI A, B1H OUT n3
MVI A, 03H OUT n0
MVI A, AAH OUT n1
MVI A, 34H OUT n2
MVI A, 12H OUT n2
Counter #0 control word setting
Counter #1 control word setting
Counter #2 control word setting
Counter #0 count value setting
Counter #1 count value setting
Counter #2 count value setting (LSB then MSB)
Notes: n0: Counter #0 address
n1: Counter #1 address n2: Counter #2 address n3: Control word register address
• The minimum and maximum count values which can be counted in each mode are listed below.
Mode Remarks
0
1
2 3
4 5
MIn.
1
1
2 2
1 1
Max.
0
0
0 0
0 0
0 executes 10000H count (ditto in other mdoes)
—
1 cannot be counted
1 cannot be counted
— —
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¡ Semiconductor MSM82C54-2RS/GS/JS
Internal Block Diagram of a Counter
Internal Data Bus
Control
Word
Register
Control
Logic
Status
Latch
Status
Register
CR
OL
M
CR
L
CE
M
OL
L
CLK
GATE
n
n
OUT
n
NOTE : CRM :
CR CE : OL OL
Count Register MSB Count Register LSB
:
L
Counter Element Output Latch MSB
:
M
Output Latch LSB
:
L
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¡ Semiconductor MSM82C54-2RS/GS/JS
Mode definition
Mode 0
• Application: Event counter
• Output operation: The output is set to “L” level by the control word setting, and kept at “L” level until the counter value becomes 0.
• Gate function: “H” level validates the count operation, and “L” level invalidates it. The gate does not affect the output.
• Count value load timing: after the control word and initial count value are written, the count value is loaded to the CE at the falling edge of the next clock pulse. The first clock pulse does not cause the count value to be decremented. In other words, if the initial count value is N, the output is not set to “H” level until the input of (N+1) the clock pulse after the initial count value writing.
• Count value writing during counting: The count value is loaded in the CE at the falling edge of the next clock, and counting with the new count value continues. The operation for 2-byte count is as follows:
1) The counting operation is suspended when the first byte is written. The output is
immediately set to “L” level. (no clock pulse is required.)
2) After the second byte is written, the new count value is loaded to the CE at the falling edge
of the next clock. For the output to go to “H” level again, N+1 clock pulse are necessary after new count value N is written.
• Count value writing when the gate signal is “L” level: The count value is also loaded to the CE at the falling edge of the next clock pulse in this case. When the gate signal is set to “H” level, the output is set to “H” level after the lapse of N clock pulses. Since the count value is already loaded in the CE, no clock pulse for loading in the CE is necessary.
Mode 1
• Application: Digital one-shot
• Output operation: The output is set to “H” level by the control word setting. It is set to “L” level at the falling edge of the clock succeeding the gate trigger, and kept at “L” level until the counter value becomes 0. Once the output is set to “H” level, it is kept at “H” level until the clock pulse succeeding the next trigger pulse.
• Count value load timing: After the control word and initial count value are written, the count value is loaded to the CE at the falling edge of the clock pulse succeeding the gate trigger and set the output to “L” level. The one-shot pulse starts in this way. If the initial count value is N, the one-shot pulse interval equals N clock pulses. The one-shot pulse is not repetitive.
• Gate function: The gate signal setting to “L” level after the gate trigger does not affect the output. When it is set to “H” level again from “L” level, gate retriggering occurs, the CR count value is loaded again, and counting continues.
• Count value writing during counting It does not affect the one-shot pulse being counted until retriggering occurs.
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¡ Semiconductor MSM82C54-2RS/GS/JS
Mode 2
• Application: Rate generator, real-time interrupt clock.
• Output operation: The output is set to “H” level by control word setting. When the initial count value is decremented to 1, the output is set to “L” level during one clock pulse, and is then set to “H” level again. The initial count value is reloaded, and the above sequence repeats. In mode 2, the same sequence is repeated at intervals of N clock pulses if the initial count value is N for example.
• Gate function: “H” level validates counting, and “L” level invalidates it. If the gate signal is set to “L” level when the output pulse is “L” level, the output is immediately set to “H” level. At the falling edge of the clock pulse succeeding the trigger, the count value is reloaded and counting starts. The gate input can be used for counter synchronization in this way.
• Count value load timing: After the control word and initial count value is written, the count value is loaded to the CE at the falling edge of the next clock pulse. The output is set to “L” level upon lapse of N clock pulses after writing the initial count value N. Counter synchronization By software is possible in this way.
• Count value writing during counting: Count value writing does not affect the current counting operation sequence. If new count value writing completes and the gate trigger arrives before the end of current counting operation, the count value is loaded to the CE at the falling edge of next clock pulse and counting continues from the new count value. If no gate trigger arrives, the new count value is loaded to the CE at the end of the current counting operation cycle. In mode 2, count value of 1 is prohibited.
Mode 3
• Application: Baud rate generator, square wave generator
• Output operation: Same as mode 2 except that the output duty is different. The output is set to “H” level by control word setting. When the count becomes half the initial count value, the output is set to “L” level and kept at “L” level during the remainder of the count. Mode 3 repeats the above sequence periodically. If the initial count value is N, the output becomes a square wave with a period of N.
• Gate operation: “H” level validates counting, and “L” level invalidates it. If the gate signal is set to “L” level when the output is “L” level, the output is immediately set to “H” level. The initial count value is reloaded at the falling edge of the clock pulse succeeding the next gate trigger. The gate can be used for counter synchronization in this way.
• Count value load timing: After the control word and initial count value are written, the count value is loaded to the CE at the falling edge of the next clock pulse, Counter synchronization by software is possible in this way.
• Count value writing during counting: The count value writing does not affect the current counting operation. When the gate trigger input arrives before the end of a half cycle of the square wave after writing the new count value, the new count value is loaded in the CE at the falling edge of the next clock pulse, and counting continues using the new count value. If there is no gate trigger, the new count value is loaded at the end of the half cycle and counting continues.
• Even number counting operation: The output is initially set to “H” level. The initial count value is loaded to the CE at the falling edge of the next clock pulse, and is decremented by 2 by consecutive clock pulses. When the counter value becomes 2, the output is set to “L” level, the initial value is reloaded and then the above operation is repeated.
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¡ Semiconductor MSM82C54-2RS/GS/JS
• Odd number counting operation: The output is initially set to “H” level. At the falling edge of the next clock pulse, the initial count value minus one is loaded in the CE, and then the value is decremented by 2 by consecutive clock pulses. When the counter value becomes 0, the output is set to “L” level, and then the initial count value minus 1 is reloaded to the CE. The value is then decremented by 2 by consecutive clock pulses. When the counter value becomes 2, the output is again set to “H” level and the initial count value minus 1 is again reloaded. The above operations are repeated. In other words, the output is set to “H” level during (N+1)/2 counting and to “L” level during (N-1)/2 counting in the case of odd number counting.
Mode 4
• Application: Software trigger strobe
• Output operation: The output is initially set to “H” level. When the counter value becomes 0, the output goes to “L” level during one clock pulse, and then restores “H” level again.
The count sequence starts when the initial count value is written.
• Gate function: “H” level validates counting, and “L” level invalidates counting. The gate signal does not affect the output.
• Count value load timing: After the control word and initial count value are written, the count value is loaded to the CE at the falling edge of the next clock pulse. The clock pulse does not decrement the initial count value. If the initial count value is N, the strobe is not output unless N+1 clock pulses are input after the initial count value is written,
• Count value writing during counting: The new count value is written to the CE at the falling edge of the next clock pulse, and counting continues using the new count value. The operation for 2-byte count is as follows:
1) First byte writing does not affect the counting operation.
2) After the second byte is written, the new count value is loaded to the CE at the falling edge
of the next clock pulse. This means that the counting operation is retriggered by software. The output strobe is set to “L” level upon input of N+1 clock pulses after the new count value N is written.
Mode 5
• Application: Hardware trigger strobe
• Output operation: The output is initially set to “H” level. When the counter value becomes 0 after triggering by the rising edge of the gate pulse, the output goes to “L” level during one clock pulse, and then restores “H” level.
• Count value load timing: Even after the control word and initial count value are written, loading to the CE does not occur until the input of the clock pulse succeeding the trigger. For the clock pulse for CE loading, the count value is not decremented. If the initial count value is N, therefore, the output is not set to “L” level until N+1 clock pulses are input after triggering.
• Gate function: The initial count value is loaded to the CE at the falling edge of the clock pulse succeeding gate triggering. The count sequence can be retriggered. The gate pulse does not affect the output.
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¡ Semiconductor MSM82C54-2RS/GS/JS
• Count value writing during counting: The count value writing does not affect the current counting sequence. If the gate trigger is generated after the new count value is written and before the current counting ends, the new count value is loaded to the CE at the falling edge of the next clock pulse, and counting continues using the new count value. The various roles of the gate input signals in the above modes are summarized in the following table.
Gate
Mode
0
1
2
3
4 Counting not possible
5
"L" Level Falling Edge
Counting not possible
(1)
Counting not possible
(2)
Counter output forced to "H" level
(1)
Counting not possible
(2)
Counter output forced to "H" level
Rising Edge
(1)
Start of counting
(2)
Retriggering
Start of counting Counting possible
Start of counting Counting possible
(1)
Start of counting
(2)
Retriggering
"H" Level
Counting possible
Counting possible
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¡ Semiconductor MSM82C54-2RS/GS/JS
Mode 0
CLK
WR
OUT
WR
(GATE = "H")
43210 210
(n=4)
(n=2)(n=4)
Mode 1
Mode 2
Mode 3
GATE
OUT
CLK
WR
GATE
OUT
GATE
OUT
CLK
WR
OUT
GATE
OUT
CLK
WR
OUT
(n=4)
(n=4)
(GATE = "H")
(n=4)
(n=4)
(GATE = "H")
4 3210
43210
43243 210
(n=2)(n=4)
43214 121
43214
42424
32 2
4321
(n=3)
24232 33
Mode 4
Mode 5
GATE
OUT
CLK
WR
OUT
GATE
OUT
CLK
GATE
OUT
GATE
OUT
42042
(n=5)
(GATE = "H")
(n=4)
(n=4)
43210
43214 3
43210
4
Note : "n" is the value set in the counter.
Figures in these diagrams refer to counter values.
42042 42
3210
210
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¡ Semiconductor MSM82C54-2RS/GS/JS
Reading Counter Values
(1) Direct reading
Counter values can be read by direct reading operations. Since the counter value read according to the timing of the RD and CLK signals is not guaranteed, it is necessary to stop the counting by a gate input signal, or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read.
(2) Counter latching
In this method, the counter value is latched by writing counter latch command, thereby enabling a stable value to be read without effecting the counting in any way at all. The output latch (OL) of the selected counter latches the count value when a counter latch command is written. The count value is held until it is read by the CPU or the control word is set again. If a counter latch command is written again before reading while a certain counter is latched, the second counter latch command is ignored and the value latched by the first counter latch command is maintained. The MSM82C54-2 features independent reading and writing from and to the same counter. When a counter is programmed for the 2-byte counter value, the following sequence is possible:
1. Count value (LSB) reading
2. New count value (LSB) writing
3. Count value (MSB) reading
4. New count value (MSB) writing
An example of a counter latching program is given below.
Counter latching executed for counter #1 (Read/Load 2-byte setting)
0 1 0 0 ¥ ¥ ¥ ¥MVI A
Denotes counter latching
OUT n3
IN n1
MOV B, A IN n1 MOV C, A
Write in control word address (n3)
The counter value at this point is latching
Reading of the LSB of the counter value latched from counter #1.
n1: Conter #1 address
Reading of MSB from counter #1
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¡ Semiconductor MSM82C54-2RS/GS/JS
(
)
(3) Read Back Command Operation
Use of the read back command enables the user to check the count value, program mode, output pin state and null count flag of the selected counter. The command is written in the control word register, and the format is as shown below. For this command, the counter selection occurs according to bits D3, D2 and D1.
D
7
1
D
6
1
D
5
COUNT
D
4
STATUS
D
3
CNT2
D
2
CNT1
D
1
CNT0
D
0
0
(CS=0, A0, A1=1, RD=1, WR=0)
: 0 = Selected counter latch operation
D
5
: 0 = Selected counter status latch operation
D
4
: 1 = Counter #2 selection
D
3
: 1 = Counter #1 selection
D
2
: 1 = Counter #0 selection
D
1
: 0 = Fixed
D
0
It is possible to latch multiple counters by using the read back command. Latching of a read counter is automatically canceled but other counters are kept latched. If multiple read back commands are written for the same counter, commands other than the first one are ignored. It is also possible to latch the status information of each counter by using the read back command. The status of a certain counter is read when the counter is read. The counter status format is as follows: Bits D5 to D0 indicate the mode programmed by the most recently written control word. Bit D7 indicates the status of the output pin. Use of this bit makes it possible to monitor the counter output, so the corresponding hardware may be omitted.
D
7
OUTPUT
D
6
NULL
COUNT
D
RL1
5
D
RL0
4
D
3
M2
D7: 1 = Output pin status is 1.
0 = Output pin status is 0.
D
: 1 = Null count
6
0 = Count value reading is effective
D
- D0: Programmed mode of counter
5
See the control word format.
D
M1
2
D
1
M0
D
BCD
0
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¡ Semiconductor MSM82C54-2RS/GS/JS
Null count indicates the count value finally written in the counter register (CR) has been loaded in the counter element (CE). The time when the count value was loaded in the CE depends on the mode of each counter, and it cannot be known by reading the counter value because the count value does not tell the new count value if the counter is latched. The null count operation is shown below.
Operation Result A. Control word register writing Null count = 1 B. Count register (CR) writing Null count = 1 C. New count loading to CE (CRÆCE) Null count = 0
Note: The null count operation for each counter is independent. When the 2-byte count
is programmed, the null count is set to 1 when the count value of the second byte is written.
If status latching is carried out multiple times before status reading, other than the first status latch is ignored. Simultaneous latching of the count and status of the selected counter is also possible. For this purpose, set bits D4 and D3, COUNT and STATUS bits, to 00. This is functionally the same as writing two separate read back commands at the same time. If counter/status latching is carried out multiple times before each reading, other than the first one is ignored here again. The example is shown below.
Counter 0 Counter 1Command Counter 2
Count Status Count Status Count Status
L
LL—L——
LL—
LL—LLL
LLL
L
L————
L
—L
L
LL
L
(NOTE)
(NOTE)
(NOTE)
LLLL
D7D6D5D4D3D2D1D
1000010
1
1100100
1
1101100
1
1011000
1
1000100
1
1100010
1
0
Contents
Read back status and count (counter 0)
Read back status (counter 1)
Read back status (counter 1 and 2)
Read back status (counter 2)
Read back status and count (counter 1)
Read back status (counter 0)
Note: The latch command at this time point is ignored, and the first latch command is valid.
If both the count and status are latched, the status latched in the first counter read operation is read. The order of count latching and status latching is irrelevant. The count(s) of the next one or two reading operations is or are read.
Note: There is the possibility of glitch noise in the output low level when reading out the data.
Peak voltage in typical condition (5 V, 25°C) is approximately 1V and in the worst condition (5.5 V, –40°C) is approximately 1.4V.
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¡ Semiconductor MSM82C54-2RS/GS/JS
g
Example of Practical Application
• MSM82C54-2 used as a 32-bit counter.
MSM82C54 -2
CLK0OUT
CLK1OUT
CLK2OUT
0
1
2
Use counter #1 and counter #2
Counter #1: mode 0, upper order 16-bit counter value
Counter #2: mode 2, lower order 16-bit counter value
This settin
enables counting up to a maximum of 232.
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¡ Semiconductor MSM82C54-2RS/GS/JS
PACKAGE DIMENSIONS
(Unit : mm)
DIP24-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more
3.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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¡ Semiconductor MSM82C54-2RS/GS/JS
(Unit : mm)
QFJ28-P-S450-1.27
Spherical surface
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more
1.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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¡ Semiconductor MSM82C54-2RS/GS/JS
(Unit : mm)
SSOP32-P-430-1.00-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more
0.60 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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