Page 1
E2E1026-27-Y4
¡ Semiconductor MSM66101
¡ Semiconductor
This version: Jan. 1998
Previous version: Nov. 1996
MSM66101
OLMS-66K Series 16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66101 is a high performance microcontroller that employs OKI original nX-8/100 CPU
core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit timers, 10bit A/D converter, serial I/O port, and pulse width modulator (PWM).
FEATURES
• 64K address space for program memory : Internal ROM : 12K bytes
• 64K address space for data memory : Internal RAM : 384 bytes
• High-speed execution
Minimum cycle for instruction : 400ns @ 10MHz
• Powerful instruction set : Instruction set superior in orthogonal matrix
8/16-bit data transfer instructions
8/16-bit arithmetic instructions
Multiplication and division operation
instructions
Bit manipulation instructions
Bit logic instrucitons
ROM table reference instructions
• Abundant addressing modes : Register addressing
Page addressing
Pointing register indirect addressing
Stack addressing
Immediate value addressing
• I/O port
Input-output port : 5 ports ¥ 8 bits
(Each bit can be assigned to input or output)
Input port : 1 port ¥ 8 bits
• Built-in multifunctional 16-bit timer : 2
Following 4 modes can be set for each timer :Auto-reload timer mode
Clock output mode
Capture register mode
Real time output mode
• Serial port : 1 channel
generator)
• 12-bit pulse width modulator : 2
• Watchdog timer
• Transition detector : 4
• 10-bit A/D converter : 8 channels
• Interrupts
Nonmaskable : 1
Maskable : Internal 10/external 2
• Stand-by function
STOP mode : Software clock stop mode
HALT mode : Software CPU stop mode
HOLD mode : Hardware CPU stop mode
(UART mode with baud rate
1/28
Page 2
¡ Semiconductor MSM66101
• Package options:
64-pin plastic shrink DIP (SDIP64-P-750-1.78) : (Product name: MSM66101-¥¥¥SS)
64-pin plastic QFP (QFP64-P-1414-0.80-BK) :
68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27) : (Product name: MSM66101-¥¥¥JS)
64-pin ceramic piggyback (ADIP64-C-750-1.78) : (Product name: MSM66G101VS)
* The piggyback type is used only for engineering samples.
¥¥¥ indicates the code number.
(Product name: MSM66101-¥¥¥GS-BK)
2/28
Page 3
¡ Semiconductor MSM66101
BLOCK DIAGRAM
A8 /P1.0
EA
READY
ALE
PSENRDWR
AD0/P0.0
AD7/P0.7
A15/P1.7
SSP LRB
BUS P
O
RAM
PSW
R
384 ¥ 8 bits
T
C
O
N
CONT.
MEMORY
ALU
.
T
PORT
P2 P3 P4 P5
P1
P0
PC
ROM
12K ¥ 8 bits
IR
RAP
DEC.
INSTRUCTION
HLDA/P2.5
HOLD/P2.4
CONT.
FLT
RES
OSC1
OSC0
GND
V
DD
ALU CONT.
R.
ACC
TEMPORARY
CONSTANTS
SYSTEM
0–1
TIMER
P4.0/TM0CK
P4.1/TM1CK
P3.4/TM0IO
SERIAL
P3.5/TM1IO
P3.1/RXD
PORT
P3.0/TXD
TION D.
TRANSI-
P4.4/TRNS0
P4.7/TRNS3
A/D
REF
V
P5.0/AI 0
CONV.
AGND
P5.7/AI 7
0,1
PWM
NMI
P4.2/PWM0
P4.3/PWM1
CONT.
INTERRUPT
P3.2/INT0
P3.3/INT1
WDT
CONT.
PERIPHERAL
RESOUT
P2.3/CLKOUT
3/28
Page 4
¡ Semiconductor MSM66101
PIN CONFIGURATION (TOP VIEW)
AD0/P0.0
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
A15/P1.7
P2.0
P2.1
P2.2
CLKOUT/P2.3
RESOUT P3.6
ALE P3.5/TM1IO
PSEN P3.4/TM0IO
RD P3.3/INT1
WR P3.2/INT0
READY P3.1/RXD
FLT P2.7
RES P2.6
OSC0 P2.5/HLDA
OSC1 P2.4/HOLD
GND NMI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EA P3.0/TXD
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
DD
V
REF
AGND
P5.7/AI7
P5.6/AI6
P5.5/AI5
P5.4/AI4
P5.3/AI3
P5.2/AI2
P5.1/AI1
P5.0/AI0
P4.7/TRNS3
P4.6/TRNS2
P4.5/TRNS1
P4.4/TRNS0
P4.3/PWM1
P4.2/PWM0
P4.1/TM1CK
P4.0/TM0CK
P3.7
64-Pin Plastic Shrink DIP
4/28
Page 5
¡ Semiconductor MSM66101
PIN CONFIGURATION (TOP VIEW) (Continued)
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
A15/P1.7
P2.0
P2.1
P2.2
10
11
12CLKOUT/P2.3
13RESOUT
14ALE
15PSEN
16RD
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
64
63
62
61
60
59
58
1
2
3
4
5
6
7
8
9
DDVREF
P0.0/AD0
V
57
56
55
AGND
54
53 P5.7/AI7
52 P5.6/AI6
54 P5.5/AI5
50 P5.4/AI4
49 P5.3/AI3
48
P5.2/AI2
47
P5.1/AI1
46
P5.0/AI0
45
P4.7/TRNS3
44
P4.6/TRNS2
43
P4.5/TRNS1
42
P4.4/TRNS0
41
P4.3/PWM1
40
P4.2/PWM0
39
P4.1/TM1CK
38
P4.0/TM0CK
37 P3.7/TM3IO
36 P3.6/TM2IO
35 P3.5/TM1IO
34 P3.4/TM0IO
33 P3.3/INT1
17
WR
18
19
EA
READY
20
21
22
23
24
FLT
RES
OSC0
OSC1
GND
64-Pin Plastic QFP
25
26
NMI
HOLD/P2.4
27
28TXC/P2.6
29RXC/P2.7
HLDA/P2.5
30TXD/P3.0
31RXD/P3.1
32INT0/P3.2
5/28
Page 6
¡ Semiconductor MSM66101
PIN CONFIGURATION (TOP VIEW) (Continued)
P5.2/AI2
P5.1/AI1
P5.0/AI0
P4.7/TRNS3
P4.6/TRNS2
P4.5/TRNS1
P4.4/TRNS0
60
59
58
57
56
55
P4.3/PWM1
54
53
P4.1/TM1CK
52
51
P4.0/TM0CKNCP3.7
50
49
48
P3.6
P3.5/TM1IO
47
46
P3.4/TM0IO
P3.3/INT1
45
44
AI3/P5.3
AI4/P5.4
AI5/P5.5
AI6/P5.6
AI7/P5.7
AGND
V
REF
V
DD
V
DD
AD0/P0.0
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
61
62
63
64
65
66
67
68
P3.2/INT0
43
P3.1/RXD
42
P3.0/TXD
41
P2.7
40
P2.6
39
P2.5/HLDA
38
P2.4/HOLD
37
NMI
36
1
2
3
4
5
6
7
8
9
35
34
33
32
31
30
29
28
27
GND
GND
OSC1
OSC0
RES
FLT
EA
READY
WR
10
11
A8/P1.0
A9/P1.1
12
13
14
15
16
17
18
NC P4.2/PWM0
P2.0
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
A15/P1.7
NC: No-connection pin
68-Pin Plastic QFJ (PLCC)
19
20
P2.1
21
22
P2.2
CLKOUT/P2.3
23
24
ALE
RESOUT
25
PSEN
26
RD
6/28
Page 7
¡ Semiconductor MSM66101
PIN DESCRIPTIONS
Type DescriptionSymbol
P0.0–P0.7/
AD0–AD7
I/O
P0: 8-bit input-output port. Each bit can be assigned to input or output.
AD: Outputs the lower 8 bits of program counter during external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also outputs the address and outputs or inputs data during an external data
memory access instruction under the control of ALE, RD, and WR.
P1.0–P1.7/
A8–A15
I/O
P1: 8-bit input-output port. Each bit can be assigned to input or output.
A: Outputs the upper 8 bits of program counter (PC
memory fetch. Also this pin outputs the upper 8 bits of address during external data
memory access instructions.
P2.0–P2.2
P2.3/CLKOUT CLKOUT:
I/O
P2: 8-bit input-output port. Each bit can be assigned to input or output.
Output pin for supplying a clock to peripheral circuits. Output frequency
range is equal to or twice the system clock.
P2.4/HOLD
P2.5/HLDA
HOLD: Input pin to request the CPU to enter the hardware power-down state.
HLDA: HOLD ACKNOWLEDGE: the HLDA signal appears in response to the HOLD
signal and indicates that the CPU has entered the power-down state.
P2.6
P2.7
P3.0/T
P3.1/R
D
X
D
X
I/O
P3.2/INT0 R
P3: 8-bit input-output port. Each bit can be assigned to be an input or an output.
TXD: Serial port transmitter data output pin.
D: Serial port receiver data input pin with high impedance.
X
P3.3/INT1 INT: Interrupt Request Input pin.
P3.4/TM0IO
P3.5/TM1IO
P3.6
P3.7
TM0IO-TM1IO: One of the following signals is output or input.
• Clock at twice the frequency range of the 16-bit timer overflow
• Load trigger signal to the capture register input
• Setting value output
Whether the signal is input or output depends on the mode.
) during external program
8–15
P4.0/TM0CK P4: 8-bit input-output port. Each bit can be assigned to an input or an output.
I/O
P4.1/TM1CK TM0CK, TM1CK: Clock input pins of timer 0, timer 1.
P4.2/PWM0
P4.3/PWM1
P4.4
– P4.7/
TRANS: The input pins which sense the rising edge and set the flag.
PWM: 12-bit pulse-width modulator output pin.
TRANS0 – 3
P5.0 – P5.7/
AI0 –AI7
I
P5: 8-bit input port.
AI: Analog signal input pin for A/D converter.
7/28
Page 8
¡ Semiconductor MSM66101
PIN DESCRIPTIONS (Continued)
Type DescriptionSymbol
RESOUT
O
Outputs 'H' level when the CPU is in RESET status.
Reset to 'L' level in some programs.
ALE
PSEN Program Store Enable:
RD Output strobe activated during a bus read cycle.
WR Output strobe during a bus write cycle.
EA Normally set to 'H' level.
FLT If FLT is 'H' level, ALE, WR, RD, PSEN are set to 'H' level when reset.
RES RESET input pin.
OSC0
OSC1
NMI Nonmaskable interrupt input pin (falling edge)
V
REF
AGND Ground for A/D converter.
V
DD
GND Ground.
O
O
O
O
IREADY Used when the CPU accesses low speed peripherals.
I
I
I
I
O
I
I
I
I
I
Address Latch Enable:
Used to enable data on to the bus from the external data memory.
Used as write strobe to external data memory.
If set to 'L' level, the CPU fetches the code from external program memory.
If FLT is set to 'L', ALE, WR, RD, PSEN are set to floating level when reset.
Clock oscillation pins
Reference voltage input pin for A/D converter.
System power supply.
The timing pulse to latch the lower 8 bits of the address
output from port 0 when the CPU accesses the external
memory.
The strobe pulse to fetch to external program
memory.
8/28
Page 9
¡ Semiconductor MSM66101
REGISTERS
Accumulator
15 0
ACC
Control Register (CR)
15 0
Program Status Word
Program Counter
Local Register Base
System Stack Pointer
Pointing Register (PR)
Index Register 1
Index Register 2
Data Pointer
User Stack Pointer
PSW
PC
LRB
SSP
15 0
X1
X2
DP
USP
Local Register
7070
ER0
ER1
ER2
ER3
R1
R3
R5
R7
R0
R2
R4
R6
9/28
Page 10
¡ Semiconductor MSM66101
SFR
Address
(HEX)
0000
0001
0002
0003
0004I
0005I
0006
0007
0010I
0011
0012I
0013
0018I
0019I
001AI
001BI
001CI
0020
0021
0022
0023
0024
0025
0026I
0028
0029
002AI
002C
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
Name Symbol R/W
System stack pointer
Local register base
Program status word
Accumulator
Standby control register
Watchdog timer
Peripheral control register
Stop code acceptor
Interrupt request register
Interrupt enable register
External Iinterrupt control register
Port 0 data register
Port 0 mode register
Port 1 data register
Port 1 mode register
Port 2 data register
Port 2 mode register
Port 2 secondary function control register
Port 3 data register
Port 3 mode register
Port 3 secondary function control register
Port 4 data register
Port 4 mode register
Port 4 secondary function control register
Port 5
Timer 0 counter
Timer 0 register
Timer 1 counter
Timer 1 register
SSP
(ASSP)
LRB
(ALRB)
PSWL
(APSW)
PSWH
ACC
SBYCON
WDT
PRPHF
STPACP
IRQ
IE
EXICON
P0
P0IO
P1
P1IO
P2
P2IO
P2SF
P3
P3IO
P3SF
P4
P4IO
P4SF
P5
TM0
TMR0
TM1
TMR1
8/16-bit
Operation
R/W
8/16
W
R/W
W
8/16
R/W
R
R/W 16
Reset
FFH
FFH
undefined
C8H
0CH
00H
00H
F8H
00H/WDT
8
is stopped
FDH
"0"
08H
0FH
08H
0FH
FCH
undefined
00H
undefined
00H
undefined
8
00H
C7H
undefined
00H
C0H
undefined
00H
00H
—
00H
00H
00H
00H
00H
00H
00H
00H
I indicates that the register has a nonexistent bit.
10/28
Page 11
¡ Semiconductor MSM66101
SFR (Continued)
Address
(HEX)
0040
0041
0046I
0048
0049
004AI
0050I
0051
0054
0055
0056I
0058I
0060I
0061
0062I
0063
0064I
0065
0066I
0067
0068I
0069
006AI
006B
006CI
006D
006EI
006F
Name R/W
Timer 0 control register
Timer 1 control register
Transition detector register
Serial port transmission baud rate generator counter
Serial port transmission baud rate generator register
Serial port transmission baud rate generator control
register
Serial port transmission mode control register
Serial port transmission data buffer register
Serial port receiving mode control register
Serial port receiving data buffer register
Serial port receiving error register
A/D scan mode register
A/D conversion result register 0
A/D conversion result register 1
A/D conversion result register 2
A/D conversion result register 3
A/D conversion result register 4
A/D conversion result register 5
A/D conversion result register 6
A/D conversion result register 7
Symbol
TCON0
TCON1
TRNSIT
STTM
STTMR
STTMC
STCON
STBUF
SRCON
SRBUF
SRSTAT
ADSCAN
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
R/W
W
R/W
R
R/W
R
8/16-bit
Operation
undefined
8
undefined
undefined
8/16 undefined
Reset
00H
00H
00H
00H
0FH
82H
12H
F0H
80H
I indicates that the register has a nonexistent bit.
11/28
Page 12
¡ Semiconductor MSM66101
SFR (Continued)
Address
(HEX)
0070
0071I
0072
0073I
0074
0075I
0076
0077I
0078I
007AI
PWM 0 counter
PWM 0 register
PWM 1 counter
PWM 1 register
PWM 0 control register
PWM 1 countrol register
Name R/W
I indicates that the register has a nonexistent bit.
Symbol
PWMC0
PWMR0
PWMC1
PWMR1
PWCON0
PWCON1
R/W
8/16-bit
operation
8/16
8
Reset
00H
F0H
00H
F0H
00H
F0H
00H
F0H
0CH
0CH
12/28
Page 13
¡ Semiconductor MSM66101
ADDRESSING MODES
The MSM66101 provides independent 64K-byte data and 64K-byte program spaces with
various types of addressing modes. These modes are shown below, for both RAM (for data
space) and ROM (for program space).
1. RAM Addressing Mode (for data space)
1.1 Register Direct Addressing
1.2 Page Addressing
a) Zero Page
b) Direct Page
Example
Example
Example
ROR
L
ST
A,
DP
18H
A,
off 10H
DP
0000H
SFR
0018H
xx00H
RAM
xx10H
1.3 Pointing Register (PR) Indirect Addressing
a) Data Point (DP) Indirect
Example
SLL
[DP]
DP
b) User Stack Pointer (USP) Indirect
Example
SRL
10H
[USP]
–128 to +127
RAM
RAM
USP
13/28
Page 14
¡ Semiconductor MSM66101
c) Index Register (X1, X2) Indirect
Example
INC 300H
[X1]
RAM
X1
0–65535
1.4 Immediate Addressing
Example
MOV
#27FHSSP,
2. ROM Addressing Mode (for program space)
2.1 Direct Addressing
Example
LC A,
2.2 Simple Indirect Addressing
Example
2.3 Double Indirect Addressing
Example
DP
LC
200H
[DP]
A,
DP
A, [[DP]]LC
RAM
ROM
0200H
ROM
ROM
2.4 Indirect Addressing with 16-bit Offset
Example
CMPC A, [300H [X1]]
0–65535
X1
ROM
14/28
Page 15
¡ Semiconductor MSM66101
MEMORY MAPS
Program Memory Space
0000H
2FFFH
FFFFH
Internal
ROM Area
External
Memory
0000H
0027H
0028H
0037H
0038H
2FFFH
Vector
Table
Area
(40 bytes)
VCAL
Table
Area
(16 bytes)
Data Memory Space
0000H
007FH
Zero
Page
Area
Internal
RAM
Area
External
Memory
Area
0080H
00BFH
00C0H
00FFH
01FFH
FFFFH
0000H
SFR area Special
PR area
007FH
0080H
00BFH
00C0H
Function
Registers
PORT, A/D C,
TIMER, PWM,
etc....
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
80
82
84
86
X1
X2
DP
USP
Low-Order
High-Order
01FFH
15/28
Page 16
¡ Semiconductor MSM66101
ABSOLUTE MAXIMUM RATINGS
(Ta = 25°C)
Parameter
Symbol
Supply Voltage
Input Voltage
Output Voltage
Analog Ref. Voltage V
Analog Input Voltage
Power Dissipation
V
V
V
P
DD
V
REF
AI
I
O
D
per package
Condition
GND = AGND = 0V
64-pin shrink DIP
Ta=85°C
64-pin QFP 565
68-pin QFJ 1120
Rating
–0.3 to 7.0
–0.3 to V
–0.3 to V
DD
DD
+0.3
+0.3
–0.3 to VDD+0.3
–0.3 to V
REF
930
Unit
V
mW
Ta = 85°C per output
Storage Temperature
T
STG
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Memory Hold Voltage
Operating Frequency
Ambient Temperature
Fan Out
Symbol
V
DD
V
DDH
f
OSC
Ta –40 to +85 °C
N
TTL load
Condition Range
f
£ 10MHz
OSC
= 0Hz
f
OSC
V
= 5V ±10%
DD
—
MOS load
P0
P1, P2, P3, P4 1
50
–55 to +150
4.5 to 5.5
2.0 to 5.5
0 to 10
20
2
°C
Unit
V
MHz
—
16/28
Page 17
¡ Semiconductor MSM66101
ELECTRICAL CHARACTERISTICS
DC Characteristics
= 5V ± 10%, Ta = –40 to +85°C)
(V
DD
Parameter Symbol Condition Min. Max. Unit
"H" Input Voltage 1, 3, 6
"H" Input Voltage 5, 7
"H" Input Voltage 8
"H" Input Voltage 2
"L" Input Voltage 1, 2, 3, 6
"L" Input Voltage 8
"H" Output Voltage 1, 4
"H" Output Voltage 2
"L" Output Voltage 1, 4
"L" Output Voltage 2
Input Leakage Current 3, 6, 7
Input Current 8
"H" Output Current 1
"H" Output Current 2
"L" Output Current 1
"L" Output Current 2
Output Leakage Current 1, 2, 4
Input Capacitance
Output Capacitance
Analog Reference Power
Supply Current
Current Consumption
(during STOP) *
V
V
V
V
IIH/I
I
OH
I
I
C
C
I
REF
I
DDS
OH
OL
OL
LO
IH
IL
IL
I
O
—
—
= –400mA
I
O
= –200mA
I
O
= 3.2mA
I
O
= 1.6mA
I
O
= 2.4V
V
O
VO = V
DD
f = 1MHz
Ta = 25°C
/
0V
A/D in operation
A/D stopped
= 2V
V
DD
—
2.4
4.0
4.2
3.6
–0.3
–0.3
–0.3
4.2
4.2
—
—
—
—
—
–2
–1
10
5
—±2mA
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
7
0.3
0.5
0.2
1
VDD+0.3
+0.3
V
DD
+0.3
V
DD
+0.3
V
DD
0.8
0.8
0.4
—
—
0.4
0.4
1/–1
1/–20
10/–10
—
—
—
—
—
—
2
10
10
100
V"L" Input Voltage 5, 7
mAVI = VDD/0VInput Current 5
mA
pF
mA
mA
mA
Current Consumption
(during HALT)
I
DDH
f
OSC
= 10MHz
—10
6
No load
Current Consumption
I
DD
—35
20
1 : Applied to P0
2 : Applied to P1, P2,P3 and P4
3 : Applied to P5
4 : Applied to ALE, PSEN, RD, WR and RESOUT
5 : Applied to RES and NMI
6 : Applied to READY and EA
7 : Applied to FLT
8 : Applied to OSC0
* : VDD or GND for ports serving as the input pin. No-load for any other.
mA
17/28
Page 18
¡ Semiconductor MSM66101
AC Characteristics
• External program memory control
=5V±10%, Ta=–40 to +85°C)
(V
DD
Parameter Symbol Condition Min. Max. Unit
Clock (OSC) Pulse
ALE Pulse Width
PSEN Pulse Width
PSEN Pulse Delay Time
Low Address Setup time
Low Address Hold Time
High Address Delay Time
High Address Hold Time
Instruction Setup Time
Instruction Hold Time
t
t
t
t
PAD
t
AAS
t
AAH
t
AAD
t
APH
fW
AW
PW
t
t
—
C
= 50pF
L
IS
IH
3t
4t
2t
t
t
t
t
fW
fW
fW
fW
fW
fW
fW
50
–20
–20
–20
–35
–20
–20
–20
100
0
2t
t
t
t
t
t
fW
fW
fW
fW
fW
fW
—
—
—
—
+20
+20
+40
+40
+40
–20
ns
• External data memory control
Parameter Symbol Condition Min. Max. Unit
Clock (OSC) Pulse
ALE Pulse Width
RD Pulse Width
WR Pulse Width
RD Pulse Delay Time
WR Pulse Delay Time
Low Address Setup Time
Low Address Hold Time
High Address Setup Time
High Address Hold Time t
High Address Hold Time t
Memory Data Setup Time t
Memory Data Hold Time t
Data Delay Time t
Data Hold Time
t
t
t
t
WW
t
RAD
t
WAD
t
AAS
t
AAH
t
AAD
ARH
AWH
t
fW
AW
RW
MS
MH
DD
DH
C
L
—
= 50pF
=5V±10%, Ta=–40 to +85°C)
(V
DD
50
3t
fW
–20
4t
fW
–20
4t
fW
–20
2t
t
t
t
t
t
t
fW
fW
fW
fW
fW
fW
fW
–20
–20
–35
–20
–20
–20
–20
2t
t
t
t
t
t
t
fW
fW
fW
fW
fW
fW
fW
100
0t
t
fW
–20
t
fW
–20
fW
t
fW
t
fW
—
—
—
—
—
+20
+20
+20
+40
+40
+40
+40
–20
+40
+40
ns
18/28
Page 19
¡ Semiconductor MSM66101
CLK
t
t
∆W
ALE
PSEN
∆W
t
AW
t
PAD
t
PW
AD0–7
AD8–15
RD
AD0–7
AD8–15
t
AAD
PC0–7 INST0–7
t
AAS
t
AAH
PC8–15
t
RAD
t
RW
RAP0–7
t
AAS
t
AAH
RAP8–15
t
IS
DIN0–7
t
MS
t
t
IH
APH
t
MH
WR
AD0–7
AD8–15
t
t
AAD
AAD
t
WAD
t
WW
RAP0–7 DOUT0–7
t
AAS
t
AAH
t
DD
RAP8–15
t
t
t
AWH
APH
DH
19/28
Page 20
¡ Semiconductor MSM66101
• Serial port control
Master mode
(V
=5V±10%, Ta=–40 to +85°C)
DD
Parameter Symbol Condition Min. Max. Unit
Clock (OSC) Pulse Width
Serial Clock Pulse Width
Output Data Setup Time
Output Data Hold Time
Input Data Setup Time
Input Data Hold Time
t
fW
t
SCKW
t
STMXS
t
STMXH
t
SRMXS
t
SRMXH
—50
—
8t
fW
8tfW+40
–20
6t
C
L
=50pF
2t
fW
fW
+10
50
—
—
—
ns
—
—
—
Slave mode
=5V±10%, Ta=–40 to +85°C)
(V
DD
Parameter Symbol Condition Min. Max. Unit
Clock (OSC) Pulse Width
Serial Clock Pulse Width
Output Data Setup Time
Output Data Hold Time
Input Data Setup Time
Input Data Hold Time
t
fW
t
SCKW
t
STSXS
t
STSXH
t
SRSXS
t
SRSXH
—50
—
8t
fW
6tfW+40
–20
6t
C
L
=50pF
fW
100
100
—
—
—
ns
—
—
—
20/28
Page 21
¡ Semiconductor MSM66101
OSC
SCK
SDOUT
(TXD)
SDIN
(RXD)
t
∆W
t
∆W
t
STMXH
t
SCKW
t
STMXS
t
SCKW
Valid Valid
t
SRMXH
t
SRMXS
SCK
SDOUT
(TXD)
SDIN
(RXD)
t
SCKW
t
STSXH
t
SCKW
t
STSXS
Valid Valid
t
SRSXH
t
SRSXS
21/28
Page 22
¡ Semiconductor MSM66101
A/D Converter Characteristics
• Operating range
Parameter Symbol Condition Min. Max. Unit
f
Power Supply Voltage
Analog Reference Voltage
Analog Input Voltage
Analog Reference Power
Voltage Resistance
Operating Temperature
V
DD
V
R
V
AI
R
R
T
op
£ 10MHz 4.5
OSC
V
= GND = 0V
AG
= 5V ± 10%
DD
4.5
V
AG
—
–40
Typ.
—
—
—
16
—V
5.5
V
DD
V
—
+85
R
• A/D Converter accuracy
Normal operation mode
Parameter Symbol Condition
Resolution
Absolute Error
Relative Error
Full Scale Error –1.0 — — –3.5 –3.5
Differential Linearity Error E
Crosstalk
See the
n
recommended
E
A
circuit.
V
E
R
E
Z
E
D
E
C
R=VDD
VAG=GND=0V
Analog input source
impedance
F
£5kW
One channel
conversion time
=64ms
t
C
(VDD=5V±10%, f
Min.
*
—
—
—
—
—
—
—
—
—
=10MHz, Ta=–40 to +85°C)
OSC
Typ. Max.
*
—
—
—
10
+3.0
–3.5
±1.5
0Zero Point Error 0 — — +3.0 +2.0
–0.5
————
—
—
±0.5
±0.5
+3.0 +2.0
——
*
10
+2.0
–3.5
±1.0
V
kW
°C
Unit
Bit
LSB
* V
=5V, Ta=25°C
DD
HALT/HOLD operation mode
(VDD=5V±10%, f
Min.
Parameter Symbol Condition
*
Resolution
Absolute Error
Relative Error
E
E
E
Full Scale Error –1.5 — — –3.5 –2.0
Differential Linearity Error E
Crosstalk
* V
DD
=5V, Ta=25°C
E
See the
n
recommended
A
circuit.
V
R
Z
E
F
D
C
R=VDD
VAG=GND=0V
Analog input source
impedance
£5kW
One channel
conversion time
=64ms
t
C
—
—
—
—
—
—
—
—
—
+0.5Zero Point Error +0.5 — — +2.0 +1.0
–1.0
————
—
—
±0.5
=10MHz, Ta=–40 to +85°C)
OSC
Typ. Max.
*
—
—
—
10
+2.0
–3.5
±1.0
+2.0 +1.0
±0.5
——
*
10
+1.0
–2.0
±0.5
Unit
Bit
LSB
22/28
Page 23
¡ Semiconductor MSM66101
• Recommended circuit
Reference
Voltage
+
47
0.1
µF
R
I
µF
–
+
~
Analog Input
0.1
µF
RI (Analog input source impedance) £ 5kW
• A/D Converter conversion characteristics 1
V
REF
AI0–7
AGND
V
DD
GND
0.1
µF
+5V
+
47
µF
0V
Conversion Code
[HEX]
3FF
000
E
F
MAX
Actual Conversion (center line)
E
Z
MIN
E
Z
MAX
Analog Input
Conversion Characteristics Diagram 1
E
F
MIN
Ideal Conversion (center line)
Actual Conversion width
REF
[V]
V
23/28
Page 24
¡ Semiconductor MSM66101
Absolute error (EA)
The absolute error indicates a difference between actual conversion and ideal conversion,
excluding a quantizing error. The absolute error of the A/D converter gets larger as it
approaches the zero point or full scale. (See to Conversion Characteristics Diagram 1.)
Relative error (ER)
The relative error indicates a deviation from a line which connects the center point of the zero
point conversion width with that of the full scale conversion width, excluding a quantizing
error.
The relative error of this A/D converter is almost due to a differential linearity error.
Zero point error (EZ) and full scale error (EF)
The zero point error and full scale error indicate a difference between actual conversion and
ideal conversion at the zero point and full scale, respectively. (See Conversion Characteristics
Diagram 1.)
• A/D Converter conversion characteristics 2 (Temperature Characteristics)
[HEX]
3FF
Conversion
Code
000
–40°C
E
S
E
S
Eta [V]
Analog Input
Conversion
Characteristics
Diagram 2-1
+25°C
+85°C
[LSB]
+4
+3
E
S
Differential
Linearity
+2
Error
+1
During normal
operation
During HALT
0
–40 +85
Temperature Ta
Conversion
Characteristics
Diagram 2-2
[°C]
Differential linearity error (ED)
The differential linearity error indicates a difference between the actual conversion width
(actual step width) and ideal value (1LSB).
With this A/D converter, a voltage for actual conversion is shifted and the inclination of a
voltage is changed, with changes of temperature (see Conversion Characteristics Diagram
2-1). Specifications described in the foregoing tables are established from Eta shown in
Conversion Characteristics Diagram 2-1. Conversion Characteristics Diagram 2-2 shows
temperature characteristics of differential linearity error of ES.
24/28
Page 25
¡ Semiconductor MSM66101
PACKAGE DIMENSIONS
(Unit : mm)
SDIP64-P-750-1.78
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
8.70 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
25/28
Page 26
¡ Semiconductor MSM66101
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
26/28
Page 27
¡ Semiconductor MSM66101
(Unit : mm)
QFJ68-P-S950-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
4.50 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
27/28
Page 28
¡ Semiconductor MSM66101
(Unit : mm)
ADIP64-C-750-1.78
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
28/28
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