SAE-J1850 Multiplex Communication Protocol Conformity Transmission Controller for
Automotive LAN
GENERAL DESCRIPTION
The MSM6636B is a transmission controller for automotive LAN based on data communication
protocol SAE-J1850. This device can realize a data bus topology bus LAN system with a PWM
bit encoding method (41.6 kbps). In addition to a protocol control circuit, MSM6636B has an
enclosed quartz oscillation circuit, host CPU interface (parallel interface), a transmit/receive
buffer, and a bus receiver circuit that decreases the burden on the host CPU.
FEATURES
• Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued
August 12, 1991)
• Non-destructive collision and priority control using CSMA/CD
• Multi-address setting with physical addressing: 1 type / functional addressing: 15 types
• Address filter function by multi-addressing (broadcasting possible)
• Automatic retransmission function by arbitration loss and non ACK
• Three types of in-frame response support:
q Single-byte response from a single node
w Multi-byte response from a single node (with CRC code)
e Single-byte response from multiple nodes (ID response as ACK)
• Error detection by cyclic redundancy check (CRC)
• Various communication error detections
• Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function
• Host CPU interface is accessed in parallel
• Sleep function
Low current consumption mode by oscillation stop (IDS Max < 50µA)
SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus
• Package:24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6636BGS-K)
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¡ SemiconductorMSM6636B
BLOCK DIAGRAM
CPU
x'tal
Buffer Register
Receive
Register
Address Register
Status Register
Parallel Interface
Transmission Register
Response Register
Clock
Generator
Receive
Buffer
S-P
Converter
CRC
Checker
Generator
Converter
MSM6636B
CRC
P-S
LAN Controller
PWM
Decoder
Receive Controller
Transmission Controller
Degital
Filter
Address
Filter
Bus
Receiver
PWM
Encoder
LAN
Bus
Input
LAN
Bus
Output
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Page 3
¡ SemiconductorMSM6636B
PIN CONFIGURATION (TOP VIEW)
24
23
22
21
20
19
AD3
18
17
16
15
14
13
DD
1
2
3
4
5
6
7
8
9
10
11
12
WRDV
RDAD7
ALEAD6
INTAD5
RESAD4
AV
BO–AD2
BI–AD1
BI+AD0
BO+CS
AGNDOSC0
DGNDOSC1
24-Pin Plastic SOP
PIN DESCRIPTION
PinDescription
Symbol
WR1I
RD2I
ALE3I
INT4O
RES5I
6—
AV
DD
BO–7O
BI–8I
BI+9I
BO+10O
AGND11—
DGND12—
OSC113O
OSC014I
CS15I
AD0-716-23I/O
24—
DV
DD
Type
Data write enable input pin
Data read enable input pin
Address latch input pin
Interrupt output pin
Reset input pin
Analog power supply voltage
LAN—BUS output –
LAN—BUS input –
LAN—BUS input +
LAN—BUS output +
Analog ground pin
Digital ground pin
Crystal (or ceramic resonator) oscillation output
Crystal (or ceramic resonator) oscillaiton input
Chip select input pin
Address input/data input-output pin
Digital power supply voltage
DD
3/13
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¡ SemiconductorMSM6636B
ABSOLUTE MAXIMUM RATINGS
DGND=AGND=0V
Parameter
Power Supply Voltage
Input Voltage
Output VoltageV
Power DissipationP
Storage TemperatureT
Symbol
DVDD, AV
V
I
O
D(SOP)
STG
DD
1
*
*1 24-pin SOP package power dissipation
Power Dissipation Curve
< 24-pin SOP package>
1000
[mW]
780
ConditionRating
—
AVDD=DV
AVDD=DV
DD
DD
–0.3 to +7.0
–0.3 to DVDD+0.3
–0.3 to DVDD+0.3
Ta=25°C780
—–55 to +150
Unit
V
V
V
mW
°C
D(SOP)
500
–40 25125 150
Power dissipation P
Ambient temperature Ta (°C)
4/13
Page 5
¡ SemiconductorMSM6636B
RECOMMENDED OPERATING CONDITIONS
DGND=AGND=0V
Parameter
Power Supply Voltage
Operating Frequency
Symbol
DVDD, AV
f
OSC
DD
ConditionRange
AVDD=DV
DVDD=AVDD=5V±10%
DD
4.5 to 5.5
2 to 16
Ambient TemperatureTa—–40 to +85
Unit
V
MHz
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD=AVDD=5V±10%, DGND=AGND=0V, Ta=–40 to +85°C
Applied pin
ParameterSymbolConditionUnit
"H" Input Voltage
"L" Input Voltage
"H" Input Voltage
"L" Input Voltage
"H" Input Voltage
"L" Input Voltage
Receiver Hysteresis Width
"H" Input Current
"L" Input Current
"H" Input Current
"L" Input Current
"H" Input Current
"L" Input Current
"H" Output Voltage
"L" Output Voltage
"H" Output Voltage
"L" Output Voltage
GND Offset Voltage
Current Consumption 1
=AVDD=5V±10%, Ta=–40 to +85°C, In setting 41.6 kbps
DV
DD
ParameterSymbol
Bit LengthTP1
"1" Dominant WidthTP2
"0" Dominant WidthTP3
"SOF" Dominant WidthTP4
"SOF, BRK" LengthTP5
"BRK" Dominant WidthTP6
"EOD" + Bit LengthTP7
"EOF" + Bit LengthTP8
"EOF + IFS" " + Bit LengthTP994.5696.00—86.00—ms
"0" Passive WidthTP10
mintypmaxminmax
23.6424.0024.3621.0028.00ms
6.907.007.115.0012.00ms
14.8715.0015.2313.0020.00ms
30.5431.0031.4729.0036.00ms
47.2848.0048.7245.0052.00ms
38.4239.0039.5937.0044.00ms
47.2848.0048.7243.0051.00ms
70.9272.00—69.0076.00ms
8.869.009.144.0015.00ms
TransmitReceive
Unit
Note:The sending timing in the above table does not include the delay of the bus drivers.
" 1 "
" 0 "
" SOF "
" EOD "
" EOF "
" IFS "
Dominant
Passive
Dominant
Passive
Dominant
Passive
Dominant
Passive
Dominant
Passive
TP2
TP3
TP1
LAST BIT
LAST BIT
TP10
TP4
TP5
EOD
TP7
EOFIFS
TP8
" BRK "
Dominant
Passive
TP9
TP6
TP5
6/13
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¡ SemiconductorMSM6636B
• CPU parallel interface timing
DVDD=AVDD=5V±10%, Ta=–40 to +85°C
ParameterSymbolMin.Max.Unit
ALE Pulse Widtht
Address Setup Timet
Address Hold Timet
CS Setup Timet
RD Setup Timet
Continuous Read Cycle Timet
RD Output Enable Delay Timet
RD Output Floating Delay Timet
RD Pulse Widtht
RD Hold Time at Readt
WR Setup Time
Continuous Write Cycle Time
t
WR Pulse Width
Data Setup Time
Data Hold Time
CS Hold Time at Write
t
AW
AS
AH
CSS
RDS
RDCY
RD
RDH
RDW
RCSH
t
WRS
WRCY
t
WRW
t
DS
t
DH
WCSH
Measuring
condition
=50pF
C
L
65—
65—
5—
50—
20—
160—
—70
—50
75—
0—
100—
160—
75—
100—
40—
50—
ns
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¡ SemiconductorMSM6636B
Parallel Interface Timing
t
AW
ALE
AD0-7
CS
RD
ALE
AD0-7
t
RDS
t
AS
t
AH
AddressData Output
t
t
CSS
RD
t
RDW
t
RDH
t
RCSH
Read Timing
t
WRS
AddressData Input
t
DS
t
DH
CS
WR
Write Timing
t
WRW
t
WCSH
8/13
Page 9
¡ SemiconductorMSM6636B
Timing When Automatic Address Increment is Used
ALE
AD0-7
CS
RD
ALE
AD0-7
CS
Address
Address
t
RDS
t
WRS
Data Output
t
RD
t
RDCY
t
RDW
Read Timing
Data Input
t
DS
t
WRCY
t
WRW
Data Output
t
Data Output
RDH
Data InputData Input
t
DH
WR
Write Timing
9/13
Page 10
¡ SemiconductorMSM6636B
• Wakeup input signal
DV
=AVDD=5V±10%, Ta=–40 to +85°C
DD
ParameterSymbolMin.Typ.Max.Unit
LAN bus Passive Æ Dominant Change Pulse Width
RXD Terminal Input Pulse Width
Bus Receiver Stable Time *1
t
t
t
WD
WR
RS
7—ms
400—ns
1—ms
—
—
—
*1 The stable time of the bus receiver is from just after wakeup to the restart of message
transmission and reception. However, the clock oscillation source should use an external
clock. (A clock is input even in the sleep status.)
t
WD
t
WD
t
WD
BI+
BI–
RXD
t
WR
Note: The time chart shows the wakeup input signals from each sleep status.
10/13
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¡ SemiconductorMSM6636B
• Fault tolerant function operation conditions
DV
=AVDD=5V±10%, Ta=–40 to +85°C, In setting 41.6 kbps
DD
ParameterSymbolMin.Typ.Max.Unit
LAN bus (+) GND Short Circuit Detection Pulse Width
LAN bus (+) V
Short Circuit Detection Pulse Width
DD
LAN bus (–) GND Short Circuit Detection Pulse Width
LAN bus (–) V
Short Circuit Detection Pulse Width
DD
BUS(+)
BUS(–)
t
PG
BUS(+)
t
PG
t
PV
t
NG
t
NV
5—ms
48—ms
—
—
48—ms—
5—ms
—
t
PV
BUS(–)
t
NV
t
NG
• Reset input pulse width
=AVDD=5V±10%, Ta=–40 to +85°C
DV
DD
ParameterSymbolMin.Typ.Max.Unit
Reset Input Pulse Widtht
RES
0.1—ms
—
RES
t
RES
Note:The oscillation stable time after power ON is determined by the crystal used and the
parasitic capacitance generated by connection.
Make t
greater than or equal to the oscillation stable time.
RES
In the table above, the reset input pulse width indicates the minimum pulse width when
oscillation is stable after power is turned on.
11/13
Page 12
¡ SemiconductorMSM6636B
APPLICATION CIRCUIT
Host CPU and J1850 Line Bus Connection Example
Unit A
MSM6636BHost CPU
DV
DD
AD0-7AD0-7
ALEALEBO (+)
RD
WRWRBI (+)
PXX
INT
CLKOUT
OPEN
RD
CS
INT
OSC0
OSC1
RES
C
DGND
*1
AGNDRES
AV
DD
BI (–)
BO (–)
R
S
R
B
R
R
R
R
ZD
ZD
R
P
R
B
R
S
Unit B
R
.
D
.
.
Bus + Bus –
An optimum system can be constructed by selecting an optimum host CPU and combining it
with the MSM6636B.
*1 Insert a capacitor between the power supply and GND to prevent supply noise.
It is recommended to connect a small-capacitance bypass capacitor and a large-capacitance
filter capacitor serially. The typical capacitors are as follows:
0.01 to 0.22 mF : Ceramic capacitor
10 to 100 mF :Tantalum capacitor
12/13
Page 13
¡ SemiconductorMSM6636B
PACKAGE DIMENSIONS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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