Page 1
E2E1017-27-Y3
¡ Semiconductor
This version: Jan. 1998
Previous version: Nov. 1996
MSM65X227¡ Semiconductor
MSM65X227
8-Bit Microcontroller (with 4K-Byte EEPROM)
GENERAL DESCRIPTION
The MSM65X227 is a high-performance, 8-bit microcontroller that employs OKI original
CPU core, the nX-8/50. The MSM65X227 includes a minimum instruction execution time of
667 ns (@6 MHz) that enables high-speed processing. It has 60K-byte program memory
space, internal 4K bytes of EEPROM (general memory space), 1K-byte data memory (384
bytes for local memory space and 640 bytes for general memory space), a timer, a serial port
and an A/D converter. The MSM65X227, which has no internal program ROM, is provided
with the special time-division data/address bus that can be connected to an extrernal
program ROM.
FEATURES
• Operating range
Operating frequency : 0 to 6MHz
Operating voltage : 4.5 to 5.5V
Operating temperature : – 40 to +85°C
• Memory space : 128K bytes
Program memory space : 60K bytes
Internal EEPROM : 4K bytes
Internal data memory : 1K bytes
• Minimum instruction execution time : 667ns @ 6MHz
• Ample instruction set : 81 basic instructions
8/16-bit operation instructions
Bit manipulation instructions
Complex function instructions
• Ample addressing modes
• Timer : 8-bit auto-reload timer ¥ 2 (one is shared
with the baud rate generator)
Watchdog timer ¥ 1
• Counter : Time base counter ¥ 1
• Serial port : Serial port ¥ 1 (UART/clock synchronous
system)
• A/D converter : 8 bits ¥ 4 channels
• I/O port : 7 ports, 48 bits
Input-output port : 5 ports ¥ 8 bits, 1 port ¥ 4 bits
Input-port : 1 port ¥ 4 bits
• External interrupts : 2
• Interrupt sources : 10
• Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM65X227TS-K)
1/18
Page 2
2/18
MSM65X227¡ Semiconductor
BLOCK DIAGRAM
OSC0
OSC1
RESET
HSTOP*
V
DD
GND
OSC
CONT.
RAM
(640 bytes)
EXT.MEM.
CONT.
INST.
DEC.
T/C
IR
ALU
GMAR
PC
AR
BR PSW SP LMAR
BUS
CONT.
I/O PORT
RAM
(384 bytes)
TBC WDT
8-bit TIMERx2
INTERRUPT CONT.
AD0-7
A8-16
RD
WR
ALE
T1OUT*
T0CK*
GATE*
INT0*
INT1*
P0 P1 P2
* is secondary function of each port.
XT
XT
EEPROM
(4K bytes)
EXWR
WUP TIMER
SIO
TXD*
RXD*
**P5 is a 4-bit input-output port.
***P6 is a 4-bit input only port.
P3 P4 P5** P6***
8-bit A/D C
¥ 4ch
AI0*- AI3*
AGND
VRLVRHAV
DD
CPU CORE
Page 3
PIN CONFIGURATION (TOP VIEW)
NC
P1.4
P1.5
P1.6
P1.7
NC
P0.0
P0.1
P0.2
92
93
94
95
96
97
98
99
100
1
NC
2NC
3P0.3
4P0.4
5P0.5
6P0.6
7P0.7
8XT
9NC
10XT
11GND
12OSC0
13NC
14OSC1
15ALE
16NC
17RD
18WR
19RESET
20EXWR
21AGND
22P6.0
23P6.1
24P6.2
25P6.3
P1.3
91
P1.2
90
P1.1
89
NC
88
P1.0
87
P2.7
86
NC
85
P2.6
84
P2.5
83
P2.4
82
NC
81
P2.3
80
P2.2
79
P2.1
78
P2.0
77
MSM65X227¡ Semiconductor
A16
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
A15
A14
A13
NC
A12
A11
A10
A9
A8
V
DD
P3.7
NC
P3.6
P3.5
NC
P3.4
P3.3
P3.2
P3.1
P3.0
AD7
AD6
AD5
NC
26
V
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
RL
RH
DD
V
AV
P5.0
P5.1
P5.2
P5.3
NC
P4.0
P4.1
P4.2
P4.3
NC
P4.4
NC
P4.5
P4.6
P4.7
AD0
AD1
AD2
NC
AD3
AD4
NC
NC: No-connection Pin
100-Pin Plastic TQFP
3/18
Page 4
PIN DESCRIPTION
Basic Functions
Function Symbol Type Description
MSM65X227¡ Semiconductor
Power Supply
Oscillation
V
DD
GND
AV
DD
AGND Analog ground—
V
RH
V
RL
OSC0 CPU oscillation input pinI
OSC1 CPU oscillation output pinO
XT CPU start-up timer oscillation input pinI
XT CPU start-up timer oscillation output pinO
RESET
EXWR I
—
—
Digital power supply (5V)
Digital ground
Analog power supply (5V)—
Analog reference voltage (5V)—
Analog reference voltage (ground)—
System reset input:
When this pin goes into the "L" state, the internal state is
I
initialized and the execution of an instruction starts from address
0040H. The input is pulled up to V
with an internal pull-up
DD
resistor.
External write enable pin :
Sampled at a system reset and enables external EEPROM write
and read during the "L" level.
Control
RD O
WR O
ALE O
AD0 - AD7 I/O
A8 - A16 O
Read signal at external memory access:
Read cycle in memory is indicated when the signal goes into the
"L" level during external memory access.
Write-signal during external memory access:
Write cycle in memory is indicated when the signal goes into the
"L" level during external memory access.
Address latch signal at external memory access:
The MSM65X227 uses a time dividing address/data bus. This
signal uses the lower 8 bits of the address as a strobe signal to
latch the external latch circuit.
8-bit address/data bus:
Address/data bus performs lower 8-bit address output,
instruction fetch or data read/write along with the ALE, RD and
WR pins.
9-bit address bus:
Address bus for the upper 9 bits.
4/18
Page 5
Basic Functions (Continued)
MSM65X227¡ Semiconductor
Function
Port
Symbol Type Description
8-bit input-output port (Port 0):
P0.0 - P0.7
P1.0 - P1.7
I/O
I/O
I/OP2.0 - P2.7
I/OP3.0 - P3.7
Users can specify input or output at each bit with the port 0
direction register (P0DIR).
8-bit input-output port (Port 1):
Users can specify input or output at each bit with the port 1
direction register (P1DIR).
In the input mode, ports can be set as inputs with a pull-up
resistor at each bit.
A secondary function shown in the next table is assigned at the
P1.7 pin.
8-bit input-output port ( Port 2):
Users can specify input or output at each bit by the port 2
direction register (P2DIR).
Each pin of Port 2 is assigned a secondary function shown in the
next table.
8-bit input-output port (Port 3):
Users can specify input or output at each bit by the port 3
direction register (P3DIR).
A secondary function shown in the next table is assigned at the
P3.0 pin.
8-bit input-output port (Port 4):
I/OP4.0 - P4.7
I/OP5.0 - P5.3
IP6.0 - P6.3
Users can specify input or output at each bit with the port 4
direction register (P4DIR).
4-bit input-output port (Port 5):
Users can specify input or output at each bit with the port 5
direction register (P5DIR).
4-bit input port (Port 6):
Each pin of Port 6 functions as an analog input channel during
A/D conversion.
5/18
Page 6
Secondary Functions
Function Symbol Type Description
Secondary function of P1.7:
External
Interrupt
Control
INT0 I
INT1 I
HSTOP I
Input pin of external interrupt 0. "Receive" is enabled at
rising/falling edges or at the "L" level.
Secondary function of P2.0:
Input pin of external interrupt 1. "Receive" is enabled at
rising/falling edges or at the "L" level. Can also be used as a gate
signal input pin that enables/disables the count of Timer 0.
Secondary function of P3.0:
Hardware stop mode input pin. Changes to hardware stop mode
by setting this pin to the "L" level when the HSTP bit of SBYCON
is 1. In hardware stop mode, the oscillation of OSC is halted to
reduce power consumption.
MSM65X227¡ Semiconductor
Timer 0
Timer 1
Serial Port
A/D Converter
T0CK
T1OUT
RXD
O
I/O
OTXD
I
IAI0 - AI3
Secondary function of P 2.1:
External clock input pin of Timer 0.
Secondary function of P 2.2:
This pin outputs a waveform with a period equal to two times of
overflow of Timer 1.
Secondary function of P 2.3:
As UART: Receive data input pin of asynchronous
communication.
As clock synchronization: Send/receive data input-output pin of
clock synchronous communication.
Secondary function of P 2.4:
As UART: Send data output pin of asynchronous
communication.
As clock synchronization: Synchronized clock output pin of
clock synchronous communication.
Secondary function of P 6.0 to P 6.3:
Functions as an analog input channel at A/D conversion.
6/18
Page 7
MEMORY MAPS
MSM65X227¡ Semiconductor
General Memory Space
Local Memory Space
1FFH
Data Memory
100H
80H
Data Memory
40H
Local Register Set 3
30H
Local Register Set 2
20H
Local Register Set 1
10H
Local Register Set 0
0
SFR
0FFFFH
0F000H
Page 1
Page 0
100H
80H
40H
20H
Bank 0
EEPROM
Program/Data Area
Vector Call Table
Program/Data Area
Interrupt Vector Table
Vector Call Table
0
0FFFFH
Internal
Memory
External
Memory
1000H
27FH
Bank 1
External Data Memory
Unavailable Area
Data Memory
0
External
Memory
Internal
Memory
7/18
Page 8
ABSOLUTE MAXIMUM RATINGS
MSM65X227¡ Semiconductor
Parameter
Supply Voltage
Input Voltage
Output Voltage
Analog Reference Voltage
Analog Input Voltage
Symbol Condition Rating Unit
=AV
V
DD
DD
V
I
V
O
, V
V
RH
RL
V
AI
Ta=25°C –0.3 to VDD+0.3
GND=AGND=0V –0.3 to VDD+0.3
Ta=25°C (per package) 400
T
P
STG
D
Ta=25°C (per output pin) 50
Excluding EEPROM data storage –55 to +150 °C
Maximum Power Dissipation
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Analog Supply Voltage
Analog Reference Voltage
Analog Input Voltage
Memory Hold Voltage
Operating Frequency
Operating Temperature
Symbol Condition Range Unit
f
V
DD
AV
DD
*AV
V
V
V
DDMH
f
OSC
T
RH
AI
op
V
RL
£6MHz
OSC
VDD=AV
=AGND=GND=0V
f
OSC
=4.5V to 5.5V 1 to 6
V
DD
— –40 to +85
=0Hz
DD
–0.3 to 7.0
–0.3 to VDD+0.3 V
–0.3 to VDD+0.3
mW
4.5 to 5.5
4.5 to 5.5
–0.5 to AV
DD
VRL to V
DD
RH
2.0 to 5.5
MHz
°C
V
*VRH should be connected to VRL if A/D converter is not used.
8/18
Page 9
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter Symbol Condition Min. Typ. Max. Unit
"H" Input Voltage 1 *
"H" Input Voltage 2 *
"L" Input Voltage V
"H" Output Voltage V
"L" Output Voltage V
Input Leakage Current 1 *
Input Leakage Current 2 *
"L" Input Current *
"L" Input Current *
Input Capacitance C
Current Consumption at Standby I
Current Consumption during Writing to
EEPROM
Operating Current Consumption I
1
2
3
4
5
6
V
V
I
I
I
I
DDS
I
DDE
IH1
IH2
IL
OH1
OL1
LI1
LI2
IL
IL
I
DD
MSM65X227¡ Semiconductor
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C)
CPUCLK=1MHz 2.4 — —
CPUCLK=1MHz 0.7V
DD
CPUCLK=1MHz — — 0.8
IOH=–200mA 0.75V
DD
IOL=1.6mA — — 0.4
VI=VDD/0V — — ±1
VI=VDD/0V — — ±10
VI=0V –100 –250 –500
VI=0V –40 –100 –200
f=1MHz, Ta=25°C — 5 —
Sleep mode** — 50 100
Sleep mode, no load — 4 10
f
=6MHz, no load
OSC
See Figure 15-1
—2040
——
——
V
mA
pF
mA
mA
*1 Excluding OSC0 and RESET
*2 OSC0 and RESET
*3 EXWR and P6
*4 Excluding EXWR and P6
*5 P1 in pull-up input
*6 RESET
** When the input ports and V
are at 0V and the output ports are unloaded.
REF
9/18
Page 10
AC Characteristics
• External memory control
Parameter Symbol Condition Min. Max. Unit
MSM65X227¡ Semiconductor
(VDD=AVDD=VRH=4.5 to 5.5V, GND=AGND=VRL=0V, Ta=–40 to +85°C)
Clock Cycle t
"L" Clock Pulse Width t
"H" Clock Pulse Width t
ALE Pulse Width t
ALE Pulse Delay Time 1 t
ALE Pulse Delay Time 2 t
RD Pulse Width t
RD Pulse Delay Time t
WR Pulse Width t
WR Pulse Delay Time t
"L" Address Setup Time t
"H" Address Setup Time t
"L" Address Hold Time t
Bus Floating Time t
"H" Address Hold Time t
"H" Address Hold Time t
HAHW
C
CLW
CHW
AW
ALD1
ALD2
RW
RD
WW
WD
LAS
HAS
LAH
LAZ
HAHR
—
CL=100pF
167 —
75 —
75 —
tC+t
tC+t
tC+t
–40 —
CHW
t
–20 —
CLW
t
–20 —
CLW
–40 —
CHW
t
–20 t
CLW
–40 —
CHW
t
–20 t
CLW
CLW
CLW
+40
+40
tC–40 —
tC+t
–40 —
CHW
t
–20 —
CLW
—20
t
–20 —
CLW
t
–20 —
CLW
ns
Read Data Access Time t
Read Data Access Time t
Read Data Hold Time t
Write Data Hold Time t
Write Data Hold Time t
RDAA
RDAR
RDH
WDS
WDH
• CPU control
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C)
Parameter Symbol Condition Min. Max. Unit
RESET Pulse Width
RESET Pulse Width
*1
*2
t
RESW1
t
RESW2
—
—
*1 Except during power-on, sleep, and hardware stop modes
*2 During power-on, sleep, and hardware stop modes
—t
—t
C+tCLW
CHW
–15
+10
0—
tC+t
–40 —
CHW
t
–20 —
CLW
20 — ns
oscillation
stabilization
—
time
—
10/18
Page 11
• Peripheral control 1
Parameter Symbol Condition Unit
OSC Clock Cycle
External Interrupt
EXI
Pulse Width
External Clock Pulse
Width
T0
GATE Pulse Width
t
t
EXIW
t
T0CW
t
T0GW
MSM65X227¡ Semiconductor
= AVDD = 4.5 to 5.5V, GND = AGND = 0V, Ta = –40 to +85˚C)
(V
DD
MIN
1 t
167
4 t
C
4 t
C
T0CLK
*
C
—
—
MAX
—
—
ns
—
—
*t
: Cycle time of timer 0 count clock selected by T0CON.
T0CLK
• Peripheral control 2
Parameter Symbol Condition Min. Max. Unit
OSC
SIO
(Clock
Synchro-
nous
Mode)
Clock Cycle t
Synchronous Clock Cycle
Synchronous Clock "L"
Pulse Width
Synchronous Clock "H"
Pulse Width
Output Data Setup Time t
Output Data Hold Time t
Input Data Setup Time t
Input Data Hold Time t
t
SIC
t
SICLW
t
SICHW
SIOS
SIOH
SIIS
SIIH
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C)
C
167 —
8 t
C
—
4 tC–20 —
—
4 tC–20
—
ns
6 tC–100 —
2 tC–100 —
tC+t
+100 —
CLW
0—
11/18
Page 12
• A/D converter characteristics
(V
= AVDD = VRH = 4.5 to 5.5V, GND = AGND = VRL = 0V, Ta = –40 to +85˚C)
DD
Parameter Symbol Condition Unit
Resolution
Linearity Error
Differential Linearity Error
Zero Scale Error
Full Scale Error
Crosstalk
Conversion Time*
E
E
E
E
E
t
CONV
n
ZS
CT
FS
Min.
—
—
L
D
Refer to the recommended circuit.
Analog input source impedance
RI £ 5kW
—
—
—
Refer to the measuring circuit.
f
= 6MHz
OSC
—
—
Typ. Max.
—
—
—
—
—
26.7
* The conversion time immediately after G0 bit is set to "I" is 24.7µs/CH.
Definition of Terms
MSM65X227¡ Semiconductor
8
—
+1.5
–1.5
±0.5
+1.5
–1.5
±0.5
—
bit
LSB
LSB
LSB
LSB
LSB
ms/CH
Resolution
Recognizable minimum input analog value.
This can be resolved into 2
8
= 256, that is (V
– VRL) ÷ 256
RH
Linearity Error Deviation between ideal conversion characteristics as an 8-bit A/D converter
and actual conversion characteristics. (Not including quantization error.)
Ideal conversion characteristics means a step which divides voltage between
V
and LRL into 256.
RH
Differential Linearity Error Shows the smoothness of conversion characteristics.
1LSB = (V
– VRL) ÷ 256 is ideal for analog input voltage width corresponding
RH
to change per 1 bit of digital output. The differential linearity error is the
deviation between this ideal bit size and a bit size at arbitrary point in
conversion range.
Zero Scale Error Deviation between ideal conversion characteristics of transfer point for digital
outputs "000H" to "001H" and actual conversion characteristics.
Full Scale Error Deviation between ideal conversion characteristics of transfer point for digital
outputs "0FEH" to "0FFH" and actual conversion characteristics.
12/18
Page 13
Recommended circuit
MSM65X227¡ Semiconductor
AV
DD
V
RH
V
DD
+5V
–
R
I
+
Analog Voltage Input
R
Crosstalk measuring circuit
–
+
Analog Voltage Input
5kW
0.1
µF
MSM65X227
AI0-3
GND
V
RL
AGND
0.1
µF
(Analog input source impedance) £ 5kW
I
AI0
AI1
+
0.1µF47
µF
0V
Crosstalk is defined as
the difference of A/D
conversion result
between supplying the
same voltage to AI0 to
AI3 and supplying
voltage shown in this left
diagram.
V
RH
AI3
or AGND
13/18
Page 14
EEPROM Characteristics
Parameter ConditionRating
MSM65X227¡ Semiconductor
Number of rewrites
Data storage time 10 years
10,000 100 bytes
100 3,996 bytes
Storage between –40 and 85°C
Failure rate < 1%
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C)
Parameter Typ. Max.
Write disable time after reset 5 —
Write time 6 8
Symbol Min.
t
INHWR
t
EEWR
—
—
Unit
ms
ms
14/18
Page 15
TIMING DIAGRAM
External Memory Control
MSM65X227¡ Semiconductor
OSC0
ALE
RD
AD0-7
A8-16
t
CHW
t
CLW
t
C
t
AW
t
LAS
ADDRESS L
t
HAS
t
t
LAH
t
RDAA
RD
t
RDAR
t
LAZ
t
RW
INST or
DATA IN
t
ALD1
t
RDH
t
HAHR
ADDRESS H
WR
AD0-7
A8-16
t
WD
t
t
WDS
WW
ADDRESS L DATA OUT
ADDRESS H
t
ALD2
t
WDH
t
HAHW
15/18
Page 16
CPU Control
1) RESET pulse width
RESET
Peripheral control 1
OSC0
t
CLW
MSM65X227¡ Semiconductor
t
RESW1, 2
t
C
1) EXI Pulse width
INT0-1
2) T0
T0CK
GATE
t
EXIW
t
T0CW
t
T0GW
16/18
Page 17
Peripheral control 2
1) SIO
(Clock synchronous mode)
TXD
t
SFCLW
t
SFC
t
SFCHW
MSM65X227¡ Semiconductor
RXD (transmission)
RXD (reception)
t
SFOS
t
SFIS
t
SFOH
t
SFIH
17/18
Page 18
PACKAGE DIMENSIONS
TQFP100-P-1414-0.50-K
Mirror finish
MSM65X227¡ Semiconductor
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
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