Datasheet MSM66Q573-TB, MSM66Q573L-TB, MSM66573-TB, MSM66573L-TB, MSM66P573-TB Datasheet (OKI)

PEDL66573-02

1

Semiconductor

This version: Aug. 1999
Previous version: Jun.1999

MSM66573 Family

Preliminary

16-Bit Microcontroller

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GENERAL DESCRIPTION

The MSM66573 family of highly functional CMOS 16-bit single chip microcontrollers utilize the nX-8/500S,
Oki's proprietary CPU core.

A wide variety of internal multi-functioned timers provide timer functions such as compare out, capture, event
counter, auto reload, and PWM, and can be used for periodic and timed measurements. In addition to the main
clock and clock gear functions, there is a sub clock (32.768 kHz) that is suitable for low power applications. A
three channel serial interface and a high-speed bus interface that has separate address and data buses and does not
require external address latches are provided as interfaces to external devices.

With a 16-bit CPU core that enables high-speed 16-bit arithmetic computations and a variety of bit processing
functions, this general-purpose microcontroller is optimally suited for Digital Audio devices such as a Mini-Disc
and an MP3 player.

The flash ROM version (MSM66Q573L) programmable with a single 2.4 V (minimum) power supply and flash
ROM version (MSM66Q573) programmable with a single 5 V power supply are also included in the family. These
versions are easily adaptable to sudden specification changes and to new product versions.

APPLICATIONS

Digital Audio Control Systems
PC peripheral Control Systems
Office Electronics Control Systems

ORDERING INFORMATION

Order Code or Product Name Package Remark

MSM66573L-TB

Low voltage version
(2.4 to 3.6 V)

MSM66573-TB

5V mask ROM version
(4.5 to 5.5 V)

MSM66Q573L-TB

MSM66573L flash ROM
version

MSM66Q573-TB

MSM66573 flash ROM
version

MSM66P573-TB

100-pin plastic TQFP

(TQFP 100-P-1414-0.50-K)

MSM66573 OTP ROM
version (2.7 to 5.5 V)

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FEATURES

Name MSM66573L MSM66573
Operating temperature –30°C to +70°C
Power supply voltage/

maximum frequency

V

DD

=2.4 to 3.6 V/f=14 MHz VDD=4.5 to 5.5 V/f=30 MHz

143 ns at 14 MHz (2.4 to 3.6 V) 67ns at 30 MHz (4.5 to 5.5 V)

Minimum instruction
execution time

61µs at 32.768 kHz (2.4 to 3.6/4.5 to 5.5 V)

Internal ROM size
(max. external)

64 KB

(1 MB)
Internal RAM size
(max. external)

4 KB

(1 MB)

I/Oports

75 I/O pins

(with programmable pull-up resistors)

8 input-only pins

16-bit free running timer × 1ch

Compare out/capture input × 2ch

16-bit timer (auto reload/timer out) × 1ch

8-bit auto reload timer × 1ch
8-bit auto reload timer × 3ch

(also fumctions as serial communication baud rate generator)

Watchdog timer (also functions as 8-bit auto reload timer)

Watch timer (real-time counter) × 1ch

Timers

8-bit PWM × 4ch

(can also be used as 16-bit PWM × 2ch)

Serial port

UART × 1ch

Synchronous × 1ch

UART/ Synchronous × 1ch

A/D converter

10-bit A/D converter, 8-ch multiplexer × 1ch

External interrupt

Non-maskable × 1ch

Maskable × 6ch

Interrrupt priority 3 levels

Separate address and data busses

Bus release functionOthers

Dual clocks
OTP ROM version MSM66P573 (Max. f = 24 MHz)
Flash ROM version MSM66Q573L MSM66Q573

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SPECIAL FEATURES

1. High-performance CPU

The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical
addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support.

2. A variety of power saving modes

Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single
clock in place of dual clocks is possible. Switching the CPU clock to this clock signal, 1/2 × main clock, or 1/4

×

main clock, then produces operation in a low power consumption mode. The clock gear function allows a 1/2 × or
1/4 × main clock to be selected for the CPU operating clock.
The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the
oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator
running, and the HALT mode that shuts down the CPU but leaves the peripherals running.

3. MSM66Q573L and MSM66Q573 with flash memory programmable with single power supply

In addition to the regular mask ROM version, the family includes these versions with 64KB of flash memory that
can be programmed using a single power supply. For the MSM66Q573L, an internal booster circuit derives the
necessary program voltage from the device's low (2.4 V min) power supply, and the program voltage for the
MSM66Q573 is provided with a single 5 V power supply.

4. Multifunction, high-precision analog-to-digital converter

The family includes a high-precision 10-bit analog-to-digital converter with eight channels and is ideal for such
analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and
controlling battery use in portable equipment. Each channel has its own result register readily accessible from the
software. In addition to single-channel conversions, there is also a scan function offering automatic conversion
from the user's choice of starting channel through to the last channel.

5. Multifunction PWM

The family supports both 8- and 16-bit PWM operation. Choosing between the time-base counter output or
overflow from an 8-bit auto-reload timer as the PWM counter clock source provides a wide number of possibilities
over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that
generates a high-precision output signal with less ripple suitable for digital-to-analog control applications.

6. Programmable pull-up resistors

Building the pull-up resistors into the chip contributes to overall design compactness. Making them
programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These
programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the
oscillator connection pins).

7. High-speed bus interface

The interface to external devices uses separate data and address buses. This arrangement permits rapid bus access
for controlling the system from the microcontroller.

8. Wide support for external interrupts

There are a total of seven interrupt channels for use in communicating with external devices: six for maskable
interrupts and one for non-maskable interrupts.

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BLOCK DIAGRAM

NMI
EXINT0
to
EXINT5

Instruction
Decoder

RAM 4K

TBC

RTC

TM0OUT
TM0EVT

CLKOUT
XTOUT

CPU Core

Port Control

ROM 64K

Bus Port Control

RXD0
TXD0
RXC0

TM3OUT
TM3EVT

RXD1
TXD1
RXC1

TM4OUT

SIOI3
SIOO3
SIOCK3

TM5EVT

16 bit Timer0

Peripheral

SIO0
(UART)

8 bit Timer3/BRG

SIO1
(UART/SYNC)

8 bit Time4/BRG

8 bit PWM0

8 bit PWM1

SIO3
(SYNC)

8 bit Timer5/BRG

8 bit Timer6/WD

T

8 bit Timer9

CAP/CMP

16 bit FRC

10 bit A/D
Converter

Interrupt

PWMOUT0
PWMOUT2
PWMOUT1
PWMOUT3

TM9OUT
TM9EVT

CPCM0
CPCM1

V

REF

AGND
AI0

to

AI7

ALU Control
ACC

P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12

System
Control

EA
PSEN
RD
WR

WAIT

D0
to
D7

A0
to
A19

Memory Control
Pointing Registers
Local Registers

SSP

LRB

PSW

PC

DSR TSR CSR

XT0

XT1

OSC0

OSC1

HOLD
HLDACK

RES

Control
Registers

ALU

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PIN CONFIGURATION (TOP VIEW)

P10-4
P10-5

TM5EVT/P10-7

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3

TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7

V

DD

GND

HLDACK/P9-7

EXINT4/P9-0
EXINT5/P9-1

P9-2

P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3

P6-4

P6-5

P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0

P3-3/WR

P3-2/RD

P3-1/PSEN

P11-7/TM9EVT

P11-6/TM9OUT

P11-3/XTOUT

P11-2/CLKOUT

P11-1/HOLD

P11-0/WAIT

V

DD

OSC1

OSC0

GND

XT1

XT0

V

DD

EA

NMI

RES

P5-7/TM0EVT

P5-6/TM0OUT

P5-5/CPCM1

P5-4/CPCM0

P6-7

P6-6

A16/P2-0

A17/P2-1

A18/P2-2

A19/P2-3

V

DDVREF

AI0/P12-0

AI1/P12-1

AI2/P12-2

AI3/P12-3

AI4/P12-4

AI5/P12-5

AI6/P12-6

AI7/P12-7

AGND

RXD0/P7-0

TXD0/P7-1

GND

RXC0/P7-2

TM3OUT/P7-4

TM3EVT/P7-5

SIOCK3/P10-0

SIOI3/P10-1

SIOO3/P10-2

P10-3

80

85

90

95

100

1

5

10

15

20

25

75

70

65

60

55

50

45

40

35

30

P1-7/A15

100-pin Plastic TQFP

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PIN CONFIGURATION (TOP VIEW) (continued)

P10-4
P10-5

TM5EVT/P10-7

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3

TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7

V

DD

GND

HLDACK/P9-7

EXINT4/P9-0
EXINT5/P9-1

P9-2

P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3

P6-6

P6-4

P6-5

P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0
P3-3/WR
P3-2/RD
P3-1/PSEN

P11-7/TM9EVT

P11-6/TM9OUT

P11-3/XTOUT

P11-2/CLKOUT

P11-1/HOLD

P11-0/WAIT

V

DD

OSC1

OSC0

GND

XT1

XT0

V

DD

EA

NMI

RES

P5-7/TM0EVT

P5-6/TM0OUT

P5-5/CPCM1

P5-4/CPCM0

A18/P2-2

A19/P2-3

VDDV

REF

AI0/P12-0

AI1/P12-1

AI2/P12-2

AI3/P12-3

AI4/P12-4

AI5/P12-5

AI6/P12-6

AI7/P12-7

AGND

RXD0/P7-0

TXD0/P7-1

GND

RXC0/P7-2

TM3OUT/P7-4

TM3EVT/P7-5

SIOCK3/P10-0

SIOI3/P10-1

SIOO3/P10-2

P10-3

85

90

95

100

1

5

10

15

20

25

P6-7

30

80

75

70

65

60

55

50

45

40

35

P1-7/A15

P2-0/A16

P2-1/A17

100-pin Plastic QFP

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PIN DESCRIPTIONS

In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin.

Function

Classification Symbol

Type Primary function Type Secondary function
P0_0/D0
to
P0_7/D7

I/O

8-bit I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit

I/O

External memory access
Data I/O port

P1_0/A8
to
P1_7/A15

I/O

8-bit I/O port
Pull-up resistors can be
specified for each individual bit

O

External memory access
Address output port

P2_0/A16
to
P2_3/A19

I/O

4-bit I/O port
Pull-up resistors can be
specified for each individual bit

O

External memory access
Address output port

P3_1/PSEN

O

External program memory
access
Read strobe output pin

P3_2/RD

O

External memory access
Read strobe output pin

P3_3/WR

I/O

3-bit I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit

O

External memory access
Write strobe output pin

P4_0/A0
to
P4_7/A7

I/O

8-bit I/O port
Pull-up resistors can be
specified for each individual bit

O

External memory access
Address output port

P5_4/CPCM0

I/O

Capture 0 input / Compare
0 output pin

P5_5/CPCM1

I/O

Capture 1 input / Compare
1 output pin

P5_6/TM0OUT

O

Timer 0 timer output pin

P5_7/TM0EVT

I/O

4-bit I/O port
Pull-up resistors can be
specified for each individual bit

I

Timer 0 external event input pin

P6_0/EXINT0 I

External interrupt 0 input pin

P6_1/EXINT1 I

External interrupt 1 input pin

P6_2/EXINT2 I

External interrupt 2 input pin

P6_3/EXINT3

8-bit I/O port
Pull-up resistors can be
specified for each individual bit

I

External interrupt 3 input pin

Port

P6_4 to P6_7

I/O

—

None

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Function

Classification Symbol

Type Primary function Type Secondary function

P7_0/RXD0

I

SIO0 receive data input pin

Port

P7_1/TXD0

I/O

7-bit I/O port
Pull-up resistors can be
specified for each individual bit

O

SIO0 transmit data output pin

P7_2/RXC0

I

SIO0 external clock input pin

P7_4/TM3OUT

O

Timer 3 timer output pin

P7_5/TM3EVT

I

Timer 3 external event input pin

P7_6/PWM0OUT

O

PWM0 output pin

P7_7/PWM1OUT

O

PWM1 output pin

P8_0/RXD1

I

SIO1 receive data input pin

P8_1/TXD1

O

SIO1 transmit data output pin

P8_2/RXC1

I/O

SIO1 receive clock I/O pin

P8_3/TXC1

I/O

SIO1 transmit clock I/O pin

P8_4/TM4OUT

O

Timer 4 timer output pin

P8_6/PWM2OUT

O

PWM2 output pin

P8_7/PWM3OUT

I/O

7-bit I/O port
Pull-up resistors can be
specified for each individual bit

O

PWM3 output pin

P9_0/EXINT4

I

External Interrupt 4 input pin

P9_1/EXINT5

I

External Interrupt 5 input pin

P9_2, P9_3

—

None

P9_7/HLDACK

I/O

5-bit I/O port
Pull-up resistors can be
specified for each individual bit

O

HOLD mode output pin

P10_0/SIOCK3

I/O

SIO3 transmit-receive clock I/O pin

P10_1/SIOCI3

I

SIO3 receive data input pin

P10_2/SIOO3

O

SIO3 transmit data output pin

P10_3 to P10_5

—

None

P10_7/TM5EVT

I/O

7-bit I/O port
Pull-up resistors can be
specified for each individual bit

I

Timer 5 external event input pin

P11_0/WAIT

I

External data memory access
wait input pin

P11_1/HOLD

I

HOLD mode request input pin

P11_2/CLKOUT

O

Main clock pulse output pin

P11_3/XTOUT

O

Sub clock pulse output pin

P11_6/TM9OUT

O

Timer 9 timer output pin

P11_7/TM9EVT

I/O

6-bit I/O port
10 mA sink capability
Pull-up resistors can be
specified for each individual bit

I

Timer 9 external event input pin

P12_0/AI0

to

P12_7/AI7

I

8-bit input port

I

A/D converter analog input port

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Classification Symbol Type Function

V

DD

I Power supply pin

Connect all VDD pins to the power supply.

GND I GND pin

Connect all GND pins to GND.

V

REF

I Analog reference voltage pin

Power
supply

AGND I Analog GND pin

XT0 I Sub clock oscillation input pin

Connect to a crystal oscillator of f = 32.768 kHz.

XT1

O Sub clock oscillation output pin

Connect to a crystal oscillator of f = 32.768 kHz.
The clock output is opposite in phase to XT0.

OSC0 I Main clock oscillation input pin

Connect to a crystal or ceramic oscillator. Or, input an external
clock.

Oscillation

OSC1

O Main clock oscillation output pin

Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.

Reset

RES

I Reset input pin

NMI I Non-maskable interrupt input pinOther

EA

I External program memory access input pin

If the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external
program memory through all address space.

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rated value Unit

Digital power supply voltage

V

DD

–0.3 to +7.0 V

Input voltage V

I

–0.3 to VDD+0.3 V

Output voltage V

O

–0.3 to VDD+0.3 V

Analog reference voltage V

REF

–0.3 to VDD+0.3 V

Analog input voltage V

AI

GND=AGND=0V

Ta=25°C

–0.3 to V

REF

V

100-pin TQFP 650 mW

Power dissipation P

D

Ta=70°C

per package

100-pin QFP 750 mW

Storage temperature T

STG

—

–50 to +150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Rated value Unit

MSM66573

MSM66Q573

f

OSC

≤30 MHz

4.5 to 5.5

MSM66573L

MSM66Q573L

f

OSC

≤14 MHz

2.4 to 3.6

f

OSC

≤24 MHz 4.5 to 5.5

Dogital power supply
voltage

V

DD

MSM66P573

f

OSC

≤12 MHz 2.7 to 3.6

V

Analog reference voltage V

REF

—V

DD

–0.3 to V

DD

V

Analog input voltage V

AI

— AGND to V

REF

V

Memory hold voltage V

DDH

f

OSC

=0Hz 2.0 to 5.5 V

MSM66573

MSM66Q573

V

DD

=4.5 to 5.5 V 2 to 30

MSM66573L

MSM66Q573L

V

DD

=2.4

to

3.6 V 2 to 14

VDD=4.5 to 5.5 V 2 to 24

Operating frequency f

OSC

MSM66P573

V

DD

=2.7

to

3.6 V 2 to 12

MHz

Ambient temperature Ta — –30 to +70 °C

MOS load 20 —

P0, P3, P11 6 —

Fan out N

TTL load

P1, P2, P4, P5,

P6, P7, P8, P9, P10

1—

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ALLOWABLE OUTPUT CURRENT VALUES

MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66573/Q573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)

MSM66P573 (VDD=2.7 to 3.6V/4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Pin Symbol Min. Typ. Max. Unit

“H” output pin (1 pin) All output pins I

OH

——–2

“H” output pins (sum total)

Sum total of all output
pins

∑ I

OH

— — –40

P0, P3, P11

10

“L” output pin (1 pin)

Other ports

I

OL

——

5

Sum total of P0, P3, P11

80

Sum total of P1, P2, P4

Sum total of P5, P6, P9

Sum total of P7, P8, P10

50

“L” output pins (sum total)

Sum total of all output
pins

∑ I

OL

——

140

mA

[Note]
Connect the power supply voltage to all V

DD

pins and the ground voltage to all GND pins.

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ELECTRICAL CHARACTERISTICS

DC Characteristics 1 (VDD=4.5 to 5.5 V)

MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Typ. Max. Unit

“H” input voltage *1

0.44 V

—V

+0.3

“H” input voltage

*2, *3, *4, *5, *6, *7

V

IH

—

0.80 V

—V

+0.3

“L” input voltage *1

–0.3 — 0.16 V

“L” input voltage

*2, *3, *4, *5, *6, *7

V

IL

—

–0.3 — 0.2 V

DD

I

O

=–400 µAV

DD

–0.4 — —

“H” output voltage *1, *4

I

O

=–2.0 mA VDD–0.6 — —

I

O

=–200 µAV

DD

–0.4 — —

“H” output voltage *2

V

OH

IO=–2.0 mA VDD–0.6 — —

IO=3.2 mA — — 0.4

“L” output voltage *1, *4

I

O

=10.0 mA — — 0.8

IO=1.6 mA — — 0.4

“L” output voltage *2

V

OL

IO=5.0 mA — — 0.8

V

Input leakage current*3, *6 — — 1/–1

Input current *5 — — 1/–250

Input current *7

IIH/I

IL

VI=VDD/0 V

— — 15/–15

µA

output leakage current

*1, *2, *4

I

LO

VO=VDD/0 V — — ±10

µA

Pull-up resistance

R

pull

VI= 0 V 25 50 100

kΩ

Input capacitance

C

I

—5—

Output capacitance

C

O

f=1 MHz, Ta=25°C

—7—

pF

During A/D operation — — 4 mA

Analog reference supply
current

I

REF

When A/D is stopped — — 10 µA

*1: Applicable to P0 *5: Applicable to

RES

*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10 *6: Applicable to EA, NMI
*3: Applicable to P12 *7: Applicable to OSC0
*4: Applicable to P3, P11

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Supply current (V

DD

=4.5 to 5.5 V)

• MSM66573
(V

DD

=4.5 to 5.5 V, Ta=–30 to +70°C)

Mode

Symbol Condition Min. Typ. Max. Unit

f=30 MHz, No Load

—3655mA

CPU operation mode I

DD

f=32.768 kHz, No Load

— 60 160

µA

HALT mode I

DDH

f=30 MHz, No Load

—2335mA

XT is used*

— 5 110

OSC is

stopped

XT is not

used*

— 1 100

STOP mode I

DDS

OSC is stopped, XT is not

used

V

DD

=2 V, Ta=25°C*

—0.210

µA

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

• MSM66Q573
(V

DD

=4.5 to 5.5 V, Ta=–30 to +70°C)

Mode

Symbol Condition Min. Typ. Max. Unit

f=30 MHz, No Load

—4270mA

CPU operation mode I

DD

f=32.768 kHz, No Load

— 60 160

µA

HALT mode

I

DDH

f=30 MHz, No Load — 24 40 mA

XT is used*

— 5 110

OSC is

stopped

XT is not

used*

— 1 100

STOP mode I

DDS

OSC is stopped, XT is not

used

V

DD

=2 V, Ta=25°C*

—0.210

µA

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

• MSM66P573
(V

DD

=4.5 to 5.5 V, Ta=–30 to +70°C)

Mode Symbol Condition Min. Typ. Max. Unit

f=24 MHz, No Load

—6080mA

CPU operation mode I

DD

f=32.768 kHz, No Load

— 114 300

µA

HALT mode

I

DDH

f=24 MHz, No Load — 30 40 mA

XT is used*

— 6 120

OSC is

stopped

XT is not

used*

— 1 100

STOP mode I

DDS

OSC is stopped, XT is not

used

V

DD

=2 V, Ta=25°C*

—0.210

µA

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

PEDL66573-02

1

Semiconductor

MSM66573 Family

14/28

DC Characteristics 2 (V

DD

=2.4 to 3.6 V)

MSM66573L/Q573L (V

DD

=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (V

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Typ. Max. Unit

“H” input voltage *1

0.44V

—V

DD

+0.3

“H” input voltage

*2, *3, *4, *5, *6, *7

V

IH

—

0.80V

—V

DD

+0.3

“L” input voltage *1

–0.3 — 0.16 V

“L” input voltage

*2, *3, *4, *5, *6, *7

V

IL

—

–0.3 — 0.2 V

DD

I

O

=–400 µA

V

–0.4 — —

“H” output voltage *1, *4

IO=–2.0 mA

V

–0.8 — —

I

O

=–200 µA

V

–0.4 — —

“H” output voltage *2

V

OH

IO=–1.0 mA

V

–0.8 — —

IO=3.2 mA

——0.5

“L” output voltage *1, *4

I

O

=5.0 mA

——0.9

IO=1.6 mA

——0.5

“L” output voltage *2

V

OL

IO=2.5 mA

——0.9

V

Input leakage current*3, *6

— — 1/–1

Input current *5

— — 1/–250

Input current *7

IIH/I

IL

VI=VDD/0 V

— — 15/–15

µA

output leakage current

*1, *2, *4

I

LO

VO=VDD/0 V — — ±10

µA

Pull-up resistance

R

pull

VI= 0 V 40 100 200

kΩ

Input capacitance

C

I

—5—

Output capacitance

C

O

f=1 MHz, Ta=25°C

—7—

pF

During A/D operation

—— 2mA

Analog reference supply
current

I

REF

When A/D is stopped

—— 5

µA

*1: Applicable to P0 *5: Applicable to

RES

*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10 *6: Applicable to EA, NMI
*3: Applicable to P12 *7: Applicable to OSC0
*4: Applicable to P3, P11

PEDL66573-02

1

Semiconductor

MSM66573 Family

15/28

Supply current (V

DD

=2.4 to 3.6 V)

• MSM66573L
(V

DD

=2.4 to 3.6 V, Ta=–30 to +70°C)

Mode

Symbol Condition Min. Typ. Max. Unit

f=14 MHz, No Load

—1220mA

CPU operation mode I

DD

f=32.768 kHz, No Load

— 30 130

µA

HALT mode

I

DDH

f=14 MHz, No Load — 7 11 mA

XT is used*

— 2 110

OSC is

stopped

XT is not

used*

— 1 100

STOP mode I

DDS

OSC is stopped, XT is not

used

V

DD

=2 V, Ta=25°C*

—0.210

µA

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

• MSM66Q573L
(V

DD

=2.4 to 3.6 V, Ta=–30 to +70°C)

Mode Symbol Condition Min. Typ. Max. Unit

f=14 MHz, No Load

—1322mA

CPU operation mode I

DD

f=32.768 kHz, No Load

— 30 130

µA

HALT mode

I

DDH

f=14 MHz, No Load — 7 11 mA

XT is used*

— 3 110

OSC is

stopped

XT is not

used*

— 1 100

STOP mode I

DDS

OSC is stopped, XT is not

used

V

DD

=2 V, Ta=25°C*

—0.210

µA

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

• MSM66P573
(V

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

Mode Symbol Condition Min. Typ. Max. Unit

f=12 MHz, No Load

—1724mA

CPU operation mode I

DD

f=32.768 kHz, No Load

— 65 160

µA

HALT mode

I

DDH

f=12 MHz, No Load — 8 12 mA

XT is used*

— 3 110

OSC is

stopped

XT is not

used*

— 1 100

STOP mode I

DDS

OSC is stopped, XT is not

used

V

DD

=2 V, Ta=25°C*

—0.210

µA

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

PEDL66573-02

1

Semiconductor

MSM66573 Family

16/28

AC Characteristics 1 (VDD = 4.5 to 5.5 V)

(1) External program memory control

MSM66573/Q573/P573 (V

DD

=4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=30 MHz 33.3 —

Clock pulse width (HIGH level)

t

φ

WH

13 —

Clock pulse width (LOW level)

t

φ

WL

13 —

PSEN pulse width

t

PW

2tφ–15

—

PSEN pulse delay time

t

PD

—45

Address setup time

t

AS

tφ–25

—

Address hold time

t

AH

0—

Instruction setup time

t

IS

25

*1

—

Instruction hold time

t

IH

0—

Read data access time

t

ACC

CL=50 pF

—

3tφ–65

*2

ns

Note: t=t

cyc

/2

*1: MSM66P573=30

*2: MSM66P573=3t–70

t

φ

WH

t

φ

WL

t

cyc

PC0 to 19

t

PW

t

PD

INST0 to 7

t

AS

t

AH

t

ACC

t

IS

t

IH

Bus timing during no wait cycle time

CPUCLK

PSEN

A0 to A19

D0 to D7

PEDL66573-02

1

Semiconductor

MSM66573 Family

17/28

(2) External data memory control

MSM66573/Q573/P573 (V

DD

=4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=30 MHz 33.3 —

Clock pulse width (HIGH level)

t

φ

WH

13 —

Clock pulse width (LOW level)

t

φ

WL

13 —

RD pulse width

t

RW

2tφ–15

—

WR pulse width

t

WW

2tφ–15

—

RD pulse delay time

t

RD

—45

WR pulse delay time

t

WD

—45

Address setup time

t

AS

tφ–25

—

Address hold time

t

AH

tφ–3

—

Read data setup time

t

RS

25

*1

—

Read data hold time

t

RH

0—

Read data access time

t

ACC

—

3tφ–65

*2

Write data setup time

t

WS

2tφ–30

—

Write data hold time

t

WH

CL=50 pF

tφ–3

—

ns

Note: t=t

cyc

/2

*1: MSM66P573=30

*2: MSM66P573=3t–70

t

RH

t

AH

t

φ

WH

t

φ

WL

t

cyc

RAP0 to 19

t

RW

t

RD

DIN0 to 7

t

AS

t

ACC

t

RS

CPUCLK

RD

A0 to A19

D0 to D7

Bus timing during no wait cycle time

t

WH

t

AH

RAP0 to 19

t

WW

t

WD

DOUT0 to 7

t

AS

t

WS

WR

A0 to A19

D0 to D7

PEDL66573-02

1

Semiconductor

MSM66573 Family

18/28

(3) Serial port control

Master mode

MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=30 MHz 33.3 —

Serial clock cycle time

t

SCKC

4t

cyc

—

Output data setup time

t

STMXS

2tφ–5

—

Output data hold time

t

STMXH

5tφ–10

—

Input data setup time

t

SRMXS

13 —

Input data hold time

t

SRMXH

CL=50 pF

0—

ns

Note: tφ=t

cyc

/2

t

cyc

CPUCLK

TXC/

RXC

SDOUT

(TXD)

SDIN

(RXD)

t

STMXS

t

STMXH

t

SCKC

t

SRMXStSRMXH

PEDL66573-02

1

Semiconductor

MSM66573 Family

19/28

Slave mode

MSM66573/Q573/P573 (V

DD

=4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=30 MHz 33.3 —

Serial clock cycle time

t

SCKC

4t

cyc

—

Output data setup time

t

STMXS

2tφ–15

—

Output data hold time

t

STMXH

4tφ–10

—

Input data setup time

t

SRMXS

13 —

Input data hold time

t

SRMXH

CL=50 pF

3—

ns

Note: tφ=t

cyc

/2

TXC/

RXC

SDOUT

(TXD)

SDIN

(RXD)

t

STMXS

t

STMXH

t

SCKC

t

SRMXS

t

SRMXH

t

cyc

CPUCLK

Measurement points for AC timing (except the serial port)

V

DD

0 V

2.0 V

0.8 V

2.0 V

0.8 V

Measurement points for AC timing (the serial port)

V

DD

0V

0.8V

DD

0.2V

DD

0.8V

DD

0.2V

DD

PEDL66573-02

1

Semiconductor

MSM66573 Family

20/28

AC Characteristics 2 (VDD = 2.4 to 3.6 V)

(1) External program memory control

MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=14 MHz 71.4 —

Clock pulse width (HIGH level)

t

φ

WH

28 —

Clock pulse width (LOW level)

t

φ

WL

28 —

PSEN pulse width

t

PW

2tφ–25

*1

—

PSEN pulse delay time

t

PD

—75

Address setup time

t

AS

tφ–40

—

Address hold time

t

AH

-8

*2

—

Instruction setup time

t

IS

60 —

Instruction hold time

t

IH

-8

*2

—

Read data access time

t

ACC

CL=50 pF

—

3tφ–120

ns

Note: t=t

cyc

/2

*1: MSM66P573=2t–20

*2: MSM66P573=0

t

φ

WH

t

φ

WL

t

cyc

PC0 to 19

t

PW

t

PD

INST0 to 7

t

AS

t

AH

t

ACC

t

IS

t

IH

Bus timing during no wait cycle time

CPUCLK

PSEN

A0 to A19

D0 to D7

PEDL66573-02

1

Semiconductor

MSM66573 Family

21/28

(2) External data memory control

MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=14 MHz 71.4 —

Clock pulse width (HIGH level)

t

φ

WH

28 —

Clock pulse width (LOW level)

t

φ

WL

28 —

RD pulse width

t

RW

2tφ–25

*1

—

WR pulse width

t

WW

2tφ–25

*1

—

RD pulse delay time

t

RD

—75

WR pulse delay time

t

WD

—75

Address setup time

t

AS

tφ–40

—

Address hold time

t

AH

tφ–8

*2

—

Read data setup time

t

RS

60 —

Read data hold time

t

RH

0—

Read data access time

t

ACC

—

3tφ–120

Write data setup time

t

WS

2tφ–40

—

Write data hold time

t

WH

CL=50 pF

tφ–6

—

ns

Note: t=t

cyc

/2

*1: MSM66P573=2t–20

*2: MSM66P573=t–6

t

RH

t

AH

t

φ

WH

t

φ

WL

t

cyc

RAP0 to 19

t

RW

t

RD

DIN0 to 7

t

AS

t

ACC

t

RS

CPUCLK

RD

A0 to A19

D0 to D7

Bus timing during no wait cycle time

t

WH

t

AH

RAP0 to 19

t

WW

t

WD

DOUT0 to 7

t

AS

t

WS

WR

A0 to A19

D0 to D7

PEDL66573-02

1

Semiconductor

MSM66573 Family

22/28

(3) Serial port control

Master mode

MSM66573L/Q573L (V

DD

=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (V

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=14 MHz 71.4 —

Serial clock cycle time

t

SCKC

4tcyc —

Output data setup time

t

STMXS

2tφ–10

—

Output data hold time

t

STMXH

5tφ–20

—

Input data setup time

t

SRMXS

21 —

Input data hold time

t

SRMXH

CL=50 pF

0—

ns

Note: t=t

cyc

/2

t

cyc

CPUCLK

TXC/

RXC

SDOUT

(TXD)

SDIN

(RXD)

t

STMXS

t

STMXH

t

SCKC

t

SRMXS

t

SRMXH

PEDL66573-02

1

Semiconductor

MSM66573 Family

23/28

Slave mode

MSM66573L/Q573L (V

DD

=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (V

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Max. Unit

Cycle time

t

cyc

f

OSC

=14 MHz 71.4 —

Serial clock cycle time

t

SCKC

4t

cyc

—

Output data setup time

t

STMXS

2tφ–30

—

Output data hold time

t

STMXH

4tφ–20

—

Input data setup time

t

SRMXS

21 —

Input data hold time

t

SRMXH

CL=50 pF

7—

ns

Note: t=t

cyc

/2

TXC/

RXC

SDOUT

(TXD)

SDIN

(RXD)

t

STMXS

t

STMXH

t

SCKC

t

SRMXS

t

SRMXH

t

cyc

CPUCLK

Measurement points for AC timing of MSM66573L/Q573L

V

DD

0V

0.44V

DD

0.16V

DD

0.44V

DD

0.16V

DD

Measurement points for AC timing of MSM66P573 (except the serial port)

V

DD

0 V

2.0 V

0.8 V

2.0 V

0.8 V

Measurement points for AC timing (the serial port)

V

DD

0V

0.8V

DD

0.2V

DD

0.8V

DD

0.2V

DD

PEDL66573-02

1

Semiconductor

MSM66573 Family

24/28

A/D Converter Characteristics 1 (V

DD

=4.5 to 5.5 V)

MSM6573/Q573/P573 (Ta=–30 to +70°C, V

DD=VREF

=4.5 to 5.5 V, AGND=GND=0 V)

Parameter

Symbol Condition Min. Typ. Max. Unit

Resolution

n—10—Bit

Linearity error

E

L

——±3

Differential Linearity error

E

D

——±2

Zero scale error

E

ZS

——+3

Full-scale error

E

FS

Refer to measurement

circuit 1

Analog input source

impedance

R

I

≤5 kΩ

t

CONV

=10.7 µs

——–3

Cross talk

E

CT

Refer to measurement

circuit 2

——±1

LSB

Conversion time

t

CONV

Set according to ADTM set

data

10.7 — —

µs/ch

A/D Converter Characteristics 2 (VDD=2.4 to 3.6 V)

MSM66573L/Q573L (Ta=–30 to +70°C, VDD=V

REF

=2.4 to 3.6 V, AGND=GND=0 V)

MSM66P573 (Ta=–30 to +70°C, VDD=V

REF

=2.7 to 3.6 V, AGND=GND=0 V)

Parameter Symbol

Condition Min. Typ. Max. Unit

Resolution

n—10—Bit

Linearity error

E

L

——±4

Differential Linearity error

E

D

——±3

Zero scale error

E

ZS

——+4

Full-scale error

E

FS

Refer to measurement

circuit 1

Analog input source

impedance

R

I

≤5 kΩ

t

CONV

=27.4 µs

——–4

Cross talk

E

CT

Refer to measurement

circuit 2

——±2

LSB

Conversion time

t

CONV

Set according to ADTM set

data

27.4 — — s/ch

V

REF

Reference

voltage

V

DD

GND

–

+

Analog input

R

I

AI0 to AI7

C

I

0.1µF47

µF

+

0.1µF47

µF

+

+5 V

0 VAGND

R

I

(impedance of analog input source) ≤5 kΩ

C

I

≅ 0.1 µF

Measurement Circuit 1

PEDL66573-02

1

Semiconductor

MSM66573 Family

25/28

–

+

Analog input

5 k

Ω

0.1 µF

AI0

AI1

AI7

Cross talk is the difference
between the A/D conversion
results when the same
analog input is applied to
AI0 through AI7 and the A/D
conversion results of the
circuit to the left.

to

V

REF

or AGND

Measurement Circuit 2

Definition of Terminology

1. Resolution

Resolution is the value of minimum discernible analog input.
With 10 bits, since 2

10

= 1024, resolution of (V

REF

– AGND) ÷ 1024 is possible.

2. Linearity error

Linearity error is the difference between ideal conversion characteristics and actual conversion c
haracteristics of a 10-bit A/D converter (not including quantization error).
Ideal conversion characteristics can be obtained by dividing the voltage between V

REF

and AGND into 1024

equal steps.

3. Differential linearity error

Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog
input voltage that corresponds to 1 converted bit of digital output is 1LSB = (V

REF

– AGND) ÷ 1024.
Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion
range.

4. Zero scale error
Zero scale error is the difference between ideal conversion characteristics and actual conversion
characteristics at the point where the digital output changes from 000H to 001H.

5. Full-scale error
Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics
at the point where the digital output changes from 3FEH to 3FFH.

PEDL66573-02

1

Semiconductor

MSM66573 Family

26/28

PACKAGE DIMENSIONS

(Unit: mm)

TQFP100-P-1414-0.50-K

Package material
Lead frame material
Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin
42 alloy
Solder plating
5

m or more

0.55 TYP.

Mirror finish

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

PEDL66573-02

1

Semiconductor

MSM66573 Family

27/28

(Unit: mm)

QFP100-P-1420-0.65-BK

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5

m or more

1.29 TYP.

Mirror finish

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

PEDL66573-02

1

Semiconductor

MSM66573 Family

28/28

NOTICE

1. The information contained herein can change without notice owing to product and/or technical

improvements. Before using the product, please make sure that the information being referred to is
up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as

an explanation for the standard action and performance of the product. When planning to use the
product, please ensure that the external conditions are reflected in the actual circuit, assembly, and
program designs.

3. When designing your product, please use our product below the specified maximum ratings and

within the specified operating ranges including, but not limited to, operating voltage, power
dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or
accident, improper handling, or unusual physical or electrical stress including, but not limited to,
exposure to parameters beyond the specified maximum ratings or operation outside the specified
operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc.

is granted by us in connection with the use of the product and/or the information and drawings
contained herein. No responsibility is assumed by us for any infringement of a third party’s right
which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for

commercial applications (e.g., office automation, communication equipment, measurement
equipment, consumer electronics, etc.). These products are not authorized for use in any system or
application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to

particular countries. The purchaser assumes the responsibility of determining the legality of export
of these products and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior

permission.

Copyright 1999 Oki Electric Industry Co., Ltd.