Datasheet MSM66573 Datasheet (OKI)

查询MSM66P573供应商

PEDL66573-02

1

Semiconductor

MSM66573 Family

16-Bit Microcontroller

Preliminary

This version: Aug. 1999
Previous version: Jun.1999

GENERAL DESCRIPTION

The MSM66573 family of highly functional CMOS 16-bit single chip microcontrollers utilize the nX-8/500S,
Oki's proprietary CPU core.

A wide variety of internal multi-functioned timers provide timer functions such as compare out, capture, event
counter, auto reload, and PWM, and can be used for periodic and timed measurements. In addition to the main
clock and clock gear functions, there is a sub clock (32.768 kHz) that is suitable for low power applications. A
three channel serial interface and a high-speed bus interface that has separate address and data buses and does not
require external address latches are provided as interfaces to external devices.

With a 16-bit CPU core that enables high-speed 16-bit arithmetic computations and a variety of bit processing
functions, this general-purpose microcontroller is optimally suited for Digital Audio devices such as a Mini-Disc
and an MP3 player.

The flash ROM version (MSM66Q573L) programmable with a single 2.4 V (minimum) power supply and flash
ROM version (MSM66Q573) programmable with a single 5 V power supply are also included in the family. These
versions are easily adaptable to sudden specification changes and to new product versions.

APPLICATIONS

Digital Audio Control Systems
PC peripheral Control Systems
Office Electronics Control Systems

ORDERING INFORMATION

Order Code or Product Name Package Remark

MSM66573L-TB

MSM66573-TB

MSM66Q573L-TB

MSM66Q573-TB

MSM66P573-TB

100-pin plastic TQFP

(TQFP 100-P-1414-0.50-K)

Low voltage version
(2.4 to 3.6 V)
5V mask ROM version
(4.5 to 5.5 V)
MSM66573L flash ROM
version
MSM66573 flash ROM
version
MSM66573 OTP ROM
version (2.7 to 5.5 V)

1/28

1

Semiconductor

MSM66573 Family

FEATURES

Name MSM66573L MSM66573
Operating temperature –30°C to +70°C
Power supply voltage/

maximum frequency
Minimum instruction

execution time
Internal ROM size

(max. external)
Internal RAM size
(max. external)

I/Oports

Timers

Serial port

A/D converter

External interrupt

Interrrupt priority 3 levels

OTP ROM version MSM66P573 (Max. f = 24 MHz)
Flash ROM version MSM66Q573L MSM66Q573

=2.4 to 3.6 V/f=14 MHz VDD=4.5 to 5.5 V/f=30 MHz

V

DD

143 ns at 14 MHz (2.4 to 3.6 V) 67ns at 30 MHz (4.5 to 5.5 V)

61µs at 32.768 kHz (2.4 to 3.6/4.5 to 5.5 V)

64 KB

(1 MB)

4 KB

(1 MB)

75 I/O pins

(with programmable pull-up resistors)

8 input-only pins

16-bit free running timer × 1ch

Compare out/capture input × 2ch

16-bit timer (auto reload/timer out) × 1ch

8-bit auto reload timer × 1ch
8-bit auto reload timer × 3ch

(also fumctions as serial communication baud rate generator)

Watchdog timer (also functions as 8-bit auto reload timer)

Watch timer (real-time counter) × 1ch

8-bit PWM × 4ch

(can also be used as 16-bit PWM × 2ch)

UART × 1ch

Synchronous × 1ch

UART/ Synchronous × 1ch

10-bit A/D converter, 8-ch multiplexer × 1ch

Non-maskable × 1ch

Maskable × 6ch

Separate address and data busses

Bus release functionOthers

Dual clocks

PEDL66573-02

2/28

PEDL66573-02

1

Semiconductor

MSM66573 Family

SPECIAL FEATURES

1. High-performance CPU

The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical
addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support.

2. A variety of power saving modes

Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single
clock in place of dual clocks is possible. Switching the CPU clock to this clock signal, 1/2 × main clock, or 1/4
main clock, then produces operation in a low power consumption mode. The clock gear function allows a 1/2 × or
1/4 × main clock to be selected for the CPU operating clock.
The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the
oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator
running, and the HALT mode that shuts down the CPU but leaves the peripherals running.

3. MSM66Q573L and MSM66Q573 with flash memory programmable with single power supply

In addition to the regular mask ROM version, the family includes these versions with 64KB of flash memory that
can be programmed using a single power supply. For the MSM66Q573L, an internal booster circuit derives the
necessary program voltage from the device's low (2.4 V min) power supply, and the program voltage for the
MSM66Q573 is provided with a single 5 V power supply.

×

4. Multifunction, high-precision analog-to-digital converter

The family includes a high-precision 10-bit analog-to-digital converter with eight channels and is ideal for such
analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and
controlling battery use in portable equipment. Each channel has its own result register readily accessible from the
software. In addition to single-channel conversions, there is also a scan function offering automatic conversion
from the user's choice of starting channel through to the last channel.

5. Multifunction PWM

The family supports both 8- and 16-bit PWM operation. Choosing between the time-base counter output or
overflow from an 8-bit auto-reload timer as the PWM counter clock source provides a wide number of possibilities
over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that
generates a high-precision output signal with less ripple suitable for digital-to-analog control applications.

6. Programmable pull-up resistors

Building the pull-up resistors into the chip contributes to overall design compactness. Making them
programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These
programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the
oscillator connection pins).

7. High-speed bus interface

The interface to external devices uses separate data and address buses. This arrangement permits rapid bus access
for controlling the system from the microcontroller.

8. Wide support for external interrupts

There are a total of seven interrupt channels for use in communicating with external devices: six for maskable
interrupts and one for non-maskable interrupts.

3/28

1

T

Semiconductor

BLOCK DIAGRAM

PEDL66573-02

MSM66573 Family

TM0OUT
TM0EVT

CLKOUT
XTOUT

RXD0
TXD0
RXC0

TM3OUT
TM3EVT

RXD1
TXD1
RXC1

TM4OUT

SIOI3
SIOO3
SIOCK3

TM5EVT

PWMOUT0
PWMOUT2
PWMOUT1
PWMOUT3

TM9OUT
TM9EVT

CPCM0
CPCM1

V

REF

AGND

to

AI0

AI7

NMI
EXINT0
to
EXINT5

16 bit Timer0

Peripheral

SIO0
(UART)

8 bit Timer3/BRG

SIO1
(UART/SYNC)

8 bit Time4/BRG

SIO3
(SYNC)

8 bit Timer5/BRG

8 bit Timer6/WD

8 bit PWM0

8 bit PWM1

8 bit Timer9

CAP/CMP

16 bit FRC

10 bit A/D
Converter

Interrupt

CPU Core

ALU

ALU Control
ACC

Memory Control
Pointing Registers
Local Registers

RAM 4K

TBC

RTC

Control
Registers

SSP

LRB

DSR TSR CSR

ROM 64K

System
Control

PSW

PC

Instruction
Decoder

XT0

XT1

OSC0

OSC1

HOLD
HLDACK

RES

EA
PSEN
RD
WR

WAIT

D0

Bus Port Control

to
D7

A0
to
A19

P0
P1
P2
P3
P4
P5
P6
P7

Port Control

P8
P9
P10
P11
P12

4/28

1

Semiconductor

PIN CONFIGURATION (TOP VIEW)

PEDL66573-02

MSM66573 Family

P10-4
P10-5

TM5EVT/P10-7

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3

TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7

V

DD

GND

HLDACK/P9-7

EXINT4/P9-0
EXINT5/P9-1

P9-2

P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3

P6-4

P6-5

10

15

20

25

1

5

SIOI3/P10-1

SIOO3/P10-2

P10-3

100

GND

RXC0/P7-2

TM3OUT/P7-4

TM3EVT/P7-5

SIOCK3/P10-0

95

30

AI7/P12-7

AGND

RXD0/P7-0

TXD0/P7-1

90

35

AI4/P12-4

AI5/P12-5

AI6/P12-6

40

AI1/P12-1

AI2/P12-2

AI3/P12-3

85

DDVREF

V

AI0/P12-0

80

45

A17/P2-1

A18/P2-2

A19/P2-3

A16/P2-0

75

70

65

60

55

50

P1-7/A15
P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0

P6-6

P6-7

P5-5/CPCM1

P5-4/CPCM0

P5-7/TM0EVT

P5-6/TM0OUT

RES

NMI

XT0

XT1

GND

OSC1

OSC0

DD

EA

V

100-pin Plastic TQFP

DD

V

P11-0/WAIT

P11-1/HOLD

P3-1/PSEN

P11-3/XTOUT

P11-2/CLKOUT

P11-7/TM9EVT

P11-6/TM9OUT

P3-2/RD

P3-3/WR

5/28

1

Semiconductor

PIN CONFIGURATION (TOP VIEW) (continued)

PEDL66573-02

MSM66573 Family

SIOI3/P10-1

SIOO3/P10-2

P10-3
P10-4
P10-5

TM5EVT/P10-7

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3

TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7

V

DD

GND

HLDACK/P9-7

EXINT4/P9-0
EXINT5/P9-1

P9-2

P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3

P6-4

P6-5

P6-6

P6-7

SIOCK3/P10-0

100

1

5

10

15

20

25

30

TXD0/P7-1

GND

RXC0/P7-2

TM3OUT/P7-4

TM3EVT/P7-5

95

35

AI6/P12-6

AI7/P12-7

AGND

RXD0/P7-0

40

AI3/P12-3

AI4/P12-4

AI5/P12-5

90

AI0/P12-0

AI1/P12-1

AI2/P12-2

85

45

REF

A19/P2-3

VDDV

A18/P2-2

80

75

70

65

60

55

50

P2-1/A17
P2-0/A16
P1-7/A15
P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0
P3-3/WR
P3-2/RD
P3-1/PSEN

P5-5/CPCM1

P5-4/CPCM0

P5-7/TM0EVT

P5-6/TM0OUT

RES

NMI

XT0

XT1

GND

DD

EA

V

100-pin Plastic QFP

OSC1

OSC0

DD

V

P11-0/WAIT

P11-1/HOLD

P11-3/XTOUT

P11-2/CLKOUT

P11-7/TM9EVT

P11-6/TM9OUT

6/28

PEDL66573-02

1

Semiconductor

MSM66573 Family

PIN DESCRIPTIONS

In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin.

Classification Symbol

Port

P0_0/D0
to
P0_7/D7

P1_0/A8
to
P1_7/A15
P2_0/A16
to
P2_3/A19

P3_1/PSEN

P3_2/RD

P3_3/WR

P4_0/A0
to
P4_7/A7

P5_4/CPCM0

P5_5/CPCM1

P5_6/TM0OUT

P5_7/TM0EVT

P6_0/EXINT0 I

P6_1/EXINT1 I

Function

Type Primary function Type Secondary function

8-bit I/O port

I/O

10 mA sink capability
Pull-up resistors can be
specified for each individual bit

8-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

4-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

3-bit I/O port

I/O

10 mA sink capability
Pull-up resistors can be
specified for each individual bit

8-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

4-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

8-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

External memory access

I/O

Data I/O port

External memory access

O

Address output port

External memory access

O

Address output port

External program memory

O

access
Read strobe output pin
External memory access

O

Read strobe output pin
External memory access

O

Write strobe output pin
External memory access

O

Address output port

Capture 0 input / Compare

I/O

0 output pin
Capture 1 input / Compare

I/O

1 output pin

Timer 0 timer output pin

O

Timer 0 external event input pin

I

External interrupt 0 input pin

External interrupt 1 input pin

P6_2/EXINT2 I

P6_3/EXINT3

P6_4 to P6_7

External interrupt 2 input pin

External interrupt 3 input pin

I

None

—

7/28

1

Semiconductor

PEDL66573-02

MSM66573 Family

Classification Symbol

Port

P7_0/RXD0

P7_1/TXD0

P7_2/RXC0

P7_4/TM3OUT

P7_5/TM3EVT

P7_6/PWM0OUT

P7_7/PWM1OUT

P8_0/RXD1

P8_1/TXD1

P8_2/RXC1

P8_3/TXC1

P8_4/TM4OUT

P8_6/PWM2OUT

P8_7/PWM3OUT

P9_0/EXINT4

P9_1/EXINT5

P9_2, P9_3

P9_7/HLDACK

P10_0/SIOCK3

P10_1/SIOCI3

P10_2/SIOO3

P10_3 to P10_5

P10_7/TM5EVT

P11_0/WAIT

P11_1/HOLD

P11_2/CLKOUT

P11_3/XTOUT

P11_6/TM9OUT

P11_7/TM9EVT

P12_0/AI0

to

P12_7/AI7

Function

Type Primary function Type Secondary function

7-bit I/O port
Pull-up resistors can be

I/O

specified for each individual bit

7-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

5-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

7-bit I/O port

I/O

Pull-up resistors can be
specified for each individual bit

6-bit I/O port

I/O

10 mA sink capability
Pull-up resistors can be
specified for each individual bit

8-bit input port

I

I

SIO0 receive data input pin

O

SIO0 transmit data output pin

I

SIO0 external clock input pin

O

Timer 3 timer output pin

I

Timer 3 external event input pin

O

PWM0 output pin

O

PWM1 output pin

I

SIO1 receive data input pin

O

SIO1 transmit data output pin

I/O

SIO1 receive clock I/O pin

I/O

SIO1 transmit clock I/O pin

O

Timer 4 timer output pin

O

PWM2 output pin

O

PWM3 output pin

I

External Interrupt 4 input pin

I

External Interrupt 5 input pin

—

None

O

HOLD mode output pin

I/O

SIO3 transmit-receive clock I/O pin

I

SIO3 receive data input pin

O

SIO3 transmit data output pin

—

None

I

Timer 5 external event input pin
External data memory access

I

wait input pin

I

HOLD mode request input pin

O

Main clock pulse output pin

O

Sub clock pulse output pin

O

Timer 9 timer output pin

I

Timer 9 external event input pin

A/D converter analog input port

I

8/28

1

Semiconductor

Classification Symbol Type Function
Power
supply

V

DD

I Power supply pin

Connect all VDD pins to the power supply.

GND I GND pin

Connect all GND pins to GND.

V

REF

I Analog reference voltage pin

AGND I Analog GND pin

Oscillation

XT0 I Sub clock oscillation input pin

Connect to a crystal oscillator of f = 32.768 kHz.

XT1

O Sub clock oscillation output pin

Connect to a crystal oscillator of f = 32.768 kHz.
The clock output is opposite in phase to XT0.

OSC0 I Main clock oscillation input pin

Connect to a crystal or ceramic oscillator. Or, input an external
clock.

OSC1

O Main clock oscillation output pin

Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.

Reset

RES

I Reset input pin

NMI I Non-maskable interrupt input pinOther

EA

I External program memory access input pin

If the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external
program memory through all address space.

PEDL66573-02

MSM66573 Family

9/28

PEDL66573-02

1

Semiconductor

MSM66573 Family

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rated value Unit

Digital power supply voltage

Input voltage V

Output voltage V

Analog reference voltage V

Analog input voltage V

Power dissipation P

Storage temperature T

V

DD

REF

AI

D

STG

I

O

per package

GND=AGND=0V

Ta=70°C

Ta=25°C

100-pin TQFP 650 mW

100-pin QFP 750 mW

—

–0.3 to +7.0 V

–0.3 to VDD+0.3 V

–0.3 to VDD+0.3 V

–0.3 to VDD+0.3 V

–0.3 to V

REF

–50 to +150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Rated value Unit

Dogital power supply

voltage

Analog reference voltage V

Analog input voltage V

Memory hold voltage V

Operating frequency f

V

REF

DDH

OSC

MSM66573

MSM66Q573

MSM66573L

DD

MSM66Q573L

MSM66P573

AI

f

OSC

MSM66573

MSM66Q573

MSM66573L

MSM66Q573L

MSM66P573

f

≤30 MHz

OSC

f

≤14 MHz

OSC

f

≤24 MHz 4.5 to 5.5

OSC

f

≤12 MHz 2.7 to 3.6

OSC

—V

— AGND to V

=0Hz 2.0 to 5.5 V

=4.5 to 5.5 V 2 to 30

V

DD

to

=2.4

V

DD

3.6 V 2 to 14

VDD=4.5 to 5.5 V 2 to 24

to

=2.7

V

DD

3.6 V 2 to 12

Ambient temperature Ta — –30 to +70 °C

MOS load 20 —

Fan out N

TTL load

P0, P3, P11 6 —

P1, P2, P4, P5,

P6, P7, P8, P9, P10

4.5 to 5.5

2.4 to 3.6

–0.3 to V

DD

DD

REF

1—

V

V

V

V

MHz

10/28

1

Semiconductor

ALLOWABLE OUTPUT CURRENT VALUES

MSM66P573 (VDD=2.7 to 3.6V/4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Pin Symbol Min. Typ. Max. Unit

“H” output pin (1 pin) All output pins I

“H” output pins (sum total)

“L” output pin (1 pin)

“L” output pins (sum total)

Sum total of all output
pins

P0, P3, P11

Other ports

Sum total of P0, P3, P11

Sum total of P1, P2, P4

Sum total of P5, P6, P9

Sum total of P7, P8, P10
Sum total of all output

pins

PEDL66573-02

MSM66573 Family

MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66573/Q573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)

——–2

— — –40

——

——

10

80

50

5

mA

140

∑ I

∑ I

OH

OH

I

OL

OL

[Note]
Connect the power supply voltage to all V

pins and the ground voltage to all GND pins.

DD

11/28

1

Semiconductor

MSM66573 Family

ELECTRICAL CHARACTERISTICS

DC Characteristics 1 (VDD=4.5 to 5.5 V)

MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)

Parameter Symbol Condition Min. Typ. Max. Unit

“H” input voltage *1
“H” input voltage

*2, *3, *4, *5, *6, *7

“L” input voltage *1
“L” input voltage

*2, *3, *4, *5, *6, *7

“H” output voltage *1, *4

“H” output voltage *2

V

IH

V

IL

V

OH

—

—

I

=–400 µAV

O

=–2.0 mA VDD–0.6 — —

I

O

I

=–200 µAV

O

0.44 V

0.80 V

–0.3 — 0.16 V

–0.3 — 0.2 V

–0.4 — —

DD

–0.4 — —

DD

IO=–2.0 mA VDD–0.6 — —

“L” output voltage *1, *4

“L” output voltage *2

V

OL

IO=3.2 mA — — 0.4

=10.0 mA — — 0.8

I

O

IO=1.6 mA — — 0.4

IO=5.0 mA — — 0.8

Input leakage current*3, *6 — — 1/–1

Input current *5 — — 1/–250

Input current *7
output leakage current

*1, *2, *4

Pull-up resistance

Input capacitance

Output capacitance

Analog reference supply
current

IIH/I

I

R

C

I

REF

IL

VI=VDD/0 V

— — 15/–15

LO

pull

C

I

O

VO=VDD/0 V — — ±10

VI= 0 V 25 50 100

f=1 MHz, Ta=25°C

—5—

—7—

During A/D operation — — 4 mA

When A/D is stopped — — 10 µA

—V

—V

PEDL66573-02

+0.3

+0.3

DD

V

µA

µA

kΩ

pF

*1: Applicable to P0 *5: Applicable to

RES

*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10 *6: Applicable to EA, NMI
*3: Applicable to P12 *7: Applicable to OSC0
*4: Applicable to P3, P11

12/28

1

Semiconductor

PEDL66573-02

MSM66573 Family

Supply current (V

=4.5 to 5.5 V)

DD

• MSM66573

Mode

CPU operation mode I

HALT mode I

STOP mode I

• MSM66Q573

Mode

CPU operation mode I

HALT mode

STOP mode I

=4.5 to 5.5 V, Ta=–30 to +70°C)

(V

DD

Symbol Condition Min. Typ. Max. Unit

DD

DDH

DDS

f=30 MHz, No Load

f=32.768 kHz, No Load

f=30 MHz, No Load

OSC is

stopped

XT is used*

XT is not

used*

OSC is stopped, XT is not

used

=2 V, Ta=25°C*

V

DD

—3655mA

— 60 160

µA

—2335mA

— 5 110

— 1 100

µA

—0.210

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

(V

=4.5 to 5.5 V, Ta=–30 to +70°C)

DD

Symbol Condition Min. Typ. Max. Unit

—4270mA

— 60 160

µA

— 5 110

— 1 100

µA

—0.210

I

DDH

DDS

DD

f=32.768 kHz, No Load

f=30 MHz, No Load — 24 40 mA

OSC is

stopped

OSC is stopped, XT is not

=2 V, Ta=25°C*

V

DD

f=30 MHz, No Load

XT is used*

XT is not

used*

used

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

• MSM66P573

Mode Symbol Condition Min. Typ. Max. Unit

CPU operation mode I

HALT mode

STOP mode I

(V

=4.5 to 5.5 V, Ta=–30 to +70°C)

DD

—6080mA

— 114 300

— 6 120

— 1 100

—0.210

I

DDH

DDS

DD

f=32.768 kHz, No Load

f=24 MHz, No Load — 30 40 mA

OSC is

stopped

OSC is stopped, XT is not

=2 V, Ta=25°C*

V

DD

f=24 MHz, No Load

XT is used*

XT is not

used*

used

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

µA

µA

13/28

1

Semiconductor

PEDL66573-02

MSM66573 Family

DC Characteristics 2 (V

Parameter Symbol Condition Min. Typ. Max. Unit

“H” input voltage *1
“H” input voltage

*2, *3, *4, *5, *6, *7

“L” input voltage *1
“L” input voltage

*2, *3, *4, *5, *6, *7

“H” output voltage *1, *4

“H” output voltage *2

“L” output voltage *1, *4

“L” output voltage *2

Input leakage current*3, *6

Input current *5

Input current *7
output leakage current

*1, *2, *4

Pull-up resistance

Input capacitance

Output capacitance

Analog reference supply
current

=2.4 to 3.6 V)

DD

V

V

V

V

IIH/I

I

R

C

I

LO

C

REF

OH

OL

pull

MSM66573L/Q573L (V

MSM66P573 (V

0.44V

IH

—

0.80V

=2.4 to 3.6 V, Ta=–30 to +70°C)

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

DD

—V

—V

DD

DD

+0.3

+0.3

–0.3 — 0.16 V

IL

—

I

=–400 µA

O

IO=–2.0 mA

I

=–200 µA

O

IO=–1.0 mA

IO=3.2 mA

=5.0 mA

I

O

IO=1.6 mA

IO=2.5 mA

–0.3 — 0.2 V

V

–0.4 — —

–0.8 — —

V

V

–0.4 — —

V

–0.8 — —

DD

——0.5

——0.9

——0.5

——0.9

V

— — 1/–1

IL

VI=VDD/0 V

— — 1/–250

µA

— — 15/–15

VO=VDD/0 V — — ±10

VI= 0 V 40 100 200

I

O

f=1 MHz, Ta=25°C

During A/D operation

When A/D is stopped

—5—

—7—

—— 2mA

—— 5

µA
kΩ

pF

µA

*1: Applicable to P0 *5: Applicable to

RES

*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10 *6: Applicable to EA, NMI
*3: Applicable to P12 *7: Applicable to OSC0
*4: Applicable to P3, P11

14/28

1

Semiconductor

PEDL66573-02

MSM66573 Family

Supply current (V

=2.4 to 3.6 V)

DD

• MSM66573L

Mode

CPU operation mode I

HALT mode

STOP mode I

• MSM66Q573L

Mode Symbol Condition Min. Typ. Max. Unit

CPU operation mode I

HALT mode

STOP mode I

=2.4 to 3.6 V, Ta=–30 to +70°C)

(V

DD

Symbol Condition Min. Typ. Max. Unit

—1220mA

— 30 130

µA

— 2 110

— 1 100

µA

—0.210

I

DDH

DDS

DD

f=32.768 kHz, No Load

f=14 MHz, No Load — 7 11 mA

OSC is

stopped

OSC is stopped, XT is not

=2 V, Ta=25°C*

V

DD

f=14 MHz, No Load

XT is used*

XT is not

used*

used

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

(V

=2.4 to 3.6 V, Ta=–30 to +70°C)

DD

—1322mA

— 30 130

µA

— 3 110

— 1 100

µA

—0.210

I

DD

DDH

f=32.768 kHz, No Load

f=14 MHz, No Load — 7 11 mA

OSC is

stopped

DDS

OSC is stopped, XT is not

=2 V, Ta=25°C*

V

DD

f=14 MHz, No Load

XT is used*

XT is not

used*

used

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

• MSM66P573

Mode Symbol Condition Min. Typ. Max. Unit

CPU operation mode I

HALT mode

STOP mode I

(V

=2.7 to 3.6 V, Ta=–30 to +70°C)

DD

—1724mA

— 65 160

— 3 110

— 1 100

—0.210

I

DD

DDH

f=32.768 kHz, No Load

f=12 MHz, No Load — 8 12 mA

OSC is

stopped

DDS

OSC is stopped, XT is not

=2 V, Ta=25°C*

V

DD

f=12 MHz, No Load

XT is used*

XT is not

used*

used

*: Ports used as inputs are at VDD or 0 V. Other ports are unloaded.

µA

µA

15/28

PEDL66573-02

1

Semiconductor

MSM66573 Family

AC Characteristics 1 (VDD = 4.5 to 5.5 V)

(1) External program memory control

MSM66573/Q573/P573 (V

Parameter Symbol Condition Min. Max. Unit

Cycle time

Clock pulse width (HIGH level)

Clock pulse width (LOW level)

PSEN pulse width
PSEN pulse delay time

Address setup time

Address hold time

Instruction setup time

Instruction hold time

Read data access time

t

t

φ

t

t

t

t

t

t

cyc

WH

φ

WL

PW

PD

AS

AH

t

IS

t

IH

ACC

f

=30 MHz 33.3 —

OSC

CL=50 pF

=4.5 to 5.5 V, Ta=–30 to +70°C)

DD

13 —

13 —

2tφ–15

—

—45

tφ–25

—

0—

*1

25

—

0—

—

3tφ–65

*2

Note: t=t

*1: MSM66P573=30

*2: MSM66P573=3t–70

ns

cyc

/2

CPUCLK

PSEN

A0 to A19

D0 to D7

t

cyc

t

φ

WH

t

φ

WL

t

PD

t

PW

PC0 to 19

t

AS

t

AH

INST0 to 7

t

ACC

t

IS

t

IH

Bus timing during no wait cycle time

16/28

PEDL66573-02

1

Semiconductor

MSM66573 Family

(2) External data memory control

MSM66573/Q573/P573 (V

Parameter Symbol Condition Min. Max. Unit

Cycle time

Clock pulse width (HIGH level)

Clock pulse width (LOW level)

RD pulse width
WR pulse width
RD pulse delay time
WR pulse delay time

Address setup time

Address hold time

Read data setup time

Read data hold time

Read data access time

Write data setup time

Write data hold time

t

t

φ

t

t

t

t

t

t

t

t

t

t

t

t

cyc

WH

φ

WL

RW

WW

RD

WD

AS

AH

RS

RH

ACC

WS

WH

f

=30 MHz 33.3 —

OSC

CL=50 pF

=4.5 to 5.5 V, Ta=–30 to +70°C)

DD

13 —

13 —

2tφ–15
2tφ–15

—

—

—45

—45

tφ–25

tφ–3

*1

25

—

—

—

0—

—

2tφ–30

tφ–3

3tφ–65

—

—

*2

Note: t=t

*1: MSM66P573=30

*2: MSM66P573=3t–70

ns

cyc

/2

CPUCLK

RD

A0 to A19

D0 to D7

WR

A0 to A19

D0 to D7

t

cyc

t

t

WH

φ

WL

φ

t

RD

t

RW

RAP0 to 19

t

AS

t

AH

DIN0 to 7

t

ACC

t

WD

t

RS

t

WW

t

RH

RAP0 to 19

t

AS

t

AH

DOUT0 to 7

t

WS

t

WH

Bus timing during no wait cycle time

17/28

1

Semiconductor

(3) Serial port control

Master mode

Parameter Symbol Condition Min. Max. Unit

Cycle time

Serial clock cycle time

Output data setup time

Output data hold time

Input data setup time

Input data hold time

CPUCLK

PEDL66573-02

MSM66573 Family

MSM66573/Q573/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)

t

cyc

t

SCKC

t

STMXS

t

STMXH

t

SRMXS

t

SRMXH

t

cyc

f

=30 MHz 33.3 —

OSC

4t

cyc

2tφ–5

CL=50 pF

5tφ–10

13 —

0—

—

—

—

Note: tφ=t

ns

cyc

/2

TXC/

RXC

SDOUT

(TXD)

SDIN

(RXD)

t

SRMXStSRMXH

t

STMXH

t

SCKC

t

STMXS

18/28

1

Semiconductor

Slave mode

Parameter Symbol Condition Min. Max. Unit

Cycle time

Serial clock cycle time

Output data setup time

Output data hold time

Input data setup time

Input data hold time

CPUCLK

PEDL66573-02

MSM66573 Family

MSM66573/Q573/P573 (V

t

cyc

t

SCKC

t

STMXS

t

STMXH

t

SRMXS

t

SRMXH

t

cyc

f

=30 MHz 33.3 —

OSC

CL=50 pF

=4.5 to 5.5 V, Ta=–30 to +70°C)

DD

4t

cyc

2tφ–15
4tφ–10

—

—

—

ns

13 —

3—

Note: tφ=t

cyc

/2

TXC/

RXC

SDOUT

(TXD)

t

STMXH

SDIN

(RXD)

t

SRMXS

t

SRMXH

Measurement points for AC timing (except the serial port)

V

DD

0 V

2.0 V

0.8 V

Measurement points for AC timing (the serial port)

V

0V

DD

0.8V

0.2V

0.8V

DD

0.2V

DD

t

SCKC

2.0 V

0.8 V

DD

DD

t

STMXS

19/28

1

Semiconductor

AC Characteristics 2 (VDD = 2.4 to 3.6 V)

(1) External program memory control

Parameter Symbol Condition Min. Max. Unit

t

t

φ

t

t

t

t

t

t

cyc

WH

φ

WL

PW

PD

AS

AH

t

IS

t

IH

ACC

Cycle time

Clock pulse width (HIGH level)

Clock pulse width (LOW level)

PSEN pulse width
PSEN pulse delay time

Address setup time

Address hold time

Instruction setup time

Instruction hold time

Read data access time

PEDL66573-02

MSM66573 Family

MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)

f

=14 MHz 71.4 —

OSC

28 —

28 —

CL=50 pF

*1

2tφ–25

—75

tφ–40

*2

-8

—

—

—

ns

60 —

*2

-8

—

—

3tφ–120

Note: t=t

cyc

/2

*1: MSM66P573=2t–20

*2: MSM66P573=0

CPUCLK

PSEN

A0 to A19

D0 to D7

t

cyc

t

φ

WH

t

φ

WL

t

PD

t

PW

PC0 to 19

t

AS

t

AH

INST0 to 7

t

ACC

t

IS

t

IH

Bus timing during no wait cycle time

20/28

1

Semiconductor

(2) External data memory control

Parameter Symbol Condition Min. Max. Unit

Cycle time

Clock pulse width (HIGH level)

Clock pulse width (LOW level)

RD pulse width
WR pulse width
RD pulse delay time
WR pulse delay time

Address setup time

Address hold time

Read data setup time

Read data hold time

Read data access time

Write data setup time

Write data hold time

t

t

φ

t

t

t

t

t

t

t

t

t

t

t

t

cyc

WH

φ

WL

RW

WW

RD

WD

AS

AH

RS

RH

ACC

WS

WH

PEDL66573-02

MSM66573 Family

MSM66573L/Q573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)

MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)

f

=14 MHz 71.4 —

OSC

28 —

28 —

2tφ–25
2tφ–25

*1

*1

—

—

—75

CL=50 pF

—75

tφ–40
tφ–8

*2

—

—

ns

60 —

0—

—

2tφ–40

tφ–6

3tφ–120

—

—

Note: t=t

cyc

/2

*1: MSM66P573=2t–20

*2: MSM66P573=t–6

CPUCLK

RD

A0 to A19

D0 to D7

WR

A0 to A19

D0 to D7

t

cyc

t

t

WH

φ

WL

φ

t

RD

t

RW

RAP0 to 19

t

AS

t

AH

DIN0 to 7

t

ACC

t

WD

t

RS

t

WW

t

RH

RAP0 to 19

t

AS

t

AH

DOUT0 to 7

t

WS

t

WH

Bus timing during no wait cycle time

21/28

1

Semiconductor

(3) Serial port control

Master mode

Parameter Symbol Condition Min. Max. Unit

Cycle time

Serial clock cycle time

Output data setup time

Output data hold time

Input data setup time

Input data hold time

CPUCLK

PEDL66573-02

MSM66573 Family

MSM66573L/Q573L (V

MSM66P573 (V

t

cyc

t

SCKC

t

STMXS

t

STMXH

t

SRMXS

t

SRMXH

t

cyc

f

=14 MHz 71.4 —

OSC

CL=50 pF

=2.4 to 3.6 V, Ta=–30 to +70°C)

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

DD

4tcyc —

2tφ–10
5tφ–20

—

—

ns

21 —

0—

Note: t=t

cyc

/2

TXC/

RXC

SDOUT

(TXD)

SDIN

(RXD)

t

SRMXS

t

SRMXH

t

STMXH

t

SCKC

t

STMXS

22/28

1

Semiconductor

Slave mode

Parameter Symbol Condition Min. Max. Unit

Cycle time

Serial clock cycle time

Output data setup time

Output data hold time

Input data setup time

Input data hold time

CPUCLK

PEDL66573-02

MSM66573 Family

MSM66573L/Q573L (V

MSM66P573 (V

t

cyc

t

SCKC

t

STMXS

t

STMXH

t

SRMXS

t

SRMXH

t

cyc

f

=14 MHz 71.4 —

OSC

CL=50 pF

=2.4 to 3.6 V, Ta=–30 to +70°C)

DD

=2.7 to 3.6 V, Ta=–30 to +70°C)

DD

4t

cyc

2tφ–30
4tφ–20

—

—

—

ns

21 —

7—

Note: t=t

cyc

/2

TXC/

RXC

t

SCKC

SDOUT

(TXD)

t

STMXH

t

STMXS

SDIN

(RXD)

t

SRMXS

t

SRMXH

Measurement points for AC timing of MSM66573L/Q573L

V

DD

0V

0.44V

0.16V

0.44V

DD

DD

0.16V

DD

DD

Measurement points for AC timing of MSM66P573 (except the serial port)

V

DD

0 V

2.0 V

0.8 V

2.0 V

0.8 V

Measurement points for AC timing (the serial port)

V

DD

0V

0.8V

0.2V

DD

DD

0.8V

0.2V

DD

DD

23/28

1

Semiconductor

PEDL66573-02

MSM66573 Family

A/D Converter Characteristics 1 (V

=4.5 to 5.5 V)

DD

MSM6573/Q573/P573 (Ta=–30 to +70°C, V

Parameter

Resolution

Linearity error

Differential Linearity error

Zero scale error

Full-scale error

Cross talk

Conversion time

Symbol Condition Min. Typ. Max. Unit

n—10—Bit

E

L

E

D

E

ZS

E

FS

E

CT

t

CONV

Refer to measurement

circuit 1

Analog input source

impedance

≤5 kΩ

R

I

t

=10.7 µs

CONV

Refer to measurement

circuit 2

Set according to ADTM set

data

A/D Converter Characteristics 2 (VDD=2.4 to 3.6 V)

MSM66573L/Q573L (Ta=–30 to +70°C, VDD=V

MSM66P573 (Ta=–30 to +70°C, VDD=V

Parameter Symbol

Resolution

Linearity error

Differential Linearity error

Zero scale error

Full-scale error

Cross talk

Conversion time

n—10—Bit

E

L

E

D

E

ZS

E

FS

E

CT

t

CONV

Condition Min. Typ. Max. Unit

Refer to measurement

circuit 1

Analog input source

impedance

≤5 kΩ

R

I

t

=27.4 µs

CONV

Refer to measurement

circuit 2

Set according to ADTM set

data

DD=VREF

=4.5 to 5.5 V, AGND=GND=0 V)

——±3

——±2

——+3

LSB

——–3

——±1

10.7 — —

=2.4 to 3.6 V, AGND=GND=0 V)

REF

=2.7 to 3.6 V, AGND=GND=0 V)

REF

µs/ch

——±4

——±3

——+4

LSB

——–4

——±2

27.4 — — s/ch

Reference

voltage

Analog input

V

REF

0.1µF47

+

µF

R

–

+

I

AI0 to AI7

C

I

(impedance of analog input source) ≤5 kΩ

R

I

C

≅ 0.1 µF

I

V

GND

DD

+

0.1µF47

µF

+5 V

0 VAGND

Measurement Circuit 1

24/28

1

Semiconductor

PEDL66573-02

MSM66573 Family

–

+

Analog input

5 k

Ω

AI0

AI1

0.1 µF

to

AI7

V

or AGND

REF

Cross talk is the difference
between the A/D conversion
results when the same
analog input is applied to
AI0 through AI7 and the A/D
conversion results of the
circuit to the left.

Measurement Circuit 2

Definition of Terminology

1. Resolution

Resolution is the value of minimum discernible analog input.
With 10 bits, since 2

= 1024, resolution of (V

– AGND) ÷ 1024 is possible.

REF

10

2. Linearity error

Linearity error is the difference between ideal conversion characteristics and actual conversion c
haracteristics of a 10-bit A/D converter (not including quantization error).
Ideal conversion characteristics can be obtained by dividing the voltage between V

REF

equal steps.

and AGND into 1024

3. Differential linearity error

Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog
input voltage that corresponds to 1 converted bit of digital output is 1LSB = (V

– AGND) ÷ 1024.

REF

Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion
range.

4. Zero scale error

Zero scale error is the difference between ideal conversion characteristics and actual conversion
characteristics at the point where the digital output changes from 000H to 001H.

5. Full-scale error

Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics
at the point where the digital output changes from 3FEH to 3FFH.

25/28

1

Semiconductor

PACKAGE DIMENSIONS

TQFP100-P-1414-0.50-K

Mirror finish

PEDL66573-02

MSM66573 Family

(Unit: mm)

Package material
Lead frame material
Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin
42 alloy
Solder plating
5

m or more

0.55 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

26/28

1

Semiconductor

QFP100-P-1420-0.65-BK

Mirror finish

PEDL66573-02

MSM66573 Family

(Unit: mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5

m or more

1.29 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

27/28

PEDL66573-02

1

Semiconductor

MSM66573 Family

NOTICE

1. The information contained herein can change without notice owing to product and/or technical

improvements. Before using the product, please make sure that the information being referred to is
up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as

an explanation for the standard action and performance of the product. When planning to use the
product, please ensure that the external conditions are reflected in the actual circuit, assembly, and
program designs.

3. When designing your product, please use our product below the specified maximum ratings and

within the specified operating ranges including, but not limited to, operating voltage, power
dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or
accident, improper handling, or unusual physical or electrical stress including, but not limited to,
exposure to parameters beyond the specified maximum ratings or operation outside the specified
operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc.

is granted by us in connection with the use of the product and/or the information and drawings
contained herein. No responsibility is assumed by us for any infringement of a third party’s right
which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for

commercial applications (e.g., office automation, communication equipment, measurement
equipment, consumer electronics, etc.). These products are not authorized for use in any system or
application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to

particular countries. The purchaser assumes the responsibility of determining the legality of export
of these products and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior

permission.

Copyright 1999 Oki Electric Industry Co., Ltd.

28/28

WWW.ALLDATASHEET.COM

Copyright © Each Manufacturing Company.

All Datasheets cannot be modified without permission.

This datasheet has been download from :

www.AllDataSheet.com

100% Free DataSheet Search Site.

Free Download.

No Register.

Fast Search System.

www.AllDataSheet.com