Datasheet MSM6599BGS-K, MSM6599BGS-BK Datasheet (OKI)

E2B0024-27-Y2

¡ Semiconductor

This version: Nov. 1997

Previous version: Mar. 1996

MSM6599B¡ Semiconductor

MSM6599B

80-DOT SEGMENT DRIVER

GENERAL DESCRIPTION

The MSM6599B is a dot matrix LCD segment driver LSI which consists of two 80-bit latches, an
80-bit level shifter and an 80-bit 4-level driver.
It latches the 4-bit parallel display data transferred from a microcomputer or LCD controller LSI,
then outputs the LCD driving waveform to the LCD.

FEATURES

• Supply voltage : 4.5 to 5.5 V

• LCD driving voltage : 18 to 28 V

• Applicable LCD duty : 1/64 to 1/256

• LCD output : 80

• Because of 4-bit parallel transfers, the transfer speed is 1/4 that of conventional serial transfer,
insuring low power consumption.

• Applicable common driver : MSM6698 (80 outputs)

• Package options:
100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM6599B GS-K)
100-pin plastic QFP(QFP100-P-1420-0.65-BK) (Product name : MSM6599B GS-BK)

1/11

BLOCK DIAGRAM

MSM6599B¡ Semiconductor

V

V

V

V

DF

DISP OFF

LOAD

EE

O1O

O

2

3

1

3

80-BIT 4-LEVEL DRIVER

4

O79O

O

78

80

V

DD

V

EE

80-BIT LEVEL SHIFTER

V

DD

V

SS

80-BIT LATCH (II)

D
D
D
D

CP

E

SHL

0
1
2
3

80-BIT LATCH (I)

V

DD

V

SS

CONTROL
CIRCUIT

I

E

O

2/11

PIN CONFIGURATION (TOP VIEW)

50O49O48O47O46O45O44O43O42O41O40O39O38O37O36O35O34O33O32O31

O

99989796959493929190898887868584838281

100

1

O

51

2

O

52

O

3

53

O

4

54

O

5

55

O

6

56

O

7

57

O

8

58

O

9

59

O

10

60

O

11

61

O

12

62

O

13

63

O

14

64

O

15

65

O

16

66

O

17

67

O

18

68

O

19

69

O

20

70

O

21

71

O

22

72

O

23

73

24

O

74

25

O

75

O

26

76

O

27

77

O

28

78

O

29

79

O

30

80

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

MSM6599B¡ Semiconductor

O

30

O

29

O

28

O

27

O

26

O

25

O

24

O

23

O

22

O

21

O

20

O

19

O

18

O

17

O

16

O

15

O

14

O

13

O

12

O

11

O

10

O

9

O

8

O

7

O

6

O

5

O

4

O

3

O

2

O

1

31323334353637383940414243444546474849

1

I

E

4

V

DF

V

V

EE

V3V

SS

DD

V

SHL

NC

NC

NC

3

D

D2D1D

0

CP

LOAD

DISPOFF

NC : No connection

100-Pin Plastic QFP

50

O

E

3/11

ABSOLUTE MAXIMUM RATINGS

MSM6599B¡ Semiconductor

Parameter

Supply Voltage (1)

Supply Voltage (2)

Input Voltage

Storage Temperature

*1 V

≥ V1 > V3 > V4 > V

DD

EE

Symbol

V

DD

VDD– V

V

I

T

STG

EE

*1

RECOMMENDED OPRATING CONDITIONS

Parameter

Supply Voltage (1)

Supply Voltage (2)

Operating Temperature

*1 V

≥ V1 > V3 > V4 > V

DD

EE

Symbol

V

DD

VDD – V

T

op

EE

*1

Condition

Ta = 25°C

Ta = 25°C

Ta = 25°C

—

Condition

—

—

—

Rating

–0.3 to +6.5

0 to 32

–0.3 to V

–55 to +150

Range

4.5 to 5.5

18 to 28

–20 to +75

DD

+ 0.3

Unit

V

V

V

°C

Unit

V

V

°C

4/11

ELECTRICAL CHARACTERISTICS

DC Characteristics

MSM6599B¡ Semiconductor

(VDD = 5V ±10%, Ta = –20 to +75°C)

Parameter

"H" Input Voltage

"L" Input Voltage

"H" Input Current

"L" Input Current

"H" Output Voltage

"L" Output Voltage

ON Resistance

Standby Current

Supply Current (1)

Supply Current (2)

Input Capacitance

Symbol

*1

V

IH

*1

V

IL

*1

I

IH

*1

I

IL

*2

V

OH

*2

V

OL

R

*4

ON

I

DDSBY

I

DD1

I

V

C

I

Condition

—

—

= VDD, VDD = 5.5V

V

I

= 0V, VDD = 5.5V

V

I

= –0.2mA, VDD = 4.5V

I

O

= 0.2mA, VDD = 4.5V

I

O

–VEE = 25V,

V

DD

| V

– VO | = 0.25V VDD = 4.5V

N

= 6.0 MHz, VDD = 5.5V

f

CP

V

DD–VEE

= 25V, No load

fCP = 6.0 MHz, VDD = 5.5V

V

DD–VEE

= 25V, No load

fCP = 6.0 MHz, VDD = 5.5V

V

DD–VEE

= 25V, No load

ƒ = 1 MHz

DD

Typ.

—

—

—

—

—

—

1.5

—

*3

Min.

0.7V

V

DD

V

—

—

—

—

—

SS

–0.4

*5

—— mA

*6

— — 100 mA

*7

—

5

Max.

V

0.3V

–1

—

0.4

3.0

300

1.0

—

DD

1

DD

1.5

Unit

V

V

mA

mA

V

V

kW

mA

pF

*1 Applicable to LOAD, CP, D0 to D3, EI, DF, DISPOFF, SHL.
*2 Applicable to EO.
*3 VN = V1 to VEE V4 = 14/16 (VDD–VEE), V3 = 2/16 (VDD–VEE), VDD = V

1.

*4 Applicable to O1 to O80.
*5 Display Data 1010 fDF = 45 Hz, current from VDD to VSS when the display data is not

being processed.

*6 Display Data 1010 fDF = 45 Hz, current (VDD side current) from VDD to VSS and VEE, and

current (VEE side current) from VDD to V

being processed.

*7 Display Data 1010 fDF = 45 Hz, f

V

EE

DD

V

= 20 kHz, current on V1, V3 and V4.

LOAD

when the display data is

EE

5/11

MSM6599B¡ Semiconductor

Switching Characteristics

(VDD = 5V ±10%. Ta = –20 to +75°C)

Parameter Symbol Condition Min. Typ. Max. Unit

Clock Frequency ƒ

Clock Pulse Width t

Load Pulse Width t

Rise/Fall Time t

Data Setup Time t

Data Hold Time t

Load Setup Time t

Load-to-Clock Time t

Propagation Delay Time t

Setup Time t

E

I

PLH

CP

W1

W2

, t

r

DSU

DHD

LSU

LC

, t

ESU

f

PHL

DUTY = 50% — — 6.5 MHz

— 56——ns

— 70——ns

— ——20ns

— 50——ns

— 50——ns

— 80——ns

— 80——ns

CL=15pF — — 236 ns

— 50——ns

Note: When display control by the DISPOFF pin is performed, the rise and fall time must be

≤ 1µs.

D

0

CP

- D

LOAD

CP

LOAD

E

t

f

t

W1

0.8V

3

DD

0.8V

DD

t

DSU

0.8VDD0.8V

0.2VDD0.2V

0.2V

DD

0.2V
t

DHD

t

r

DD

DD

DD

0.8V

t

t

W1

LSU

DD

1 2 18 19 20

0.8V

DD

t

PLH

0.8V

0

DD

t

r

t

W1

0.8V

0.2V

0.8V

DD

t

W2

0.2V

t

f

DD

DD

DD

t

LC

0.8V

0.2V

t

PHL

DD

DD

0.2V

DD

0.8V

DD

t

ESU

E

I

0.2V

DD

6/11

MSM6599B¡ Semiconductor

FUNCTIONAL DESCRIPTION

Pin Functional Description

•E

I, EO

These are enable pins. When a cascade connection is required, set the first MSM6599B's EI pin
at "L" level and connect EO pin to the next MSM6599B's EI pin. When a single MSM6599B is
used, EI should be set at "L" level.

•CP

Clock input pin for display data input. Data is clocked in the latch (I) at the falling edge of the
clock pulse. The clock pulse from this pin is active when the enable F/F is set, and inactive
when it is not set.

• LOAD

Input pin to latch the display data of one line stored in the latch (I). The latch (I) data is
transferred to the latch (II) at the falling edge. At this time, the control circuit to save the power
is reset and the display data of the next line can be stored.

•DF

Synchronous signal input pin for alternate signal for LCD driving . Frame inversion signal is
input to this pin.

•VDD, V

SS

Power supply pins of the MSM6599B. VDD is generally set to 4.5V to 5.5V. VSS is the GND
pin, which is set to 0V.

7/11

MSM6599B¡ Semiconductor

•D0, D1, D2, D

3

Display data input pins for the 80-bit latch (I). The display data is input at the falling edge of
clock pulse. Table 1 shows the relationship between display data, DF, LCD driver output, and
display.

Table 1

Display Data

L

H

L

H

DF

L

L

H

H

LCD Driver Output

Non-select level (V

Select level (V

Non-select level (V

Select level (V

EE

3

)

1

4

)

)

)

Display

OFF

ON

OFF

ON

• SHL

Input pin to select the loading direction of display data. Set this pin to "H" or "L" level during
power-on. Table 2 shows the relationship between shift direction of data (D0 to D3) and driver
output (O1 to O80).

Table 2

Direction of Data LoadingSHL

D0 Æ O1 Æ O5 Æ O

L

D1 Æ O2 Æ O6 Æ O

D2 Æ O3 Æ O7 Æ O

D3 Æ O4 Æ O8 Æ O

D0 Æ O80 Æ O76 Æ O

H

D1 Æ O79 Æ O75 Æ O

D2 Æ O78 Æ O74 Æ O

D3 Æ O77 Æ O73 Æ O

Last Data First Data

77

78

79

80

4

3

2

1

8/11

MSM6599B¡ Semiconductor

•V1, V3, V4, V

EE

Bias supply voltage pins used to drive the LCD. Use an external bias voltage supply for
driving the LCD

•O1 - O

80

Output pins for the 4-level driver that directly correspond to each bit of the 80-bit latch (II)
contents. One of V1, V3, V4 and VEE is selected and output by a combination of latched content
and DF signals. See the "Truth Table". Connect this output to the segment side of the LCD.

• DISP OFF

Input pin to control O1 to O80 outputs. The V1 level is output from O1 to O80 pins regardless
of the display data during "L" level input. See the "Truth Table".

Truth Table

DF

L

L

H

H

X

Latch Data

L

H

L

H

X

DISPOFF

H

H

H

H

L

Driver Output (O

V

3

V

1

V

4

V

EE

V

1

1

to O80)

X : Don't Care

NOTES ON USE

Precautions when turning power ON/OFF:
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to
the LCD drivers with the logic power supply floating, excess current flows. This may damage
the IC.
Be sure to follow the sequence below when turning the power ON or OFF.
Power ON : Logic circuits ON Æ LCD drivers ON, or both ON at a time
Power OFF : LCD drivers OFF Æ logic circuits OFF, or both OFF at a time

9/11

PACKAGE DIMENSIONS

QFP100-P-1420-0.65-K

Mirror finish

MSM6599B¡ Semiconductor

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.29 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

10/11

QFP100-P-1420-0.65-BK

Mirror finish

MSM6599B¡ Semiconductor

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.29 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

11/11