Page 1
MMBF4391L, MMBF4392L,
MMBF4393L
JFET Switching Transistors
N−Channel
Features
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain−Source Voltage V
Drain−Gate Voltage V
Gate−Source Voltage V
Forward Gate Current I
DS
DG
GS
G(f)
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR− 5 Board
(Note 1) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction−to−Ambient
Junction and Storage Temperature Range TJ, T
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR− 5 = 1.0 0.75 0.062 in.
P
D
R
q
JA
stg
30 Vdc
30 Vdc
30 Vdc
50 mAdc
225
1.8
556 °C/W
−55 to +150 °C
mW
mW/°C
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3
1
2
SOT−23
CASE 318
STYLE 10
2 SOURCE
3
GATE
1 DRAIN
MARKING DIAGRAM
XXX M G
G
1
XXX = Specific Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
© Semiconductor Components Industries, LLC, 1994
October, 2016 − Rev. 12
MARKING & ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 2 of this data sheet.
1 Publication Order Number:
MMBF4391LT1/D
Page 2
MMBF4391L, MMBF4392L, MMBF4393L
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
A
Symbol Min Max Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
(I
= 1.0 mAdc, VDS = 0)
G
Gate Reverse Current
(V
= 15 Vdc, VDS = 0, TA = 25°C)
GS
(VGS = 15 Vdc, VDS = 0, TA = 100°C)
Gate−Source Cutoff Voltage
(V
= 15 Vdc, ID = 10 nAdc)
DS
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
Off−State Drain Current
(V
= 15 Vdc, VGS = −12 Vdc)
DS
(VDS = 15 Vdc, VGS = −12 Vdc, TA = 100°C)
V
(BR)GSS
I
GSS
V
GS(off)
I
D(off)
30 − Vdc
−
−
−4.0
−2.0
−0.5
−
−
1.0
0.20
−10
−5.0
−3.0
1.0
1.0
nAdc
mAdc
nAdc
mAdc
Vdc
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current
(V
= 15 Vdc, VGS = 0)
DS
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
Drain−Source On−Voltage
(I
= 12 mAdc, VGS = 0)
D
MMBF4391LT1
= 6.0 mAdc, VGS = 0)
(I
D
MMBF4392LT1
(I
= 3.0 mAdc, VGS = 0)
D
MMBF4393LT1
Static Drain−Source On−Resistance
(I
= 1.0 mAdc, VGS = 0)
D
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
I
DSS
V
DS(on)
r
DS(on)
50
25
5.0
mAdc
150
75
30
Vdc
−
−
−
0.4
0.4
0.4
W
−
−
−
30
60
100
SMALL− SIGNAL CHARACTERISTICS
Input Capacitance
(V
= 0 Vdc, VGS = −15 Vdc, f = 1.0 MHz)
DS
Reverse Transfer Capacitance
(V
= 0 Vdc, VGS = −12 Vdc, f = 1.0 MHz)
DS
C
iss
C
rss
− 14
− 3.5
pF
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
ORDERING INFORMATION
Device Marking Package Shipping
MMBF4391LT1G 6J
SMMBF4391LT1G* 6J
MMBF4392LT1G 6K
SOT−23
(Pb−Free)
3,000 / Tape & Reel
MMBF4393LT1G M6G
SMMBF4393LT1G*
M6G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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2
Page 3
MMBF4391L, MMBF4392L, MMBF4393L
TYPICAL CHARACTERISTICS
1000
500
200
100
RK = R
D'
MMBF4391
MMBF4392
MMBF4393
50
20
10
, TURN-ON DELAY TIME (ns)
5.0
d(on)
2.0
t
1.0
0.5 1.0 3.0 7.05.0
0.7 2.0 10 20
RK = 0
ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time
1000
500
200
100
50
RK = R
20
10
, TURN-OFF DELAY TIME (ns)
5.0
d(off)
2.0
t
1.0
0.7 2.0 10 20 30 50
RK = 0
ID, DRAIN CURRENT (mA)
MMBF4391
MMBF4392
MMBF4393
D'
5.0
TJ = 25°C
TJ = 25°C
V
V
GS(off)
GS(off)
= 12 V
= 7.0 V
= 5.0 V
30 50
= 12 V
= 7.0 V
= 5.0 V
1000
500
200
RK = R
D'
TJ = 25°C
MMBF4391
MMBF4392
MMBF4393
V
GS(off)
100
50
20
, RISE TIME (ns)
10
r
t
5.0
RK = 0
2.0
1.0
0.5 1.0 3.0 7.05.00.7 2.0 10 20 30 50
, DRAIN CURRENT (mA)
I
D
Figure 2. Rise Time
1000
500
RK = R
D'
200
100
50
20
, FALL TIME (ns)
10
f
t
5.0
RK = 0
2.0
1.0
0.5 1.0 3.0 7.0
0.7 2.0 10 20 30 500.5 1.0 3.0 7.0
ID, DRAIN CURRENT (mA)
5.0
TJ = 25°C
MMBF4391
MMBF4392
MMBF4393
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
= 12 V
= 7.0 V
= 5.0 V
Figure 3. Turn−Off Delay Time
Figure 4. Fall Time
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3
Page 4
MMBF4391L, MMBF4392L, MMBF4393L
V
R
SET V
INPUT
R
GEN
50 W
V
GEN
INPUT PULSE
t
r
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
≤ 0.25 ns
t
≤ 0.5 ns
f
50
W
Figure 5. Switching Time Test Circuit
DS(off)
R
K
R
GG
RD' = RD(RT + 50)
= 10 V
R
> R
GG
V
GG
K
R
+ RT + 50
D
NOTE 1
DD
D
R
T
OUTPUT
50
W
The switching characteristics shown above were measured using
a test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (−V
Drain−Source Voltage (V
Voltage (V
Capacitance (C
V
+ VDS.
GG
) due to the voltage divider. Thus Reverse Transfer
DD
) of Gate−Drain Capacitance (Cgd) is charged to
rss
) is slightly lower than Drain Supply
DS
During the turn−on interval, Gate−Source Capacitance (C
discharges through the series combination of R
discharge to V
through RG and RK in series with the parallel
DS(on)
combination of effective load impedance (R’
Resistance (r
). During the turn−off, this charge flow is reversed.
DS
and RK. Cgd must
Gen
) and Drain−Source
D
GG
). The
gs
)
Predicting turn−on time is somewhat difficult as the channel
resistance r
discharges, VGS approaches zero and rDS decreases. Since C
is a function of the gate−source voltage. While C
DS
gs
gd
discharges through rDS, turn−on time is non−linear. During turn−off,
the situation is reversed with r
increasing as Cgd charges.
DS
The above switching curves show two impedance conditions; 1)
R
is equal to RD’ which simulates the switching behavior of
K
cascaded stages where the driving source impedance is normally the
load impedance of the previous stage, and 2) R
= 0 (low
K
impedance) the driving source impedance is that of the generator.
20
MMBF4392
MMBF4391
10
MMBF4393
7.0
T
= 25°C
5.0
channel
VDS = 15 V
3.0
2.0
0.5 1.0 3.0 7.05.0 5030
, FORWARD TRANSFER ADMITTANCE (mmhos)
V
0.7 2.0 10 20
fs
ID, DRAIN CURRENT (mA)
Figure 6. Typical Forward Transfer Admittance
200
160
120
80
40
RESISTANCE (OHMS)
0
DS(on)
r , DRAIN-SOURCE ON-STATE
I
DSS
25 mA
= 10
mA
1.0 3.0
100 mA
75 mA50 mA
2.0
V
, GATE-SOURCE VOLTAGE (VOLTS)
GS
4.00
125 mA
T
5.0
= 25°C
channel
6.0 7.0 8.0
15
10
7.0
5.0
3.0
C, CAPACITANCE (pF)
2.0
1.5
1.0
Figure 7. Typical Capacitance
2.0
1.8
1.6
1.4
1.2
1.0
0.8
, DRAIN-SOURCE ON-STATE
RESISTANCE (NORMALIZED)
0.6
DS(on)
r
0.4
ID = 1.0 mA
V
T
= 25°C
channel
(Cds is negligible
0.5 1.0 3.0 305.00.30.1 100.050.03
V
, REVERSE VOLTAGE (VOLTS)
R
= 0
GS
50
20-10-40
T
, CHANNEL TEMPERATURE (°C)
channel
C
gs
C
gd
80 140-70
110
170
Figure 8. Effect of Gate−Source Voltage
on Drain−Source Resistance
Figure 9. Effect of Temperature on Drain−Source
On−State Resistance
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4
Page 5
100
90
80
70
60
50
40
30
, DRAIN-SOURCE ON-STATE
RESISTANCE (OHMS)
20
10
DS(on)
r
0
10
30 40 50 60
20
I
DSS
Figure 10. Effect of I
Resistance and Gate−Source Voltage
MMBF4391L, MMBF4392L, MMBF4393L
T
= 25°C
channel
r
@ VGS = 0
DS(on)
V
GS(off)
80 90 100 110 120 130 140 150
70
, ZERO-GATE VOLTAGE DRAIN CURRENT (mA)
on Drain−Source
DSS
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
, GATE-SOURCE VOLTAGE
GS
V
NOTE 2
The Zero−Gate−Voltage Drain Current (I
principle determinant of other J−FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
Voltage (V
(r
) to I
DS(on)
) and Drain−Source On Resistance
GS(off)
. Most of the devices will be within
DSS
±10% of the values shown in Figure 10. This data will
be useful in predicting the characteristic variations for
(VOLTS)
a given part number.
For example:
Unknown
r
and VGS range for an MMBF4392
DS(on)
The electrical characteristics table indicates that an
MMBF4392 has an I
10 shows r
I
= 75 mA. The corresponding VGS values are 2.2 V
DSS
DS(on)
= 52 W for I
range of 25 to 75 mA. Figure
DSS
= 25 mA and 30 W for
DSS
and 4.8 V.
DSS
) is the
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5
Page 6
MMBF4391L, MMBF4392L, MMBF4393L
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AR
D
0.25
3
E
1
2
H
E
T
L
3X
b
e
TOP VIEW
L1
VIEW C
A
A1
SIDE VIEW
SEE VIEW C
c
END VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
DIMAMIN NOM MAX MIN
A1
b 0.37 0.44 0.50 0.015
c 0.08 0.14 0.20 0.003
D 2.80 2.90 3.04 0.110
E 1.20 1.30 1.40 0.047
e 1.78 1.90 2.04 0.070
L
L1
H
T
STYLE 10:
PIN 1. DRAIN
MILLIMETERS
0.89 1.00 1.11 0.035
0.01 0.06 0.10 0.000
0.30 0.43 0.55 0.012
0.35 0.54 0.69 0.014 0.021 0.027
2.10 2.40 2.64 0.083 0.094 0.104
E
0 −−− 10 0 −−− 10
2. SOURCE
3. GATE
INCHES
NOM MAX
0.039 0.044
0.002 0.004
0.017 0.020
0.006 0.008
0.114 0.120
0.051 0.055
0.075 0.080
0.017 0.022
____
RECOMMENDED
SOLDERING FOOTPRINT*
2.90
3X
0.90
3X
0.80
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MMBF4391LT1/D
6
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