Page 1
Preliminary Spec.
APPLICATION
(at Latch mode)
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH64S72AWJA is 67108864 - word x 72-bit
Synchronous DRAM module. This consist of thirty-six
industry standard 32M x 4 Synchronous DRAMs in
smalTSOP.
The smal TSOP on a card edge dual in-line package
provides any application where high densities and large
of quantities memory are required.
This is a socket-type memory module ,suitable for
easy interchange or addition of module.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
85pin
1pin
FEATURES
Frequency
133MHz
-7
100MHz
-8
Utilizes industry standard 32M X 4 Synchronous DRAMs in
smal TSOP package , industry standard Resister in TSSOP
package , and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst Write / Single Write (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
4096 refresh cycles every 64ms
Main memory unit for computers, Microcomputer memory.
CLK Access Time
5.4ns(CL=4)-6
6.0ns(CL=3)
6.0ns(CL=4)100MHz
94pin
95pin
124pin
125pin
168pin
10pin
11pin
40pin
41pin
84pin
MIT-DS-372-0.2
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ELECTRIC
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61 NC
20 DQ15 62 NC
21
22
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
CB0
CB1
/WE0
A10
BA1
43
54 VSS
63
64 VSS
69 DQ24
80 NC
81
VSS 85
86
87
88
89
90
91
92
93
CB2
CB3
NC
VSS 110
CK2
WP
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146
CB4
CB5
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
/S1
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
NC
147
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
/S3
NC
CB6
CB7
NC
REGE
CK3
NC = No Connection
MIT-DS-372-0.2
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Add
D18
D19D0D1
D2
D20
D3
D21
D4
D22D5D23D6D24D7D25
D8
D26
D9
D27
D10
D28
D11
D29
D12
D30
D13
D31
D14
D32
D15
D33
D16
D34
D17
D35
47K
CKE0
/S0-3
DQM0-7
/W
/RAS
/CAS
REGE
Vdd
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Preliminary Spec.
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
RCKE0
R/S0-3
RDQM0-7
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CB0
CB1
CB2
CB3
From PLL
CK0
CK1 - CK3 Terminated
RCKE0
R/S0
R/S1
R/S2
R/S3
PLL
D0-35
D18-21,26-30
D0-3,8-12
D22-25,31-35
D4-713-17
RDQM 0
RDQM 1
RDQM 2
RDQM 3
RDQM 4
RDQM 5
RDQM 6
RDQM 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB4
CB5
CB6
CB7
D0-1,D18-19
D2-3,D8,D20-21,D26
SCL
WP
D4-5,D22-23
D6-7,D24-25
D9-10,D27-28
D11-12,D17,D29-30,D35
D13-14,D31-32
D15-16,D33-34
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
VDD
VSS
SDA
D0 to D35
D0 to D35
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Preliminary Spec.
PIN FUNCTION
Combination of /RAS,/CAS,/W defines basic commands.
the bank to which a command is applied.BA must be set
Register enable:When REGE is low,All control signals and
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CK0
CKE0
/S0 - 3
/RAS,/CAS,/W
A0-11
BA0-1
Input
Input
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-10.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
with ACT,PRE,READ,WRITE commands
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
MIT-DS-372-0.2
Input/Output
Input
Power Supply
Output
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted module.
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH64S72AWJA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
Precharge All Bank
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
MNEMONIC
CKE
n-1
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CKE
n
/S
/RAS
/CAS
/WE BA0,1 A10
A11
X
X
A0-9
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X
H X L H L L V L V
L H L H H H X X X
H X L H H L X X X
H X L L L L L L
V
X
X
V
V
V
V
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
TBST
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoÂPrecharge*3
Action
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Preliminary Spec.
Some contents are subject to change without notice.
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoÂPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoÂPrecharge*3
ILLEGAL
ILLEGAL
Action
MIT-DS-372-0.2
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Preliminary Spec.
Some contents are subject to change without notice.
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-372-0.2
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
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Preliminary Spec.
1. All entries assume that CKE was High during the preceding clock cycle and the current
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
NOP(Idle after tRC)
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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Preliminary Spec.
Some contents are subject to change without notice.
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
CKE
CKE
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
L X X X X X X
L L X X X X X
n
/RAS /CAS /WE Add Action
/S
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
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Preliminary Spec.
POWER ON SEQUENCE
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
LENGTH
BURST
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
LATENCY
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
WRITE
MODE
MIT-DS-372-0.2
0
1
BURST
SINGLE BIT
MITSUBISHI
R:Reserved for Future Use
FP: Full Page
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Preliminary Spec.
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
Write
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
Y
D0 D1 D2 D3
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-372-0.2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
MITSUBISHI
ELECTRIC
17/Mar. /2000
13
Page 14
Preliminary Spec.
ABSOLUTE MAXIMUM RATINGS
mA
RECOMMENDED OPERATING CONDITION
CAPACITANCE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
Symbol
Vdd
VI
VO
IO
Pd
Topr
Tstg
Operating Temperature
Parameter
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Storage Temperature
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Vdd
Parameter
Supply Voltage
Condition
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25°C
Min.
3.0
Limits
Typ.
3.3
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
39
0 ~ 70
-45 ~ 100
Max.
3.6
Unit
V
V
V
W
°C
°C
Unit
V
Vss
VIH
VIL
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Supply Voltage
0
2.0
-0.3
0
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
Input Capacitance, address pin
CI(C)
CI(CK)
CI(K)
CI/O
MIT-DS-372-0.2
Parameter
Input Capacitance, control pin
Input Capacitance, CKE pin
Input Capacitance, CK pin
Input Capacitance, I/O pin
MITSUBISHI
Test Condition
@1MHz
1.4V bias
200mV swing
Limits(max.)
ELECTRIC
Vdd+0.3
25
25
50
35
22
0
0.8
Unit
pF
pF
pF
pF
pF
17/Mar. /2000
V
V
V
14
Page 15
Preliminary Spec.
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
Limits
(max)
precharge stanby
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
one bank active (discrete)
Some contents are subject to change without notice.
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
current
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note)
1:Icc(max) is specified at the output open condition.
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1,CL=3
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
CKE=CLK=L, /CS>Vcc-0.2V
CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)
CKE=H,tCLK=15ns
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
-6
2590
322
286
1150
790
1330
970
3310
6010
322
-7, -8
2450
272
236
1100
740
1280
920
2720
5960
272
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC)
VOL(DC)
IOZ Off-stare Output Current
VOH(AC) High-Level Output Voltage(AC) CL=50pF, IOH=-
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
MIT-DS-372-0.2
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
Input Current
Ii
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd -20 20 uA
2mA
VIH=0 ~ Vdd+0.3V
MITSUBISHI
Limits
Min. Max.
2.4 V
0.4 V
2 V
10
-10
uA
Unit
ELECTRIC
17/Mar. /2000
15
Page 16
Preliminary Spec.
AC TIMING REQUIREMENTS
Some contents are subject to change without notice.
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Limits
Symbol Parameter
-6
Min. Max.
-7
Min. Max.
MITSUBISHI LSIs
-8
Min. Max.
Unit
tCLK
CK cycle time
CL=3
CL=4
tCH CK High pulse width 3
tCL CK Low pilse width 3 ns
tT Transition time of CK 1 10 ns
tIS Input Setup time(all inputs) 2 ns
tIH Input Hold time(all inputs) 1 ns
tRC Row cycle time 70 ns
tRCD Row to Column Delay 20 ns
tRAS Row Active time 50 100K ns
tRP Row Precharge time 20 ns
tWR Write Recovery time 20 ns
tRRD
Act to Act Deley time
tRSC Mode Register Set Cycle time 20 ns
tSRX Self Refresh Exit time 10 ns
10
7.5
2.5
2.5
1 10
1.5
0.8
67.5
20
45 100K
20
15
15
15
7.5
10
13
10 10 ns
3
3
1 10
2
1
70
20
50 100K
20
20
20 ns
20
20
10
ns
ns
tPDE Power Down Exit time 10 ns107.5
tREF Refresh Interval time 64 ms
64
64
CK
Signal
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
17/Mar. /2000
16
Page 17
Preliminary Spec.
SWITCHING CHARACTERISTICS
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol Parameter
MH64S72AWJA -6,-7,-8
-6
Min. Max.
Limits
-7
Min. Max.
MITSUBISHI LSIs
-8
Min. Max.
Unit
tCLK
CK cycle time
CL=2
CL=3
tCH CK High pulse width 3
tCL CK Low pilse width 3 ns
tT Transition time of CK 1 10 ns
tIS Input Setup time(all inputs) 7 ns
tIH Input Hold time(all inputs) 0 ns
tRC Row cycle time 70 ns
tRCD Row to Column Delay 20 ns
tRAS Row Active time 50 100K ns
tRP Row Precharge time 20 ns
tWR Write Recovery time 20 ns
tRRD
Act to Act Deley time
tRSC Mode Register Set Cycle time 20 ns
tSRX Self Refresh Exit time 10 ns
10
7.5
2.5
2.5
1 10
6.5
0
67.5
20
45 100K
20
15
15
15
7.5
10
13
10 10 ns
3
3
1 10
7
0
70
20
50 100K
20
20
20 ns
20
20
10
tPDE Power Down Exit time 10 ns107.5
tREF Refresh Interval time 64 ms
64
64
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
ns
ns
LATCH MODE
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
MIT-DS-372-0.2
Access time from CK
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
CL=3
CL=4
CL=3
MITSUBISHI
ELECTRIC
-6
Min.
Max.
3
0
2.7 5.4
6
5.4
Limits
-7
Min.
3
0
3 6
Max.
6
6
-8
Min. Max.
7
6
3 ns
3 ns32.7CL=4
0 ns
3 ns6
17/Mar. /2000
Unit
ns
ns
17
Page 18
Preliminary Spec.
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol Parameter
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
Limits
-8
Min. Max.
Min.
-6
Max.
Min.
-7
Max.
Unit
tAC
tOH
tOLZ
tOHZ
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Access time from CK
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
CL=2
CL=3
CL=2
6
5.4
3
0
2.7 5.4
3
0
3 6
Output Load Condition
VOUT
50pF
CK
DQ
6
6
7
6
ns
ns
3 ns
3 ns32.7CL=3
0 ns
3 ns6
1.4V
1.4V
MIT-DS-372-0.2
CK
DQ
tAC
tOH
MITSUBISHI
ELECTRIC
Output Timing
Measurement
Reference Point
tOHZ
1.4V
1.4V
17/Mar. /2000
18
Page 19
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
WRITE CYCLE (single bank)
1
0
tRCD
3
2
tRAS
5
4
tRC
6
tWR
7
9
8
tRP
BL=4,Buffer mode(REGE="L")
10
11
12
tRCD
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
0 0
D0 D0 D0 D0
WRITE#0
PRE#0
X
X
X
0
ACT#0
Italic parameter indicates minimum case
Y
0
D0 D0 D0 D0
WRITE#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
19
Page 20
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
WRITE CYCLE (dual bank)
1
0
tRRD
2
tRCD
3
4
tRAS
5
tRC
6
tWR
7
9
8
BL=4,Buffer mode(REGE="L")
10
tRP
tWR
11
12
tRRD
13
tRCD
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
0 1
1
D0 D0 D0 D0
WRITE#0
ACT#1
Y
0
D1 D1 D1 D1
PRE#0
WRITE#1
Italic parameter indicates minimum case
X
X
X
0
ACT#0
X
X
X
1
2
ACT#2
PRE#1
Y
0
D0 D0 D0 D0
WRITE#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
20
Page 21
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
WRITE CYCLE (single bank)
1
0
tRCD
3
2
tRAS
5
4
tRC
6
tWR
7
9
8
tRP
BL=4,Lacth mode(REGE="H")
10
11
12
tRCD
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
0 0
D0 D0 D0 D0
WRITE#0
PRE#0
X
X
X
0
ACT#0
Italic parameter indicates minimum case
Y
0
D0 D0 D0 D0
WRITE#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
21
Page 22
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
WRITE CYCLE (dual bank)
1
0
tRRD
2
tRCD
3
4
tRAS
BL=4,Latch mode(REGE="H")
5
tRC
6
tWR
7
9
8
10
tRP
tWR
11
12
tRRD
13
tRCD
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
0 1
1
D0 D0 D0 D0
WRITE#0
ACT#1
Y
0
D1 D1 D1 D1
PRE#0
WRITE#1
Italic parameter indicates minimum case
X
X
X
0
ACT#0
X
X
X
1
2
ACT#2
PRE#1
Y
0
D0 D0 D0
WRITE#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
22
Page 23
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
READ CYCLE (single bank)
1
0
tRCD
3
2
tRAS tRP
5
4
tRC
DQM read latency =2
7
6
8
BL=4,CL=3,Buffer mode(REGE="L")
9
10
11
12
tRCD
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
0 0
CL=3
Q0 Q0 Q0 Q0
READ#0
READ to PRE ≥ BL allows full data out
PRE#0
X
X
X
0
ACT#0
Italic parameter indicates minimum case
Y
0
Q0 Q0
READ#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
23
Page 24
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,CL=3,Buffer mode(REGE="L")READ CYCLE (dual bank)
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
tRRD
tRCD
X
3
2
Y
X
5
4
tRAS tRP
DQM read latency =2
6
tRC
7
Y
9
8
10
11
X
12
tRRD
13
tRCD
15
14
Y
X
16
17
A10
A11
BA0,1
REGE
DQ
MIT-DS-372-0.2
X
X
0
ACT#0
X
X
0 0
1
CL=3
READ#0
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
PRE#0
READ#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
X
X
0
Q1 Q1 Q1 Q1
ACT#0
PRE#1
X
X
21
ACT#2
0
READ#0
17/Mar. /2000
Q0
24
Page 25
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
READ CYCLE (single bank)
1
0
tRCD
3
2
4
tRAS tRP
DQM read latency =3
5
tRC
7
6
9
8
BL=4, CL=3,Latch mode(REGE="H")
10
11
12
tRCD
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
0 0
CL=3
Q0 Q0 Q0 Q0
READ#0
READ to PRE ≥ BL allows full data out
PRE#0
X
X
X
0
ACT#0
Italic parameter indicates minimum case
Y
0
Q0 Q0
READ#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
25
Page 26
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,CL=3,Latch mode(REGE="H")READ CYCLE (dual bank)
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
tRRD
tRCD
X
3
2
Y
X
5
4
tRAS tRP
DQM read latency =3
6
tRC
7
Y
9
8
10
11
X
12
tRRD
13
tRCD
15
14
Y
X
16
17
A10
A11
BA0,1
REGE
DQ
MIT-DS-372-0.2
X
X
0
ACT#0
X
X
0 0
1
CL=3
READ#0
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
PRE#0
READ#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
X
X
0
Q1 Q1 Q1 Q1
ACT#0
PRE#1
X
X
21
ACT#2
0
READ#0
17/Mar. /2000
Q0
26
Page 27
Preliminary Spec.
/WE
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
tRRD
2
tRCD
4
3
Y
X
6
5
tRC
BL-1+ tWR + tRP
7
Y X
8
10
9
BL-1+ tWR + tRP
11
tRCD
12
tRRD
13
14
Y
16
15
X
17
tRCD
Y
A10
A11
BA0,1
REGE
DQ
MIT-DS-372-0.2
X
X
0
ACT#0
X
X
1
ACT#1
0 1
D0 D0 D0 D0
WRITE#0 with
AutoPrecharge
MITSUBISHI
ELECTRIC
X
X
0
D1 D1 D1 D1
ACT#0
WRITE#1 with
AutoPrecharge
Italic parameter indicates minimum case
0
D0 D0 D0 D0
WRITE#0
X
X
1
ACT#1
1
D1
WRITE#1
17/Mar. /2000
27
Page 28
Preliminary Spec.
/WE
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
tRRD
2
tRCD
4
3
Y
X
6
5
tRC
BL-1+ tWR + tRP
7
Y X
8
10
9
BL-1+ tWR + tRP
11
12
tRRD
tRCD
13
14
Y
X
15
16
tRCD
17
Y
A10
A11
BA0,1
REGE
DQ
MIT-DS-372-0.2
X
X
0
ACT#0
ACT#1
X
X
0 1
1
D0 D0 D0 D0
WRITE#0 with
AutoPrecharge
D1 D1 D1 D1
WRITE#1 with
AutoPrecharge
MITSUBISHI
ELECTRIC
X
X
0
ACT#0
Italic parameter indicates minimum case
WRITE#0
X
X
0
1
D0 D0 D0 D0
ACT#1
17/Mar. /2000
1
WRITE#1
28
Page 29
Preliminary Spec.
/WE
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
tRRD
tRCD
2
X
4
3
Y
6
5
tRC
BL+tRP
DQM read latency =2
8
7
Y
10
9
BL+tRP
X
11
12
tRRD
tRCD
13
14
Y
X
15
16
tRCD
17
Y
A10
A11
BA0,1
REGE
DQ
MIT-DS-372-0.2
X
X
0
ACT#0
ACT#1
X
X
0
1
CL=3
READ#0 with
Auto-Precharge
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with
Auto-Precharge
MITSUBISHI
ELECTRIC
X
X
0
Q1 Q1 Q1 Q1
ACT#0
Italic parameter indicates minimum case
READ#0
0
X
X
1
CL=3
ACT#1
1
Q0
Q0
17/Mar. /2000
29
Page 30
Preliminary Spec.
/WE
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
tRRD
tRCD
2
X
4
3
Y
6
5
tRC
BL+tRP
DQM read latency =3
8
7
Y
10
9
BL+tRP
X
11
12
tRRD
tRCD
13
14
Y
16
15
X
17
tRCD
Y
A10
A11
BA0,1
REGE
DQ
MIT-DS-372-0.2
X
X
0
ACT#0
ACT#1
X
X
0
1
CL=3
READ#0 with
Auto-Precharge
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with
Auto-Precharge
MITSUBISHI
ELECTRIC
X
X
0
Q1 Q1 Q1 Q1
ACT#0
Italic parameter indicates minimum case
READ#0
0
X
X
1
CL=3
ACT#1
17/Mar. /2000
Q0
1
Q0
30
Page 31
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Page Mode Burst Write (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
0 0
1
D0 D0 D0 D0
WRITE#0
ACT#1
Y Y
D0 D0 D0 D0 D0 D0 D0
WRITE#0
Y
1
D1 D1 D1 D1
WRITE#1
Italic parameter indicates minimum case
0
WRITE#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
31
Page 32
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Page Mode Burst Write (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Latch mode(REGE="H")
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
Y
X
X
X
0 0
1
D0 D0 D0 D0
WRITE#0
ACT#1
Y Y
D0 D0 D0 D0 D0 D0
WRITE#0
Y
1
D1 D1 D1 D1
WRITE#1
Italic parameter indicates minimum case
0
WRITE#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
32
Page 33
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Page Mode Burst Read (multi bank)
1
0
tRRD
2
tRCD
3
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
DQM read latency=2
Y
X
X
X
0 0
1
CL=3
READ#0
ACT#1
Y Y
CL=3
Q0 Q0 Q0
Q0
READ#0
Y
1
CL=3
Q0 Q0 Q0 Q0
READ#1
0
Q1 Q1 Q1 Q1
READ#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
33
Page 34
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Page Mode Burst Read (multi bank)
1
0
tRRD
tRCD
3
2
5
4
7
6
BL=4,Latch mode(REGE="H")
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
DQM read latency=3
Y
X
X
X
0 0
1
CL=3
READ#0
ACT#1
Y Y
CL=3
Q0 Q0 Q0
Q0
READ#0
Y
1
CL=3
Q0 Q0 Q0 Q0
READ#1
0
Q1 Q1 Q1 Q1
READ#0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
34
Page 35
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Write / Read
0
1
tRRD
tRCD
2
4
3
5
6
tCCD
7
BL=4,Buffer mode(REGE="L")
8
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
Y
X
X
X
0
1
D0 D0 D0 D0
WRITE#0
Y Y
0 0 0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0
WRITE#0
Y
1
WRITE#1
Y
READ#0
Italic parameter indicates minimum case
CL=3
Q0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
35
Page 36
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Write / Read
0
1
tRRD
tRCD
2
4
3
5
6
tCCD
BL=4,Latch mode(REGE="H")
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
REGE
DQ
X
X
X
0
ACT#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
Y
X
X
X
0
1
WRITE#0
Y Y
0 0 0
D0 D0 D0 D0
WRITE#0
WRITE#0
Y
1
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#1
Y
READ#0
Italic parameter indicates minimum case
CL=3
Q0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
36
Page 37
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Read / Write
1
0
tRRD
tRCD
3
2
5
4
DQM read latency=2
6
BL=4,Buffer mode(REGE="L")
7
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
Y
X
X
X
0 0
1
READ#0
Y Y
Q0 Q0 Q0
READ#0
Y
0
Q0
READ#0
Y
1
READ#1
Y
0
Q0 Q0 Q1 Q1
READ#0
0
Q0 D0 D0
WRITE#0
blank to prevent bus contention
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
37
Page 38
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Read / Write
1
0
tRRD
tRCD
3
2
5
4
6
DQM read latency=3
BL=4,Latch mode(REGE="H")
7
9
8
10
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
Y
X
X
X
0 0
1
READ#0
Y Y
Q0 Q0 Q0
READ#0
Y
0
Q0
READ#0
Y
1
READ#1
Y
0
Q0 Q0 Q1 Q1
READ#0
0
Q0 D0
WRITE#0
blank to prevent bus contention
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
38
Page 39
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Precharge
0
1
tRRD
tRCD
2
4
3
6
5
BL=4,Buffer mode(REGE="L")
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
X
X
X
0
1
D0 D0 D0 D0
WRITE#0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
Y
0
1
PRE#1
Burst Write is interrupted by
Precharge of the same bank.
1 1
D1 D1 D1 D1 D1
PRE#0
X
X
X
1
ACT#1
Y
WRITE#1
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
39
Page 40
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Write Interrupted by Precharge
0
1
tRRD
2
tRCD
4
3
6
5
BL=4,Latch mode(REGE="H")
8
7
10
9
11
12
13
14
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
X
X
X
0
1
D0 D0 D0 D0
WRITE#0
ACT#1
Burst Write is not interrupted
by Precharge of the other bank.
WRITE#1
Y
1 1
PRE#0
1
0
D1 D1 D1 D1 D1
PRE#1
Burst Write is interrupted by
Precharge of the same bank.
X
X
X
1
ACT#1
Y
WRITE#1
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
40
Page 41
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Precharge
0
1
tRRD
tRCD
2
4
3
6
5
DQM read latency=2
BL=4,Buffer mode(REGE="L")
8
7
10
9
11
tRP
12
13
14
tRCD
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
Y
X
X
X
0
1
READ#0
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q0 Q0 Q0
Q0
READ#1
0
PRE#0
X
X
X
1
Q1 Q1
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
1
ACT#1
Y
1
READ#1
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
41
Page 42
Preliminary Spec.
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
Read Interrupted by Precharge
0
1
tRRD
tRCD
2
4
3
6
5
BL=4,Latch mode(REGE="H")
8
7
10
9
11
tRP
12
13
14
tRCD
15
16
17
A0-9
A10
A11
BA0,1
DQ
REGE
X
X
X
0
ACT#0
DQM read latency=3
Y
X
X
X
0
1
READ#0
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q0 Q0 Q0
Q0
READ#1
0
PRE#0
X
X
X
1
Q1 Q1
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
1
ACT#1
Y
1
READ#1
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
Italic parameter indicates minimum case
17/Mar. /2000
42
Page 43
Preliminary Spec.
Mode Register Setting
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
3
2
5
4
tRC
7
6
9
8
M
10
tRSC
11
13
12
tRCD
X
14
15
Y
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
MITSUBISHI
ELECTRIC
X
X
0
0
ACT#0
Italic parameter indicates minimum case
0
D0
D0 D0 D0
WRITE#0
17/Mar. /2000
43
Page 44
Preliminary Spec.
Auto-Refresh @BL=4
/WE
After tRC from Auto-Refresh,
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
3
2
5
4
tRC
7
6
9
8
X
10
11
tRCD
12
13
Y
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
Auto-Refresh
Before Auto-Refresh,
all banks must be idle state.
X
X
0
ACT#0
all banks are idle state.
MITSUBISHI
ELECTRIC
0
D0
D0 D0 D0
WRITE#0
Italic parameter indicates minimum case
17/Mar. /2000
44
Page 45
Preliminary Spec.
Self-Refresh
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
CKE must be low to maintain Self-Refresh
3
2
CLK can be stopped
5
4
7
6
tSRX
9
8
10
11
12
tRC
13
14
15
17
16
X
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
After tRC from Self-Refresh Exit,
all banks are idle state.
MITSUBISHI
ELECTRIC
X
X
0
ACT#0
Italic parameter indicates minimum case
17/Mar. /2000
45
Page 46
Preliminary Spec.
DQM Write Mask @BL=4
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
2
tRCD
4
3
Y
6
5
8
7
Y
10
9
11
12
Y
13
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
X
X
0
ACT#0
0 0
D0 D0 D0 D0
WRITE#0
MITSUBISHI
ELECTRIC
masked
WRITE#0
0
masked
D0 D0 D0
WRITE#0
Italic parameter indicates minimum case
17/Mar. /2000
46
Page 47
Preliminary Spec.
DQM Write Mask @BL=4
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
2
tRCD
4
3
Y
6
5
8
7
Y
10
9
11
12
Y
13
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
X
X
0
ACT#0
0 0
D0 D0 D0 D0
WRITE#0
MITSUBISHI
ELECTRIC
WRITE#0
masked
0
masked
D0 D0 D0
WRITE#0
Italic parameter indicates minimum case
17/Mar. /2000
47
Page 48
Preliminary Spec.
DQM Read Mask @BL=4 CL=3
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
2
tRCD
4
3
Y
6
5
8
7
DQM read latency=2
Y
10
9
11
12
Y
13
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
X
X
0
ACT#0
0 0
Q0 Q0 Q0 Q0
READ#0
MITSUBISHI
ELECTRIC
READ#0
0
masked
READ#0
Italic parameter indicates minimum case
masked
Q0 Q0 Q0
17/Mar. /2000
48
Page 49
Preliminary Spec.
DQM Read Mask @BL=4 CL=3
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
X
1
2
tRCD
4
3
Y
6
5
8
7
DQM read latency=3
Y
10
9
11
12
Y
13
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
X
X
0
ACT#0
0 0
Q0 Q0 Q0 Q0
READ#0
MITSUBISHI
ELECTRIC
READ#0
0
masked
READ#0
Italic parameter indicates minimum case
masked
Q0 Q0 Q0
17/Mar. /2000
49
Page 50
Preliminary Spec.
Power Down
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
0
2
1
4
3
Standby Power Down
6
5
8
7
CKE latency=1
9
X
10
11
12
14
13
Active Power Down
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
Precharge All
MITSUBISHI
ELECTRIC
X
X
0
ACT#0
Italic parameter indicates minimum case
17/Mar. /2000
50
Page 51
Preliminary Spec.
CLK Suspend @BL=4 CL=3
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,Buffer mode(REGE="L")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
tRCD
CKE latency=1
X
3
2
Y
5
4
7
6
9
8
10
CKE latency=1
Y
11
12
13
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
X
X
0
ACT#0
0 0
D0 D0 D0D0
WRITE#0
CLK suspended
MITSUBISHI
ELECTRIC
READ#0
Q0 Q0 Q0 Q0
CLK suspended
Italic parameter indicates minimum case
17/Mar. /2000
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Preliminary Spec.
CLK Suspend @BL=4 CL=3
/WE
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
BL=4,Latch mode(REGE="H")
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-9
1
0
tRCD
CKE latency=1
X
3
2
Y
5
4
7
6
9
8
10
CKE latency=1
Y
11
12
13
14
15
16
17
A10
A11
BA0,1
DQ
REGE
MIT-DS-372-0.2
X
X
0
ACT#0
0 0
D0 D0 D0D0
WRITE#0
CLK suspended
MITSUBISHI
ELECTRIC
READ#0
Q0 Q0 Q0 Q0
CLK suspended
Italic parameter indicates minimum case
17/Mar. /2000
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Page 53
Preliminary Spec.
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
ECC
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8-8-7
-7
-7,-8
-6
-7,-8
-6
-6
-6
-7,-8
-6
-7,-8-6-7,-8-6-7,-8
-6
buffered,registered
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
Byte
0
Defines # bytes written into serial memory at module mfgr
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
# Column Addresses on this assembly
Voltage interface standard of this assembly LVTTL 01
DIMM Configuration type (Non-parity,Parity,ECC)
Function described
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
SPD enrty data SPD DATA(hex)
128
256 Bytes
SDRAM
A0-A11
A0-A10 0B
2BANK 02
x72 48
0 00
10ns
5.4ns
6ns
self refresh(15.625uS)
x4
x4
1 01
4bank
2/3
80
08
04
0C
757.5ns
A0
54
60
02
80
04
04
8F
04
06
19
20
21
22
23
24
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00
26
27
28
29
30
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Row Active to Row Active Min.
CS# Latency
Write Latency
SDRAM Module Attributes
Cycle time for CL=2
tAC for CL=2
Precharge to Active Minimum
RAS to CAS Delay Min
Active to Precharge Min
0
0
10ns
10ns
13ns
6ns
6ns
7ns 70
N/A 00
22.5ns 17
20ns 14
15ns 0F
20ns 14
22.5ns 17
20ns 14
45ns 2D
50ns 32
01
01
1F
0E
A0
A0
D0
60
60
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
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Page 54
Preliminary Spec.
Serial Presence Detect Table II
4D48363453373241574A412D362020202020
-6,-7
-8
-6
-7,-8-6-7,-8
-6
-7,-8
-6
-7,-8
-6
-7,-8
4D48363453373241574A412D372020202020
4D48363453373241574A412D382020202020
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
31 Density of each bank on module 256MByte 40
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34 Data signal input setup time
35
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71
72 Manufacturing location
Data signal input hold time
Superset Information (may be used in future)
Manufactures Jedec ID code per JEP-108E
1.5ns 15
2ns 20
0.8ns 08
1ns 10
2ns
0.8ns 08
1ns 10
option 00
JEDEC2
rev 1.2A 12
Check sum for -6 F0
Check sum for -7 61
Check sum for -8 A1
MITSUBISHI 1CFFFFFFFFFFFFFF
Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
MH64S72AWJA-6
151.5ns
20
02
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yyww
95-98 Assembly Serial Number serial number ssssssss
99-125
126 Intetl specification frequency 100MHz
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
Manufacture Specific Data
MH64S72AWJA-7
MH64S72AWJA-8
option
00
64
8FCL=2/3,AP,CK0
8DCL=3,AP,CK0
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
17/Mar. /2000
54
Page 55
Preliminary Spec.
Some contents are subject to change without notice.
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
3
8.89
11.43
3
24.495
6.35
36.83
42.18
6.35
1.27
54.61
127.35
38.1
3.9Max
MIT-DS-372-0.2
MITSUBISHI
ELECTRIC
1.27
17/Mar. /2000
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Preliminary Spec.
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
1.These materials are intended as a reference to assist our customers in the selection of the
a device or system that is used under circumstances in which human life is potentially at stake.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72AWJA -6,-7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonÂflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
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programs and algorithms represents information on products at the time of publication of
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due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
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loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
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(http://www.mitsubishichips.com).
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Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
MIT-DS-372-0.2
MITSUBISHI
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17/Mar. /2000
56
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