Page 1
DEVICES INCORPORATED
LPR520
4 x 16-bit Multilevel Pipeline Register
LPR520
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
FEATURES DESCRIPTION
❑❑
❑ Four 16-bit Registers
❑❑
❑❑
❑ Implements Double 2-Stage
❑❑
Pipeline or Single 4-Stage Pipeline
Register
❑❑
❑ Hold, Shift, and Load Instructions
❑❑
❑❑
❑ Separate Data In and Data Out Pins
❑❑
❑❑
❑ High-Speed, Low Power CMOS
❑❑
Technology
❑❑
❑ Three-State Outputs
❑❑
❑❑
❑ 44-pin PLCC, J-Lead
❑❑
The LPR520 is functionally compatible with the L29C520 but have 16-bit
inputs and outputs. The LPR520 is
implemented in low power CMOS.
The LPR520 contains four registers
which can be configured as two
independent, 2-level pipelines or as
one 4-level pipeline.
The Instruction pins, I1-0, control the
loading of the registers. The registers
may be configured as a four-stage
delay line, with data loaded into R1
and shifted sequentially through R2,
R3, and R4. Also, data may be loaded
from the inputs into either R1 or R3
with only R2 or R4 shifting. Finally,
I1-0 may be set to prevent any register
from changing.
The S1-0 select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
LPR520 BLOCK DIAGRAM
16
D15-0
I1-0
CLK
REGISTER 1
REGISTER 3
2
REGISTER 2
REGISTER 4
MUX
REG 1
REG 2
REG 3
REG 4
MUX
TABLE 1.
LPR520 INSTRUCTION TABLE
I1 I0 Description
LLD➞R1 R1➞R2 R2➞R3 R3➞R4
L H HOLD HOLD D➞R3 R3➞R4
16
15-0
Y
OE
2
S1-0
HLD➞R1 R1➞R2 HOLD HOLD
H H ALL REGISTERS ON HOLD
TABLE 2. OUTPUT SELECT
S1 S0 Register Selected
L L Register 4
L H Register 3
H L Register 2
H H Register 1
Pipeline Registers
1
08/02/2000–LDS.P520-C
Page 2
DEVICES INCORPORATED
LPR520
4 x 16-bit Multilevel Pipeline Register
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V
Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Over Operating Conditions (Note 4)
Symbol Parameter Test Condition Min Typ Max Unit
VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V
VIH Input High Voltage 2.0 VCC V
V IL Input Low Voltage (Note 3) 0.0 0.8 V
IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA
IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA
ICC1 VCC Current, Dynamic (Notes 5, 6) 10 40 mA
ICC2 VCC Current, Quiescent (Note 7) 1.0 mA
Pipeline Registers
2
08/02/2000–LDS.P520-C
Page 3
DEVICES INCORPORATED
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4
SWITCHING CHARACTERISTICS
LPR520
4 x 16-bit Multilevel Pipeline Register
COMMERCIAL OPERATING RANGE (0°C to +70°C)
Symbol Parameter Min Max Min Max Min Max
tPD Clock to Output Delay 25 22 15
tSEL Select to Output Delay 25 20 15
tPW Clock Pulse Width 10 10 8
tSI Instruction Setup Time 13 10 6
tHI Instruction Hold Time 3 3 1
tSD Data Setup Time 13 10 6
tHD Data Hold Time 3 3 1
tENA Three-State Output Enable Delay (Note 11) 25 21 15
tDIS Three-State Output Disable Delay (Note 11) 25 15 12
MILITARY OPERATING RANGE (–55°C to +125°C)
Symbol Parameter Min Max Min Max Min Max
tPD Clock to Output Delay 30 24 18
tSEL Select to Output Delay 30 22 18
tPW Clock Pulse Width 15 10 9
tSI Instruction Setup Time 15 10 8
tHI Instruction Hold Time 5 3 2
tSD Data Setup Time 15 10 8
tHD Data Hold Time 5 3 2
tENA Three-State Output Enable Delay (Note 11) 25 22 16
tDIS Three-State Output Disable Delay (Note 11) 20 16 13
Notes 9, 10 (ns)
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Notes 9, 10 (ns)
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25
30
LPR520–
*
22 15*
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LPR520–
*
24
*
18
*
SWITCHING WAVEFORMS
I
1-0
t
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*DISCONTINUED SPEED GRADE
D
15-0
CLK
S
1-0
OE
Y
15-0
SI
t
SD
t
HI
t
SEL
t
HD
t
PW
t
PD
t
DIS
3
t
PW
HIGH IMPEDANCE
t
ENA
Pipeline Registers
08/02/2000–LDS.P520-C
Page 4
DEVICES INCORPORATED
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V 1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
VOL*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with IOH = –10mA and IOL = 10mA
Measured V
OH
with IOH = –10mA and IOL = 10mA
NOTES
LPR520
4 x 16-bit Multilevel Pipeline Register
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. Input levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
FIGURE B. THRESHOLD LEVELS
4. Actual test conditions may vary from
those designated but operation is guaranteed as specified.
5. Supply current for a given application can be accurately approximated by:
2
NCV F
where
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
4
Pipeline Registers
08/02/2000–LDS.P520-C
Page 5
DEVICES INCORPORATED
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7
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44
Top
View
1 4243
18 23 24 25 26 27
406
28
2534
19 20 21 22
NC
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
NC
NC
D2D1D0I1I0VCCS0S1Y0Y
1
D13D14D
15
CLK
GND
OE
Y
15Y14Y13Y12
NC
LPR520 — ORDERING INFORMATION
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40-pin — 0.6" wide
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1
I
0
2
I
1
3
D
0
4
D
1
5
D
2
6
D
3
7
D
4
8
D
5
9
D
6
10
D
7
11
D
8
12
D
9
13
D
10
14
D
11
15
D
12
16
D
13
17
D
14
18
D
15
19
CLK
20
GND
Discontinued Package
Plastic DIP
Speed
(P3)
0°C to +70°C — COMMERCIAL SCREENING
22 ns
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
40
V
39
S
38
S
37
Y
36
Y
35
Y
34
Y
33
Y
32
Y
31
Y
30
Y
29
Y
28
Y
27
Y
26
Y
25
Y
24
Y
23
Y
22
Y
21
OE
CC
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ceramic DIP
(C11)
4 x 16-bit Multilevel Pipeline Register
44-pin
Plastic J-Lead Chip Carrier
(J1)
LPR520JC22
Pipeline Registers
5
08/02/2000–LDS.P520-C
LPR520
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