Page 1
LAN91C111
10/100 Non-PCI Ethernet Single
Chip MAC + PHY
Datasheet
Product Features
Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and
Transmit FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM
Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer
Memory)
Early TX, Early RX Functions
Built-in Transparent Arbitration for Slave
Sequential Access Architecture
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
3.3V Operation with 5V Tolerant IO Buffers (See
Pin List Description for Additional Details)
Single 25 MHz Reference Clock for Both PHY
and MAC
External 25Mhz-output pin for an external PHY
supporting PHYs physical media.
Low Power CMOS Design
Supports Multiple Embedded Processor Host
Interfaces
− ARM
− SH
− Power PC
− Coldfire
− 680X0, 683XX
− MIPS R3000
3.3V MII (Media Independent Interface) MAC-
PHY Interface Running at Nibble Rate
MII Management Serial Interface
128 Pin QFP Package
128 Pin TQFP Package, 1.0 mm height
Industrial Temperature Range from -40°C to
85°C (LAN91C111i only)
Network Interface
Fully Integrated IEEE 802.3/802.3u-100Base-TX
/ 10Base-T Physical Layer
Auto Negotiation: 10/100, Full / Half Duplex
On Chip Wave Shaping - No External Filters
Required
Adaptive Equalizer
Baseline Wander Correction
LED Outputs (User selectable – Up to 2 LED
functions at one time)
− Link
− Activity
− Full Duplex
− 10/100
− Transmit
− Receive
− User Programmable
SMSC DS – LAN91C111 Rev. B Page 1 Rev. 09/17/2002
PRELIMINARY
Page 2
10/100 Non-PCI Ethernet Single Chip MAC + PHY
ORDERING INFORMATION
Order Numbers:
LAN91C111-NC
LAN91C111I-NC (Industrial Temperature)
for 128 Pin QFP Packages
LAN91C111-NE (1.0mm height)
LAN91C111I-NE (Industrial Temperature)
for 128 Pin TQFP Packages
© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2002
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the
trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications;
consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is
believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product
descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The
provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR
NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS – LAN91C111 Rev. B Page 2 Rev. 09/17/2002
Page 3
10/100 Non-PCI Ethernet Single Chip MAC + PHY
TABLE OF CONTENTS
Chapter 1 General Description ........................................................................................................... 6
Chapter 2 Pin Configurations ............................................................................................................. 7
Chapter 3 Block Diagrams ..................................................................................................................9
Chapter 4 Signal Descriptions .......................................................................................................... 12
Chapter 5 Description of Pin Functions ........................................................................................... 13
Chapter 6 Signal Description Parameters........................................................................................ 18
6.1 Buffer Types .................................................................................................................................... 18
Chapter 7 Functional Description..................................................................................................... 19
7.1 Clock Generator Block .................................................................................................................... 19
7.2 CSMA/CD Block .............................................................................................................................. 19
7.2.1 DMA Block............................................................................................................................................19
7.2.2 Arbiter Block .........................................................................................................................................19
7.3 MMU Block ...................................................................................................................................... 20
7.4 BIU Block......................................................................................................................................... 20
7.5 MAC-PHY Interface......................................................................................................................... 20
7.5.1 Management Data Software Implementation........................................................................................21
7.5.2 Management Data Timing ....................................................................................................................21
7.5.3 MI Serial Port Frame Structure .............................................................................................................21
7.5.4 MII Packet Data Communication with External PHY.............................................................................23
7.6 Serial EEPROM Interface................................................................................................................ 24
7.7 Internal Physical Layer .................................................................................................................... 24
7.7.1 MII Disable............................................................................................................................................26
7.7.2 Encoder ................................................................................................................................................26
7.7.3 Decoder ................................................................................................................................................26
7.7.4 Clock and Data Recovery .....................................................................................................................27
7.7.5 Scrambler .............................................................................................................................................28
7.7.6 Descrambler .........................................................................................................................................28
7.7.7 Twisted Pair Transmitter.......................................................................................................................29
7.7.8 Twisted Pair Receiver...........................................................................................................................32
7.7.9 Collision ................................................................................................................................................34
7.7.10 Start of Packet...................................................................................................................................34
7.7.11 End of Packet....................................................................................................................................35
7.7.12 Link Integrity & Autonegotiation.........................................................................................................36
7.7.13 Jabber ...............................................................................................................................................39
7.7.14 Receive Polarity Correction...............................................................................................................39
7.7.15 Full Duplex Mode ..............................................................................................................................40
7.7.16 Loopback...........................................................................................................................................40
7.7.17 PHY Powerdown ...............................................................................................................................41
7.7.18 PHY Interrupt ....................................................................................................................................41
7.8 Reset ............................................................................................................................................... 41
Chapter 8 MAC Data Structures and Registers.............................................................................. 42
8.1 Frame Format In Buffer Memory..................................................................................................... 42
8.2 Receive Frame Status..................................................................................................................... 43
8.3 I/O Space......................................................................................................................................... 44
8.4 Bank Select Register....................................................................................................................... 45
8.5 Bank 0 - Transmit Control Register................................................................................................. 46
8.6 Bank 0 - EPH Status Register......................................................................................................... 47
8.7 Bank 0 - Receive Control Register.................................................................................................. 48
8.8 Bank 0 - Counter Register............................................................................................................... 49
SMSC DS – LAN91C111 Rev. B Page 3 Rev. 09/17/2002
Page 4
10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.9 Bank 0 - Memory Information Register ...........................................................................................49
8.10 Bank 0 - Receive/Phy Control Register ....................................................................................... 50
8.11 Bank 1 - Configuration Register ................................................................................................... 52
8.12 Bank 1 - Base Address Register..................................................................................................53
8.13 Bank 1 - Individual Address Registers ......................................................................................... 53
8.14 Bank 1 - General Purpose Register ............................................................................................. 54
8.15 Bank 1 - Control Register............................................................................................................. 54
8.16 Bank 2 - MMU Command Register .............................................................................................. 55
8.17 Bank 2 - Packet Number Register ............................................................................................... 57
8.18 Bank 2 - FIFO Ports Register....................................................................................................... 58
8.19 Bank 2 - Pointer Register ............................................................................................................. 59
8.20 Bank 2 - Data Register................................................................................................................. 60
8.21 Bank 2 - Interrupt Status Registers.............................................................................................. 60
8.22 Bank 3 - Multicast Table Registers ..............................................................................................64
8.23 Bank 3 - Management Interface...................................................................................................65
8.24 Bank 3 - Revision Register .......................................................................................................... 65
8.25 Bank 3 - Early RCV Register ....................................................................................................... 66
8.26 Bank 7 - External Registers ......................................................................................................... 66
Chapter 9 PHY MII Registers........................................................................................................... 67
9.1 Register 0. Control Register............................................................................................................ 71
9.2 Register 1. Status Register .............................................................................................................72
9.3 Register 2&3. PHY Identifier Register............................................................................................. 73
9.4 Register 4. Auto-Negotiation Advertisement Register .................................................................... 73
9.5 Register 5. Auto-Negotiation Remote End Capability Register ...................................................... 75
9.6 Register 16. Configuration 1-- Structure and Bit Definition............................................................. 75
9.7 Register 17. Configuration 2 - Structure and Bit Definition ............................................................. 76
9.8 Register 18. Status Output - Structure and Bit Definition................................................................ 76
9.9 Register 19. Mask - Structure and Bit Definition ............................................................................ 77
9.10 Register 20. Reserved - Structure and Bit Definition .................................................................. 78
Chapter 10 Software Driver and Hardware Sequence Flow......................................................... 79
10.1 Software Driver and Hardware Sequence Flow for Power Management .................................... 79
10.2 Typical Flow of Events for Transmit (Auto Release = 0) .............................................................80
10.3 Typical Flow of Events for Transmit (Auto Release = 1) .............................................................82
10.4 Typical Flow of Event For Receive .............................................................................................. 83
Chapter 11 Board Setup Information ............................................................................................. 91
Chapter 12 Application Considerations.......................................................................................... 94
Chapter 13 Operational Description ............................................................................................. 101
13.1 Maximum Guaranteed Ratings*................................................................................................. 101
13.2 DC Electrical Characteristics ..................................................................................................... 101
13.3 Twisted Pair Characteristics, Transmit ...................................................................................... 104
13.4 Twisted Pair Characteristics, Receive ....................................................................................... 105
Chapter 14 Timing Diagrams ........................................................................................................ 107
Chapter 15 LAN91C111 Revisions................................................................................................ 126
LIST OF FIGURES
FIGURE 1 - PIN CONFIGURATION – LAN91C111-FEAST 128 PIN TQFP................................................................7
FIGURE 2 - PIN CONFIGURATION – LAN91C111-FEAST 128 PIN QFP ..................................................................8
FIGURE 3 - BASIC FUNCTIONAL BLOCK DIAGRAM ................................................................................................9
FIGURE 4 - BLOCK DIAGRAM..................................................................................................................................10
FIGURE 5 - LAN91C111 PHYSICAL LAYER TO INTERNAL MAC BLOCK DIAGRAM ............................................11
Rev. 09/17/2002 Page 4 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 5
10/100 Non-PCI Ethernet Single Chip MAC + PHY
FIGURE 6 - MI SERIAL PORT FRAME TIMING DIAGRAM ......................................................................................22
FIGURE 7 - MII FRAME FORMAT & MII NIBBLE ORDER........................................................................................23
FIGURE 8 - TX/10BT FRAME FORMAT....................................................................................................................25
FIGURE 9 - TP OUTPUT VOLTAGE TEMPLATE-10 MBPS .....................................................................................30
FIGURE 10 - TP INPUT VOLTAGE TEMPLATE-10MBPS ........................................................................................33
FIGURE 11 - SOI OUTPUT VOLTAGE TEMPLATE - 10MBPS ................................................................................36
FIGURE 12 - LINK PULSE OUTPUT VOLTAGE TEMPLATE - NLP, FLP ................................................................37
FIGURE 13 - NLP VS. FLP LINK PULSE ..................................................................................................................38
FIGURE 14 - DATA FRAME FORMAT ......................................................................................................................42
FIGURE 15 - INTERRUPT STRUCTURE..................................................................................................................63
FIGURE 16 - INTERRUPT SERVICE ROUTINE .......................................................................................................84
FIGURE 17 - RX INTR ...............................................................................................................................................85
FIGURE 18 - TX INTR ...............................................................................................................................................86
FIGURE 19 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED) ...............................................87
FIGURE 20 - DRIVE SEND AND ALLOCATE ROUTINES........................................................................................88
FIGURE 21 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU ........................................................90
FIGURE 22 - 64 X 16 SERIAL EEPROM MAP ..........................................................................................................93
FIGURE 23 - LAN91C111 ON VL BUS......................................................................................................................96
FIGURE 24 - LAN91C111 ON ISA BUS ....................................................................................................................98
FIGURE 25 - LAN91C111 ON EISA BUS ................................................................................................................100
FIGURE 26 - ASYNCHRONOUS CYCLE - nADS=0 ...............................................................................................107
FIGURE 27 - ASYNCHRONOUS CYCLE - USING nADS .......................................................................................108
FIGURE 28 - ASYNCHRONOUS CYCLE - nADS=0 ...............................................................................................109
FIGURE 29 - ASYNCHRONOUS READY ...............................................................................................................110
FIGURE 30 - BURST WRITE CYCLES - nVLBUS=1 ..............................................................................................111
FIGURE 31 - BURST READ CYCLES - nVLBUS=1 ................................................................................................112
FIGURE 32 - ADDRESS LATCHING FOR ALL MODES .........................................................................................113
FIGURE 33 - SYNCHRONOUS WRITE CYCLE - nVLBUS=0.................................................................................114
FIGURE 34 - SYNCHRONOUS READ CYCLE - nVLBUS=0 ..................................................................................115
FIGURE 35 - MII TIMING.........................................................................................................................................116
FIGURE 36 - TRANSMIT TIMING ...........................................................................................................................117
FIGURE 37 - RECEIVE TIMING, END OF PACKET - 10 MBPS .............................................................................117
FIGURE 38 - COLLISION TIMING, RECEIVE .........................................................................................................118
FIGURE 39 - COLLSION TIMING, TRANSMIT .......................................................................................................119
FIGURE 40 - JAM TIMING.......................................................................................................................................120
FIGURE 41 - LINK PULSE TIMING .........................................................................................................................122
FIGURE 42 - FLP LINK PULSE TIMING..................................................................................................................123
FIGURE 43 - 128 PIN TQFP, 14X14X1.0 BODY ................................................................................................124
FIGURE 44 - SMSC 128 PIN QFP PACKAGE OUTLINE, 3.9 MM FOOTPRINT ....................................................125
LIST OF TABLES
Table 1 - LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) ...............................................12
Table 2 - 4B/5B Symbol Mapping...............................................................................................................................27
Table 3 - Transmit Level Adjust..................................................................................................................................31
Table 4 - Internal I/O Space Mapping ........................................................................................................................45
Table 5 - MII Serial Frame Structure ..........................................................................................................................68
Table 6 - MII Serial Port Register MAP ......................................................................................................................70
Table 7 - Typical Flow Of Events For Placing Device In Low Power Mode................................................................79
Table 8 - Flow Of Events For Restoring Device In Normal Power Mode....................................................................80
Table 9 - VL Local Bus Signal Connections ...............................................................................................................94
Table 10 - High-End ISA or Non-Burst EISA Machines Signal Connectors................................................................97
Table 11 - EISA 32 Bit Slave Signal Connections ......................................................................................................98
Table 12 – Transmit Timing Characteristics .............................................................................................................116
Table 13 – Receive Timing Characteristics ..............................................................................................................117
Table 14 – Collision and Jam Timing Characteristics...............................................................................................118
Table 15 – Link Pulse Timing Characteristics ..........................................................................................................121
SMSC DS – LAN91C111 Rev. B Page 5 Rev. 09/17/2002
Page 6
Chapter 1 General Description
The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet
connectivity solutions for embedded applications. For this third generation of products, flexibility and
integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that
implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also
minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded
applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive
operations.
The SMSC LAN91C111 is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU (Memory Management Unit)
architecture and a 32-bit wide internal data path. This I/O mapped architecture can sustain back-to-back
frame transmission and reception for superior data throughput and optimal performance. It also
dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and
relieving the host CPU from performing these housekeeping functions.
The SMSC 91C111 provides a flexible slave interface for easy connectivity with industry-standard buses.
The Bus Interface Unit (BIU) can handle synchronous as well as asynchronous transfers, with different
signals being used for each one. Asynchronous bus support for ISA is supported even though ISA cannot
sustain 100 Mbps traffic. Fast Ethernet data rates are attainable for ISA-based nodes on the basis of the
aggregate traffic benefits.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Two different interfaces are supported on the network side. The first Interface is a standard Magnetics
transmit/receive pair interfacing to 10/100Base-T utilizing the internal physical layer block. The second interface
follows the MII (Media Independent Interface) specification standard, consisting of 4 bit wide data transfers at
the nibble rate. This interface is applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks. Three
of the LAN91C111’s pins are used to interface to the two-line MII serial management protocol.
The SMSC LAN91C111 integrates IEEE 802.3 Physical Layer for twisted pair Ethernet applications. The
PHY can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation.
The Analog PHY block consists of a 4B5B/Manchester encoder/decoder, scrambler/de-scrambler,
transmitter with wave shaping and output driver, twisted pair receiver with on chip equalizer and baseline
wander correction, clock and data recovery, Auto-Negotiation, controller interface (MII), and serial port
(MI). Internal output wave shaping circuitry and on-chip filters eliminate the need for external filters
normally required in 100Base-TX and 10Base-T applications.
The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation
with the on-chip Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for embedded
application desiring Ethernet connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards,
repeaters, switching hubs. The LAN91C111 operates from a single 3.3V supply. The inputs and outputs of
the host Interface are 5V tolerant and will directly interface to other 5V devices.
Rev. 09/17/2002 Page 6 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 7
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 2 Pin Configurations
Pin Configuration
XTAL2
XTAL1
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3
VDD
CRS100
RX25
GND
TXD0
TXD1
TXD2
TXD3
COL100
TXEN100
VDD
TX25
GNDD0D1D2D3
GNDD4D5D6D7
VDD
nBE3
VDD
nCSOUT
IOS0
IOS1
IOS2
ENEEP
EEDO
EEDI
EESK
EECS
AVDD
RBIAS
AGND
TPO+
TPO-
AVDD
TPI+
TPI-
AGND
nLNK
LBK
nLEDA
nLEDB
GND
MDI
MDO
MCLK
nCNTRL
INTR0
RESET
nRD
nWR
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33343536373839404142434445464748495051525354555657585960616263
LAN91C111-
FEAST
TM
128 PIN TQFP
104
103
102
101
100
999897
96
nBE2
95
nBE1
94
nBE0
93
GND
92
A15
91
A14
90
A13
89
A12
88
A11
87
A10
86
A9
85
A8
84
A7
83
A6
82
A5
81
A4
80
A3
79
A2
78
A1
77
VDD
76
D8
75
D9
74
D10
73
D11
72
GND
71
D12
70
D13
69
D14
68
D15
67
GND
66
D16
65
D17
64
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
VDD
nDATACS
W/nR
nADS
nCYCLE
GND
ARDY
AEN
LCLK
nVLBUS
VDD
nSRDY
nLDEV
nRDYRTN
GND
X25OUT
GND
VDD
D18
FIGURE 1 - PIN CONFIGURATION – LAN91C111-FEAST 128 PIN TQFP
SMSC DS – LAN91C111 Rev. B Page 7 Rev. 09/17/2002
PRELIMINARY
Page 8
XTAL1
XTAL2
VDD
nCSOUT
IOS0
IOS1
IOS2
ENEEP
EEDO
EEDI
EESK
EECS
AVDD
RBIAS
AGND
TPO+
TPO-
AVDD
TPI+
TPI-
AGND
nLNK
LBK
nLEDA
nLEDB
GND
MDI
MDO
MCLK
nCNTRL
INTR0
RESET
nRD
nWR
VDD
nDATACS
nCYCLE
W/nR
Pin Configuration
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3
VDD
CRS100
RX25
GND
TXD0
TXD1
TXD2
TXD3
COL100
TXEN100
VDD
TX25
GNDD0D1D2D3
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
LAN91C111-
FEAST
TM
128 PIN QFP
109
10/100 Non-PCI Ethernet Single Chip MAC + PHY
GNDD4D5
108
107
106
105
104
103
102
D6
101
D7
100
VDD
99
nBE3
98
nBE2
97
nBE1
96
nBE0
95
GND
94
A15
93
A14
92
A13
91
A12
90
A11
89
A10
88
A9
87
A8
86
A7
85
A6
84
A5
83
A4
82
A3
81
A2
80
A1
79
VDD
78
D8
77
D9
76
D10
75
D11
74
GND
73
D12
72
D13
71
D14
70
D15
69
GND
68
D16
67
D17
66
D18
65
D19
64
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
nADS
ARDY
GND
nVLBUS
AEN
LCLK
nSRDY
VDD
nLDEV
X25OUT
nRDYRTN
GND
GND
VDD
FIGURE 2 - PIN CONFIGURATION – LAN91C111-FEAST 128 PIN QFP
Rev. 09/17/2002 Page 8 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 9
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 3 Block Diagrams
The diagram shown in FIGURE 3 - BASIC FUNCTIONAL BLOCK DIAGRAM, describes the device basic
functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal
Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions.
The optional Serial EEPROM is used to store information relating to default IO offset parameters as well as
which of the Interrupt line are used by the host.
LAN91C111
PHY
Core
Transformer
RJ45
ISA,Embedded
Processor
Ethernet
MAC
Internal IEEE 802.3 MII (Media
Independent Interface)
Host System
TX/RX Buffer (8K)
Serial
EEProm
(Optional)
Minimal LAN91C111
Configuration
FIGURE 3 - BASIC FUNCTIONAL BLOCK DIAGRAM
SMSC DS – LAN91C111 Rev. B Page 9 Rev. 09/17/2002
PRELIMINARY
Page 10
10/100 Non-PCI Ethernet Single Chip MAC + PHY
EEPROM
INTERFACE
Control
MII
Control
Address
Data
8-32 bit
Bus
Interface
Unit
Control
Control
WR
FIFO
RD
FIFO
Control
Arbiter
MMU
8K Byte
Dynamically
Allocated
SRAM
TX/RX
FIFO
Pointer
32-bit Data
32-bit Data
DMA
Control
TX Data
RX Data
Ethernet
Protocol
Handler
(EPH)
Control
TPO
10/100
PHY
TXD[0-3]
TPI
RXD[0-3]
FIGURE 4 - BLOCK DIAGRAM
The diagram shown in FIGURE 4 describes the supported Host interfaces, which include ISA or Generic
Embedded. The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and
8 bit embedded RISC and ARM processors.
The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a
10/100 Ethernet Physical layer framer to the internal MAC.
Rev. 09/17/2002 Page 10 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 11
10/100 Non-PCI Ethernet Single Chip MAC + PHY
MII External
Signals
EECS
EESK
EEPROM
CONTROL
TXD[3:0]
TX_ER
TXEN100
TX25
EEDO
EEDI
S
A
B
I
R
X
T
-
E
B
A
S
0
0
1
T
E
R
T
I
S
M
A
N
R
T
I
T
W
C
H
D
E
5
B
B
4
D
R
O
E
N
E
C
E
R
A
M
B
L
R
S
C
L
M
O
N
E
C
0
B
A
1
S
A
N
R
T
S
3
T
D
R
E
T
-
S
E
T
T
I
M
R
R
N
E
T
C
U
R
C
E
O
U
S
C
K
L
O
C
E
N
G
L
)
P
L
(
E
R
P
L
E
T
L
I
F
+
-
R
+
O
P
T
-
P
O
T
MII
SERIAL
Manage
-ment
CSMA/CD
Power
Reset
On
MII
To MII External Signals
CRS100
COL100
RXD[3:0]
RX_ER
RX_DV
RX25
MDI
MCLK
MDO
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FIGURE 5 - LAN91C111 PHYSICAL LAYER TO INTERNAL MAC BLOCK DIAGRAM
SMSC DS – LAN91C111 Rev. B Page 11 Rev. 09/17/2002
PRELIMINARY
Page 12
Chapter 4 Signal Descriptions
Table 1 - LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package)
FUNCTION PIN SYMBOLS NUMBER OF PINS
System Address Bus A1-A15, AEN, nBE0-nBE3 20
System Data Bus D0-D31 32
System Control Bus RESET, nADS, LCLK, ARDY,
nRDYRTN, nSRDY, INTR0,
nLDEV, nRD, nWR, nDATACS,
nCYCLE, W/nR, nVLBUS
Serial EEPROM EEDI, EEDO, EECS, EESK,
ENEEP, IOS0-IOS2
LEDs nLEDA, nLEDB 2
PHY TPO+, TPO-, TPI+, TPI-, nLNK,
LBK, nCNTRL, RBIAS
Crystal Oscillator XTAL1, XTAL2 2
Power VDD, AVDD 10
Ground GND, AGND 12
Physical Interface (MII) TXEN100, CRS100, COL100,
RX_DV, RX_ER, TXD0-TXD3,
RXD0-RXD3, MDI, MDO,
MCLK, RX25, TX25
MISC nCSOUT, X25OUT 2
TOTAL 128
10/100 Non-PCI Ethernet Single Chip MAC + PHY
14
8
8
18
Rev. 09/17/2002 Page 12 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 5 Description of Pin Functions
PIN NO.
TQFP QFP
81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C111 to
78-80 80-82 Address A1-A3 I** Input. Used by LAN91C111 for
41 43 Address
94-97 96-99 nByte Enable nBE0-
107-104,
102-99,
76-73, 7168, 66-63,
61-58, 5653, 51-48
30 32 Reset RESET IS** Input. When this pin is asserted
37 39 nAddress
35 37 nCycle nCYCLE I** Input. This active low signal is used
36 38 Write/
109-106,
104-101,
78-75,
73-70,
68-65,
63-60,
58-55,
53-50
NAME SYMBOL
AEN I** Input. Used as an address qualifier.
Enable
nBE3
Data Bus D0-D31 I/O24** Bidirectional. 32 bit data bus used to
nADS IS** Input. For systems that require
Strobe
W/nR IS** Input. Defines the direction of
nRead
BUFFER
TYPE
determine access to its registers.
internal register selection.
Address decoding is only enabled
when AEN is low.
I** Input. Used during LAN91C111
register accesses to determine the
width of the access and the
register(s) being accessed. nBE0nBE3 are ignored when nDATACS is
low (burst accesses) because 32 bit
transfers are assumed.
access the LAN91C111’s internal
registers. Data bus has weak
internal pullups. Supports direct
connection to the system bus without
external buffering. For 16 bit
systems, only D0-D15 are used.
high, the controller performs an
internal system (MAC & PHY) reset.
It programs all the registers to their
default value, the controller will read
the EEPROM device through the
EEPROM interface
input is not considered active unless
it is active for at least 100ns to filter
narrow glitches.
address latching, the rising edge of
nADS indicates the latching moment
for A1-A15 and AEN. All
LAN91C111 internal functions of A1A15, AEN are latched except for
nLDEV decoding.
to control LAN91C111 EISA burst
mode synchronous bus cycles.
synchronous cycles. Write cycles
when high, read cycles when low.
DESCRIPTION
(Note 5.1). This
SMSC DS – LAN91C111 Rev. B Page 13 Rev. 09/17/2002
PRELIMINARY
Page 14
10/100 Non-PCI Ethernet Single Chip MAC + PHY
PIN NO.
TQFP QFP
40 42 nVL Bus
42
38 40
43 45 nSynchronous
46 48 nReady
29 31 Interrupt INTR0 O24 Interrupt Output – Used to interrupt the
45 47 nLocal Device nLDEV O16 Output. This active low output is
44 Local Bus
NAME SYMBOL
nVLBUS I with
Access
LCLK I** Input. Used to interface synchronous
Clock
Asynchronous
Ready
Ready
Return
ARDY OD16 Open drain output. ARDY may be
nSRDY O16 Output. This output is used when
nRDYRTN I** Input. This input is used to complete
BUFFER
TYPE
pullup**
DESCRIPTION
Input. When low, the LAN91C111
synchronous bus interface is
configured for VL Bus accesses.
Otherwise, the LAN91C111 is
configured for EISA DMA burst
accesses. Does not affect the
asynchronous bus interface.
buses. Maximum frequency is 50
MHz. Limited to 8.33 MHz for EISA
DMA burst mode. This pin should be
tied high if it is in asynchronous mode.
used when interfacing asynchronous
buses to extend accesses. Its rising
(access completion) edge is controlled
by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus
clock. ARDY is negated during
Asynchronous cycle when one of the
following conditions occurs:
1) No_Wait Bit in the Configuration
Register is cleared.
2) Read FIFO contains less than 4
bytes when read.
3) Write FIFO is full when write.
interfacing synchronous buses and
nVLBUS=0 to extend accesses. This
signal remains normally inactive, and
its falling edge indicates completion.
This signal is synchronous to the bus
clock LCLK.
synchronous read cycles. In EISA
burst mode it is sampled on falling
LCLK edges, and synchronous cycles
are delayed until it is sampled high.
Host on a status event. Note: The
selection bits used to determined by
the value of INT SEL 1-0 bits in the
Configuration Register are no longer
required and have been set to
reserved in this revision of the FEAST
family of devices.
asserted when AEN is low and A4-A15
decode to the LAN91C111 address
programmed into the high byte of the
Base Address Register. nLDEV is a
combinatorial decode of unlatched
address and AEN signals.
Rev. 09/17/2002 Page 14 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 15
10/100 Non-PCI Ethernet Single Chip MAC + PHY
PIN NO.
TQFP QFP
31 33 nRead Strobe nRD IS** Input. Used in asynchronous bus
32 34 nWrite Strobe nWR IS** Input. Used in asynchronous bus
34 36 nData Path
9 11 EEPROM
10 12 EEPROM
7 9 EEPROM
8 10 EEPROM
3-5 5-7 I/O Base IOS0-
6 8 Enable
127, 128 1, 2 Crystal 1
1, 33, 44,
62, 77, 98,
110, 120
11, 16 13, 18 Analog Power AVDD +3.3V Analog power supply pins.
24, 39, 52,
57, 67, 72,
93, 103,
108, 117
13, 19 15, 21 Analog
21 23 Loopback LBK O4 Output. Active when LOOP bit is set
3, 35, 46,
64, 79,
100, 112,
122
26, 41,
54, 59,
69, 74,
95, 105,
110, 119
NAME SYMBOL
nDATACS I with
Chip Select
EESK O4
Clock
EECS O4 Output. Serial EEPROM chip select.
Select
EEDO O4 Output. Connected to the DI input of
Data Out
EEDI I with
Data In
IOS2
ENEEP I with
EEPROM
XTAL1
Crystal 2
Power VDD +3.3V Power supply pins.
Ground GND Ground pins.
Ground
XTAL2
AGND Analog Ground pins
BUFFER
TYPE
interfaces.
interfaces.
Input. When nDATACS is low, the
pullup**
pulldown
**
I with
pullup**
pullup**
Iclk** An external 25 MHz crystal is
Data Path can be accessed regardless
of the values of AEN, A1-A15 and the
content of the BANK SELECT
Register. nDATACS provides an
interface for bursting to and from the
LAN91C111 32 bits at a time.
Output. 4 µsec clock used to shift data
in and out of the serial EEPROM.
Used for selection and command
framing of the serial EEPROM.
the serial EEPROM.
Input. Connected to the DO output of
the serial EEPROM.
Input. External switches can be
connected to these lines to select
between predefined EEPROM
configurations.
Input. Enables (when high or open)
LAN91C111 accesses to the serial
EEPROM. Must be grounded if no
EEPROM is connected to the
LAN91C111.
connected across these pins. If a TTL
clock is supplied instead, it should be
connected to XTAL1 and XTAL2
should be left open. XTAL1 is the 5V
tolerant input of the internal amplifier
and XTAL2 is the output of the internal
amplifier.
(TCR bit 1).
DESCRIPTION
SMSC DS – LAN91C111 Rev. B Page 15 Rev. 09/17/2002
PRELIMINARY
Page 16
10/100 Non-PCI Ethernet Single Chip MAC + PHY
PIN NO.
TQFP QFP
20 22 nLink Status nLNK I with
28 30 nCNTRL nCNTRL O12 General Purpose Control Pin
47 49 X25out X25out O12 25Mhz Output to external PHY
111 113 Transmit
119 121 Carrier Sense
125 127 Receive Data
112 114 Collision
113-116 115-118 Transmit Data TXD3-
109 111 Transmit
118 120 Receive Clock RX25 I with
121-124 123-126 Receive Data RXD3-
25 27 Management
NAME SYMBOL
TXEN100 O12 Output to MII PHY. Envelope to 100
Enable 100
Mbps
CRS100 I with
100 Mbps
RX_DV I with
Valid
COL100 I with
Detect 100
Mbps
TXD0
TX25 I with
Clock
RXD0
MDI I with
Data Input
BUFFER
TYPE
Input. General-purpose input port
pullup
pulldown
pulldown
pulldown
O12 Outputs. Transmit Data nibble to MII
pullup
pullup
I with
pullup
pulldown
used to convey LINK status (EPHSR
bit 14).
Mbps transmission.
Input from MII PHY. Envelope of
packet reception used for deferral and
backoff purposes.
Input from MII PHY. Envelope of data
valid reception. Used for receive data
framing.
Input from MII PHY. Collision
detection input.
PHY.
Input. Transmit clock input from MII.
Nibble rate clock (25MHz for 100Mbps
& 2.5MHz for 10Mbps).
Input. Receive clock input from MII
PHY. Nibble rate clock. (25MHz for
100Mbps & 2.5MHz for 10Mbps).
Inputs. Received Data nibble from MII
PHY.
MII management data input.
DESCRIPTION
26 28 Management
Data Output
27 29 Management
Clock
126 128 Receive Error RX_ER I with
2 4 nChip Select
Output
12 14 External
Resistor
Rev. 09/17/2002 Page 16 SMSC DS – LAN91C111 Rev. B
MDO O4 MII management data output.
MCLK O4 MII management clock.
Input. Indicates a code error detected
pulldown
nCSOUT O4 Output. Chip Select provided for
RBIAS NA Transmit Current Set. An external
by PHY. Used by the LAN91C111 to
discard the packet being received.
The error indication reported for this
event is the same as a bad CRC
(Receive Status Word bit 13).
mapping of PHY functions into
LAN91C111 decoded space. Active on
accesses to LAN91C111’s eight lower
addresses when the BANK
SELECTED is 7.
resistor connected between this pin
and GND will set the output current for
the TP transmit outputs
PRELIMINARY
Page 17
10/100 Non-PCI Ethernet Single Chip MAC + PHY
PIN NO.
NAME SYMBOL
TQFP QFP
14 16 TPO+ O/I Twisted Pair Transmit Output, Positive.
15 17 TPO- O/I Twisted Pair Transmit Output,
17 19 TPI+ I/O Twisted Pair Receive Input, Positive
18 20 TPI- I/O Twisted Pair Receive Input, Negative.
22 24 nLEDA OD24 PHY LED Output
23 25 nLEDB OD24 PHY LED Output
Note 5.1 If the EEPROM is enabled.
BUFFER
TYPE
DESCRIPTION
Negative
SMSC DS – LAN91C111 Rev. B Page 17 Rev. 09/17/2002
PRELIMINARY
Page 18
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 6 Signal Description Parameters
This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in
functional groups according to their associated function.
The ‘n’ symbol at the beginning of a signal name indicates that it is an active low signal. When ‘n’ is not
present before the signal name, it indicates an active high signal.
The term “assert” or “assertion” indicates that a signal is active; independent of whether that level is
represented by a high or low voltage. The term negates or negation indicates that a signal is inactive.
The term High-Z means tri-stated.
The term Undefined means the signal could be high, low, tri-stated, or in some in-between level.
6.1 Buffer Types
O4 Output buffer with 2mA source and 4mA sink
O12 Output buffer with 6mA source and 12mA sink
O16 Output buffer with 8mA source and 16mA sink
O24 Output buffer with 12mA source and 24mA sink
OD16 Open drain buffer with 16mA sink
OD24 Open drain buffer with 24mA sink
I/O4 Bidirectional buffer with 2mA source and 4mA sink
I/O24 Bidirectional buffer with 12mA source and 24mA sink
I/OD Bidirectional Open drain buffer with 4mA sink
I Input buffer
IS Input buffer with Schmitt Trigger Hysteresis
Iclk Clock input buffer
I/O Differential Input
O/I Differential Output
** 5V tolerant. Input pins are able to accept 5V signals
DC levels and conditions defined in the DC Electrical Characteristics section
Rev. 09/17/2002 Page 18 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 19
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 7 Functional Description
7.1 Clock Generator Block
1) The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal.
2) TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a
10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
3) RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the
receive state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
4) LCLK - Bus clock - Used by the BIU for synchronous accesses. Maximum frequency is 50 MHz for VL
BUS mode, and 8.33 MHz for EISA slave DMA.
7.2 CSMA/CD Block
This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out
of the block consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of
the FIFO stores 32 bits to exploit the 32 bit data path into memory, but the FIFOs themselves are 16 bit
wide. The Control Path consists of a set of registers interfaced to the CPU via the BIU.
7.2.1 DMA Block
This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing received
data. It interfaces the CSMA/CD Transmit and Receive FIFOs on one side and the Arbiter block on the
other. To increase the bandwidth into memory, a 50 MHz clock is used by the DMA block, and the data
path is 32 bits wide.
For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the Receive FIFO
every 160ns. The DMA will read the FIFO and accumulate two words on the output port to request a memory
cycle from the Arbiter every 320ns.
The DMA machine is able to support full duplex operation. Independent receive and transmit counters are used.
Transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed.
7.2.2 Arbiter Block
The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU
requests represent pipelined CPU accesses to the Data Register, while DMA requests represent
CSMA/CD data movement.
Internal SRAM read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the
appropriate lanes as a function of the address.
The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These
FIFOs can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not
Ready' whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO.
SMSC DS – LAN91C111 Rev. B Page 19 Rev. 09/17/2002
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Page 20
7.3 MMU Block
The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It
also determines the value of the transmit and receive interrupts as a function of the queues. The page size
is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048 byte units.
7.4 BIU Block
The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used
for each one. Transparent latches are added on the address path using rising nADS for latching.
When working with an asynchronous bus like ISA, the read and write operations are controlled by the
edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The
leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is
controlled by the internal LAN91C111 clock and, therefore, asynchronous to the bus.
In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations.
Completion of the cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and
synchronous to the bus.
Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting nDATACS,
external DMA type of devices will bypass the BIU address decoders and can sequentially access memory
with no CPU intervention. nDATACS accesses can be used in the EISA DMA burst mode (nVLBUS=1) or
in asynchronous cycles. These cycles MUST be 32 bit cycles. Please refer to the corresponding timing
diagrams for details on these cycles.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
The BIU is implemented using the following principles:
a) Address decoding is based on the values of A15-A4 and AEN.
b) Address latching is performed by using transparent latches that are transparent when nADS=0 and
nRD=1, nWR=1 and latch on nADS rising edge.
c) Byte, word and doubleword accesses to all registers and Data Path are supported except a
doubleword write to offset Ch will only write the BANK SELECT REGISTER (offset 0x0Fh).
d) No bus byte swapping is implemented (no eight bit mode).
e) Word swapping as a function of A1 is implemented for 16 bit bus support.
f) The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the
leading edge of the strobe. The ARDY trailing edge is controlled by CLK.
g) The VLBUS synchronous interface uses LCLK, nADS, and W/nR as defined in the VESA specification
as well as nCYCLE to control read and write operations and generate nSRDY.
h) EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA Slave
Mode "C" specification when nDATACS is driven by nDAK.
i) Synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously.
j) Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating the
nDATACS pin.
7.5 MAC-PHY Interface
The LAN91C111 integrates the IEEE 802.3 Physical Layer (PHY) and Media Access Control (MAC) into
the same silicon. The data path connection between the MAC and the internal PHY is provided by the
internal MII. The LAN91C111 also supports the EXT_PHY mode for the use of an external PHY, such as
HPNA. This mode isolates the internal PHY to allow interface with an external PHY through the MII pins.
To enter this mode, set EXT PHY bit to 1 in the Configuration Register.
Rev. 09/17/2002 Page 20 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
7.5.1 Management Data Software Implementation
The MII interface contains of a pair of signals that physically transport the management information across
the MII, a frame format and a protocol specification for exchanging management frames, and a register set
that can be read and written using these frames. MII management refers to the ability of a management
entity to communicate with PHY via the MII serial management interface (MI) for the purpose of displaying,
selecting and/or controlling different PHY options. The host manipulates the MAC to drive the MII
management serial interface. By manipulating the MAC's registers, MII management frames are
generated on the management interface for reading or writing information from the PHY registers. Timing
and framing for each management command is to be generated by the CPU (host).
The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface.
MDIO: Management Data input/output. Bi-directional between MAC and PHY that carries management
data. All control and status information sent over this pin is driven and sampled synchronously
to the rising edge of MDC signal.
MDC: Management Data Clock. Sourced by the MAC as a timing reference for transfer of information
on the MDIO signal. MDC is a periodic signal with no maximum high or low times. The
minimum high and low times should be 160ns each and the minimum period of the signal
should be 400ns. These values are regardless of the nominal period of the TX and RX clocks.
7.5.2 Management Data Timing
A timing diagram for a Ml serial port frame is shown in FIGURE 6. The Ml serial port is idle when at least
32 continuous 1's are detected on MDIO and remains idle as long as continuous 1's are detected. During
idle, MDIO is in the high impedance state. When the Ml serial port is in the idle state, a 01 pattern on the
MDIO initiates a serial shift cycle. Data on MDIO is then shifted in on the next 14 rising edges of MDC
(MDIO is high impedance). If the register access mode is not enabled, on the next 16 rising edges of
MDC, data is either shifted in or out on MDIO, depending on whether a write or read cycle was selected
with the bits READ and WRITE. After the 32 MDC cycles have been completed, one complete register
has been read/written, the serial shift process is halted, data is latched into the device, and MDIO goes
into high impedance state. Another serial shift cycle cannot be initiated until the idle condition (at least 32
continuous 1's) is detected.
7.5.3 MI Serial Port Frame Structure
The structure of the PHY serial port frame is shown in Table 5 and timing diagram of a frame is shown in
FIGURE 6. Each serial port access cycle consists of 32 bits (or 192 bits if multiple register access is
enabled and REGAD[4:0]=11111), exclusive of idle. The first 16 bits of the serial port cycle are always
write bits and are used for addressing. The last 16/176 bits are from one/all of the 11 data registers.
The first 2 bit in Table 5 and FIGURE 6 are start bits and need to be written as a 01 for the serial port cycle
to continue. The next 2 bits are a read and write bit which determine if the accessed data register bits will
be read or write. The next 5 bits are device addresses. The next 5 bits are register address select bits,
which select one of the five data registers for access. The next 1 bit is a turnaround bit which is not an
actual register bit but extra time to switch MDIO from write to read if necessary, as shown in FIGURE 6.
The final 16 bits of the PHY Ml serial port cycle (or 176 bits if multiple register access is enabled and
REGAD[4:0]=11111) come from the specific data register designated by the register address bits
REGAD[4:0].
SMSC DS – LAN91C111 Rev. B Page 21 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
1
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P
O
0
1
]
0
:
1
[
T
S
0
O
I
D
M
C
D
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F
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S
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1
3
0
3
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
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E
L
C
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D
A
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0
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1
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2
D
3
D
4
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5
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6
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7
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0
:
5
8
1
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D
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D
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2
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3
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4
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:
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A
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:
4
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D
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4
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:
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P
3
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A
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FIGURE 6 - MI SERIAL PORT FRAME TIMING DIAGRAM
Rev. 09/17/2002 Page 22 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
7.5.4 MII Packet Data Communication with External PHY
The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl
requirements outlined in IEEE 802.3 and shown in FIGURE 7.
OF
SFD
2 BT
TX_EN = 1
DATA 1
DATA NIBBLES
DATA 2
DATA N-1 DATA N
TX_EN = 0
IDLE
PREAMBLE
PRMBLE
62 BT
START
FRAME
DELIM.
TX_EN = 0
IDLE
= [ 1 0 1 0 ... ] 62 BITS LONG
= [ 1 1 ]
SFD
= [ BETWEEN 64-1518 DATA BYTES ]
DATAn
IDLE = TX_EN = 0
MAC's SERIAL BIT STREAM
MSB
SECOND
NIBBLE
MII
NIBBLE
STREAM
FIRST BIT
FIRST
NIBBLE
TXD0 / RXD0
TXD1 / RXD1
TXD2 / RXD2
TXD3 / RXD3
PREAMBLE
D0 D1 D2 D3 D4 D5 D6 D7
LSB
FIGURE 7 - MII FRAME FORMAT & MII NIBBLE ORDER
The Mll consists of the following signals: four transmit data bits (TXD[3:0]), transmit clock (TX25),transmit
enable (TXEN100), four receive data bits(RXD[3:0]), receive clock(RX25), carrier sense (CRS100), receive
data valid (RX_DV), receive data error (RX_ER), and collision (COL100). Transmit data is clocked out using
the TX25 clock input, while receive data is clocked in using RX25. The transmit and receive clocks operate at
25 MHz in 100Mbps mode and 2.5 MHz in 10Mbps.
In 100 Mbps mode, the LAN91C111 provides the following interface signals to the PHY:
For transmission: TXEN100, TXD0-3, TX25
For reception: RX_DV, RX_ER, RXD0-3, RX25
For CSMA/CD state machines: CRS100, COL100
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble
nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first out of the EPH
at 100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and TXD0-TXD3 are
clocked by the LAN91C111 using TX25 rising edges. TXEN100 goes inactive at the end of the packet on
the last nibble of the CRC.
During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to
the LAN91C111’s clocks and will be synchronized internally to TX25.
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will be present
at RXD0-RXD3 when RX_DV is activated. The LAN91C111 requires no training sequence beyond a full flag
octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0 carries the least
SMSC DS – LAN91C111 Rev. B Page 23 Rev. 09/17/2002
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Page 24
significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of
the packet (CRC) is presented at RXD0-RXD3.
RX_ER might be asserted during packet reception to signal the LAN91C111 that the present receive packet is
invalid. The LAN91C111 will discard the packet by treating it as a CRC error.
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider
misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on nonpreamble patterns.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff
functions), but it is not used for receive framing functions. CRS100 is an asynchronous signal and it will be
active whenever there is activity on the cable, including LAN91C111 transmissions and collisions.
7.6 Serial EEPROM Interface
This block is responsible for reading the serial EEPROM upon hardware reset (or equivalent command)
and defining defaults for some key registers. A write operation is also implemented by this block, that
under CPU command will program specific locations in the EEPROM. This block is an autonomous state
machine and controls the internal Data Bus of the LAN91C111 during active operation.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
7.7 Internal Physical Layer
The LAN91C111 integrates the IEEE 802.3 physical layer (PHY) internally. The EXT PHY bit in the
Configuration Register is 0 as the default configuration to set the internal PHY enabled. The internal PHY
address is 00000, the driver must use this address to talk to the internal PHY. The internal PHY is placed
in isolation mode at power up and reset. It can be removed from isolation mode by clearing the MII_DIS
bit in the PHY Control Register. If necessary, the internal PHY can be enabled by clearing the EXT_PHY
bit in the Configuration Register.
The internal PHY of LAN91C111 has nine main sections: controller interface, encoder, decoder, scrambler,
descrambler, clock and data recovery, twisted pair transmitter, twisted pair receiver, and MI serial port.
The LAN91C111 can operate as a 100BASE-TX device (hereafter referred to as 100Mbps mode) or as a
10BASE-T device (hereafter referred to as 10Mbps mode). The difference between the 100Mbps mode
and the 10Mbps mode is data rate, signaling protocol, and allowed wiring. The 100Mbps TX mode uses
two pairs of category 5 or better UTP or STP twisted pair cable with 4B5B encoded, scrambled, and MLT-3
coded 62.5 MHz ternary data to achieve a throughput of 100Mbps. The 10Mbps mode uses two pairs of
category 3 or better UTP or STP twisted pair cable with Manchester encoded, 10MHz binary data to
achieve a 10Mbps throughput. The data symbol format on the twisted pair cable for the 100 and 10Mbps
modes are defined in IEEE 802.3 specifications and shown in FIGURE 8.
Rev. 09/17/2002 Page 24 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
INTERFRAME
GAP
IDLE
IDLE
PREAMBLE
SSD
DA, SA, LN, LLC DATA, FCS
PREAMBLE
PREAMBLE
DA, SA, LN, LLC DATA, FCS
PREAMBLE
IDLE
PREAMBLE
SFD
= [ 1 1 ] WITH NO MID BIT TRANSITION
SOI
ETHERNET MAC
FRAME
SFD DA
100 BASE-TX DATA SYMBOLS
SFD
IDLE
SSD
= [ 1 1 0 0 0 1 0 0 0 1]
= [ 1 0 1 0 ...] 62 BITS LONG
= [ 1 1]
SFD
= [ DATA]
= [ 0 1 1 0 1 0 0 1 1 1]
ESD
10 BASE-T DATA SYMBOLS
SFD
= [ NO TRANSITIONS]
= [ 1 0 1 0 ... ] 62 BITS LONG
= [ 1 1]
= [ DATA]
DA
= [ 1 1 1 1...]
DA
SA
SA
SA
LN
LLC DATA
LN ESD
LLC DATA
BEFORE / AFTER
4B5B ENCODING,
SCRAMBLING,
AND MLT3
CODING
LN
LLC DATA
BEFORE / AFTER
MANCHESTER
ENCODING
FCS
FCS
FCS
SOI
INTERFRAME
GAP
IDLE
IDLE
FIGURE 8 - TX/10BT FRAME FORMAT
On the transmit side for 100Mbps TX operation, data is received on the controller and then sent to the
4B5B encoder for formatting. The encoded data is then sent to the scrambler. The scrambled and
encoded data is then sent to the TP transmitter. The TP transmitter converts the encoded and scrambled
data into MLT-3 ternary format, reshapes the output, and drives the twisted pair cable.
On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming encoded and
scrambled MLT-3 data from the twisted pair cable, remove any high frequency noise, equalizes the input
signal to compensate for the effects of the cable, qualifies the data with a squelch algorithm, and converts
the data from MLT-3 coded twisted pair levels to internal digital levels. The output of the twisted pair
receiver then goes to a clock and data recovery block which recovers a clock from the incoming data, uses
the clock to latch in valid data into the device, and converts the data back to NRZ format. The NRZ data is
SMSC DS – LAN91C111 Rev. B Page 25 Rev. 09/17/2002
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then unscrambled and decoded by the 4B5B decoder and descrambler, respectively, and outputted to the
Ethernet controller.
10Mbps operation is similar to the 100Mbps TX operation except, (1) there is no scrambler/descrambler,
(2) the encoder/decoder is Manchester instead of 4B5B, (3) the data rate is 10Mbps instead of 100Mbps,
and (4) the twisted pair symbol data is two level Manchester instead of ternary MLT-3.
The Management Interface, (hereafter referred to as the MI serial port), is a two pin bi-directional link
through which configuration inputs can be set and status outputs can be read. Each block plus the
operating modes are described in more detail in the following sections.
7.7.1 MII Disable
The internal PHY MII interface can be disabled by setting the MII disable bit in the MI serial port Control
register. When the MII is disabled, the MII inputs are ignored, the MII outputs are placed in high
impedance state, and the TP output is high impedance.
7.7.2 Encoder
4B5B Encoder - 100 Mbps
10/100 Non-PCI Ethernet Single Chip MAC + PHY
100BASE-TX requires that the data be 4B5B encoded. 4B5B coding converts the 4-Bit data nibbles into 5Bit date code words. The mapping of the 4B nibbles to the 5B code words is specified in IEEE 802.3. The
4B5B encoder on the LAN91C111 takes 4B nibbles from the controller interface, converts them into 5B
words and sends the 5B words to the scrambler. The 4B5B encoder also substitutes the first 8 bits of the
preamble with the SSD delimiters (a.k.a. /J/K/ symbols) and adds an ESD delimiter (a.k.a. MR/ symbols) to
the end of every packet, as defined in IEEE 802.3. The 4B5B encoder also fills the period between
packets, called the idle period, with the continuous stream of idle symbols.
Manchester Encoder - 10 Mbps
The Manchester encoding process combines clock and NRZ data such that the first half of the data bit
contains the complement of the data, and the second half of the data bit contains the true data, as
specified in IEEE 802.3. This guarantees that a transition always occurs in the middle of the bit call. The
Manchester encoder on the LAN91C111 converts the 10Mbps NRZ data from the controller interface into a
Manchester Encoded data stream for the TP transmitter and adds a start of idle pulse (SOI) at the end of
the packet as specified in IEEE 802.3. The Manchester encoding process is only done on actual packet
data, and the idle period between packets is not Manchester encoded and filled with link pulses.
7.7.3 Decoder
4B5B Decoder - 100 Mbps
Since the TP input data is 4B5B encoded on the transmit side, it must also be decoded by the 4B5B
decoder on the receive side. The mapping of the 5B nibbles to the 4B code words is specified in IEEE
802.3. The 4B5B decoder on the LAN91C111 takes the 5B code words from the descrambler, converts
them into 4B nibbles per Table 2, and sends the 4B nibbles to the controller interface. The 4B5B decoder
also strips off the SSD delimiter (a.k.a. /J/K/ symbols) and replaces them with two 4B Data 5 nibbles (a.k.a.
/5/ symbol), and strips off the ESD delimiter (a.k.a. /T/R/ symbols) and replaces it with two 4B Data 0
nibbles (a.k.a. /I/symbol), per IEEE 802.3 specifications and shown in FIGURE 8.
Rev. 09/17/2002 Page 26 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
SYMBOL NAME DESCRIPTION 5B CODE 4B CODE
0 Data 0 11110 0000
1 Data 1 01001 0001
2 Data 2 10100 0010
3 Data 3 10101 0011
4 Data 4 01010 0100
5 Data 5 01011 0101
6 Data 6 01110 0110
7 Data 7 01111 0111
8 Data 8 10010 1000
9 Data 9 10011 1001
A Data A 10110 1010
B Data B 10111 1011
C Data C 11010 1100
D Data D 11011 1101
E Data E 11100 1110
F Data F 11101 1111
I Idle 11111 0000
J SSD #1 11000 0101
K SSD #2 10001 0101
T ESD #1 01101 0000
R ESD #2 00111 0000
H Halt 00100 Undefined
--- Invalid codes All others* 0000*
Table 2 - 4B/5B Symbol Mapping
* These 5B codes are not used. For decoder, these 5B codes are decoded to 4B 0000. For encoder, 4B
0000 is encoded to 5B 11110, as shown in symbol Data 0.
The 4B5B decoder detects SSD, ESD and codeword errors in the incoming data stream as specified in
IEEE 802.3. These errors are indicated by asserting RX_ER output while the errors are being transmitted
across RXD[3:0], and they are also indicated in the serial port by setting SSD, ESD, and codeword error
bits in the PHY MI serial port Status Output register.
Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the complement of the data, and the
second half of the data bit contains the true data. The Manchester decoder in the LAN91C111 converts
the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface by
decoding the data and stripping off the SOI pulse. Since the clock and data recovery block has already
separated the clock and data from the TP receiver, the Manchester decoding process to NRZ data is
inherently performed by that block.
7.7.4 Clock and Data Recovery
Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked to
the 25 MHz TX25. When valid data is detected on the TP inputs with the squelch circuit and when the
adaptive equalizer has settled, the PLL input is switched to the incoming data on the TP input. The PLL
then recovers a clock by locking onto the transitions of the incoming signal from the twisted pair wire. The
SMSC DS – LAN91C111 Rev. B Page 27 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
recovered dock frequency is a 25 MHz nibble dock, and that clock is outputted on the controller interface
signal RX25.
Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted by
the PLL. The data is then converted from a single bit stream into nibble wide data word according to the
format shown in FIGURE 7.
Clock Recovery - 10 Mbps
The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except, (1) the recovered
clock frequency is 2.5 MHz nibble clock, (2) the PLL is switched from TX25 to the TP input when the
squelch indicates valid data, (3) The PLL takes up to 12 transitions (bit times) to lock onto the preamble, so
some of the preamble data symbols are lost, but the dock recovery block recovers enough preamble
symbols to pass at least 6 nibbles of preamble to the receive controller interface as shown in FIGURE 7.
Data Recovery - 10 Mbps
The data recovery process for 10Mbps mode is identical to the 100Mbps mode. As mentioned in the
Manchester Decoder section, the data recovery process inherently performs decoding of Manchester
encoded data from the TP inputs.
7.7.5 Scrambler
100 Mbps
100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The LAN91C111
scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications,
and sends it to the TP transmitter.
10 Mbps
A scrambler is not used in 10Mbps mode.
Scrambler Bypass
The scrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY Ml serial port
Configuration 1 register. When this bit is set, the 5B data bypasses the scrambler and goes directly from
the 4B5B encoder to the twisted pair transmitter.
7.7.6 Descrambler
100 Mbps
The LAN91C111 descrambler takes the scrambled data from the data recovery block, descrambles it per
the IEEE 802.3 specifications, aligns the data on the correct 5B word boundaries, and sends it to the 4B5B
decoder.
The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE
802.3 specification. Once the descrambler is synchronized, it will maintain synchronization as long as
enough descrambled idle pattern 1's are detected within a given interval. To stay in synchronization, the
descrambler needs to detect at least 25 consecutive descrambled idle pattern 1's in a 1ms interval. If 25
Rev. 09/17/2002 Page 28 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
consecutive descrambled idle pattern 1's are not detected within the 1ms interval, the descrambler goes
out of synchronization and restarts the synchronization process.
If the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is set
in the Ml serial port Status Output register to indicate this condition. Once this bit is set, it will stay set until
the descrambler achieves synchronization.
10 Mbps
A descrambler is not used in 10 Mbps mode.
Descrambler Bypass
The descrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY MI serial
port Configuration 1 register. When this bit is set, the data bypasses the descrambler and goes directly
from the TP receiver to the 4B5B decoder.
7.7.7 Twisted Pair Transmitter
Transmitter - 100 Mbps
The TX transmitter consists of MLT-3 encoder, waveform generator and line driver.
The MLT-3 encoder converts the NRZ data from the scrambler into a three level MLT-3 code required by
IEEE 802.3. MLT-3 coding uses three levels and converts 1's to transitions between the three levels, and
converts 0's to no transitions or changes in level.
The purpose of the waveform generator is to shape the transmit output pulse. The waveform generator
takes the MLT-3 three level encoded waveform and uses an array of switched current sources to control
the rise/fall time and level of the signal at the Output. The output of the switched current sources then
goes through a low pass filter in order to "smooth" the current output and remove any high frequency
components. In this way, the waveform generator preshapes the output waveform transmitted onto the
twisted pair cable to meet the pulse template requirements outlined in IEEE 802.3. The waveform
generator eliminates the need for any external filters on the TP transmit output.
The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters
of category 5 unshielded twisted pair cable or 150 Ohm shielded twisted pair cable.
Transmitter - 10 Mbps
The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter. Even so, the
transmitter still consists of a waveform generator and line driver.
The purpose of the waveform generator is to shape the output transmit pulse. The waveform generator
consists of a ROM, DAC, dock generator, and filter. The DAC generates a stair-stepped representation of
the desired output waveform. The stairstepped DAC output then goes through a low pass filter in order to
"smooth' the DAC output and remove any high frequency components. The DAC values are determined
from the ROM outputs; the ROM contents are chosen to shape the pulse to the desired template and are
clocked into the DAC at high speed by the clock generator. In this way, the waveform generator
preshapes the output waveform to be transmitted onto the twisted pair cable to meet the pulse template
requirements outlined in IEEE 802.3 Clause 14 and also shown in FIGURE 9. The waveshaper replaces
and eliminates external filters on the TP transmit output.
The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters
of category 3/4/5 100 Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied
SMSC DS – LAN91C111 Rev. B Page 29 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
directly to the TP output pins without any external filters. During the idle period, no output signal is
transmitted on the TP outputs (except link pulse).
1.0
0.8
0.6
0.4
0.2
)
0.0
V
(
e
g
-0.2
a
t
l
o
-0.4
V
-0.6
-0.8
-1.0
0 102030405060708090100110
B
H
D
C
A
E
F
G
I
M
L
N
P
O
Q
J
K
W
R
S
U
V
T
TIME (ns)
FIGURE 9 - TP OUTPUT VOLTAGE TEMPLATE-10 MBPS
REFERENCE
TIME (NS)
INTERNAL
MAU
VOLTAGE
(V)
A 0 0
B 15 1.0
C 15 0.4
D 25 0.55
E 32 0.45
F 39 0
G 57 -1.0
H 48 0.7
I 67 0.6
J 89 0
K 74 -0.55
L 73 -0.55
M 61 0
N 85 1.0
O 100 0.4
P 110 0.75
Q 111 0.15
R 111 0
S 111 -0.15
T 110 -1.0
U 100 -0.3
V 110 -0.7
W 90 -0.7
Rev. 09/17/2002 Page 30 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Transmit Level Adjust
The transmit output current level is derived from an internal reference voltage and the external resistor on
RBIAS pin. The transmit level can be adjusted with either (1) the external resistor on the RBIAS pin, or (2)
the four transmit level adjust bits in the PHY Ml serial port Configuration 1 register as shown in Table 3.
The adjustment range is approximately -14% to +16% in 2% steps.
Table 3 - Transmit Level Adjust
TLVL[3:0] GAIN
0000 1.16
0001 1.14
0010 1.12
0011 1.10
0100 1.08
0101 1.06
0110 1.04
0111 1.02
1000 1.00
1001 0.98
1010 0.96
1011 0.94
1100 0.92
1101 0.90
1110 0.88
1111 0.86
Transmit Rise and Fall Time Adjust
The transmit output rise and fall time can be adjusted with the two transmit rise/fall time adjust bits in the
PHY Ml serial port Configuration 1. The adjustment range is -0.25ns to +0.5ns in 0.25ns steps.
STP (150 Ohm) Cable Mode
The transmitter can be configured to drive 150 Ohm shielded twisted pair cable. The STP mode can be
selected by appropriately setting the cable type select bit in the PHY MI serial port Configuration 1 register.
When STP mode is enabled, the output current is automatically adjusted to comply with IEEE 802.3 levels.
Transmit Disable
The TP transmitter can be disabled by setting the transmit disable bit in the PHY Ml serial port
Configuration 1 register. When the transmit disable bit is set, the TP transmitter is forced into the idle
state, no data is transmitted, no link pulses are transmitted, and internal loopback is disabled.
Transmit Powerdown
The TP transmitter can be powered down by setting the transmit powerdown bit in the PHY Ml serial port
Configuration 1 register. When the transmit powerdown bit is set, the TP transmitter is powered down, the
TP transmit outputs are high impedance, and the rest of the LAN91C111 operates normally.
SMSC DS – LAN91C111 Rev. B Page 31 Rev. 09/17/2002
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7.7.8 Twisted Pair Receiver
Receiver - 100 Mbps
The TX receiver detects input signals from the twisted pair input and converts it to a digital data bit stream
ready for dock and data recovery. The receiver can reliably detect data from a 100BASE-TX transmitter
that has been passed through 0-100 meters of 100-Ohm category 5 UTP or 150 Ohm STP.
The TX receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and
MLT-3 decoder. The TP inputs first go to an adaptive equalizer. The adaptive equalizer cornpensates for
the low pass characteristic of the cable, and it has the ability to adapt and compensate for 0-100 meters of
category 5, 100 Ohm UTP or 150 Ohm STP twisted pair cable. The baseline wander correction circuit
restores the DC component of the input waveform that was removed by external transformers. The
comparators convert the equalized signal back to digital levels and are used to qualify the data with the
squelch circuit. The MLT-3 decoder takes the three level MLT-3 digital data from the comparators and
converts it to back to normal digital data to be used for dock and data recovery.
Receiver - 10 Mbps
The 10 Mbps receiver is able to detect input signals from the twisted pair cable that are within the template
shown in FIGURE 10. The inputs are biased by internal resistors. The TP inputs pass through a low pass
filter designed to eliminate any high frequency noise on the input. The output of the receive filter goes to
two different types of comparators, squelch and zero crossing. The squelch comparator determines
whether the signal is valid, and the zero crossing comparator is used to sense the actual data transitions
once the signal is determined to be valid. The output of the squelch comparator goes to the squelch circuit
and is also used for link pulse detection, SOI detection, and reverse polarity detection; the output of the
zero crossing comparator is used for clock and data recovery in the Manchester decoder.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Rev. 09/17/2002 Page 32 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
a. Short Bit
3.1V
Slope 0.5 V/ ns
585mV
0
585 mV sin (2 t/PW)
0
PW/4
585 mV sin ( t/PW)
b. Long Bit
Slope 0.5 V/ ns
*
585 mV sin [2 (t - PW/2)/PW]
*
PW
3.1V
585mV
PW3PW/4
FIGURE 10 - TP INPUT VOLTAGE TEMPLATE-10MBPS
TP Squelch - 100 Mbps
The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one of the
criteria used to determine link integrity. The squelch comparators compare the TP inputs against fixed
positive and negative thresholds, called squelch levels. The output from the squelch comparator goes to a
digital squelch circuit which determines if the receive input data on that channel is valid. If the data is
invalid, the receiver is in the squelched state. If the input voltage exceeds the squelch levels at least 4
times with alternating polarity within a 10 µS interval, the data is considered to be valid by the squelch
circuit and the receiver now enters into the unquelch state. In the unsquelch state, the receive threshold
level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level.
When the receiver is in the unsquelch state, then the input signal is deemed to be valid. The device stays
in the unsquelch state until loss of data is detected. Loss of data is detected if no alternating polarity
unsquelch transitions are detected during any 10 µS interval. When the loss of data is detected, the
receive squelch is turned on again.
TP Squelch, 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps mode except, (1) the 10 Mbps TP
squelch algorithm is not used for link integrity but to sense the beginning of a packet, (2) the receiver goes
into the unsquelch state if the input voltage exceeds the squelch levels for three bit times with alternating
polarity within a 50-250 nS interval, (3) the receiver goes into the squelch state when idle is detected, (4)
unsquelch detection has no affect on link integrity, link pulses are used for that in 10 Mbps mode, (5) start
of packet is determined when the receiver goes into the unsquelch state an a CRS100 is asserted, and (6)
the receiver meets the squelch requirements defined in IEEE 802.3 Clause 14.
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Equalizer Disable
The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY Ml serial port
Configuration 1 register. When disabled, the equalizer is forced into the response it would normally have if
zero cable length was detected.
Receive Level Adjust
The receiver squelch and unsquelch levels can be lowered by 4.5 dB by setting the receive level adjust bit
in the PHY Ml serial port Configuration 1 register. By setting this bit, the device may be able to support
longer cable lengths.
7.7.9 Collision
100 Mbps
Collision occurs whenever transmit and receive occur simultaneously while the device is in Half Duplex.
Collision is sensed whenever there is simultaneous transmission (packet transmission on TPO±) and
reception (non-idle symbols detected on TP input). When collision is detected, the MAC is notified. Once
collision starts, the receive and transmit packets that caused the collision are terminated by their
respective MACs until the responsible MACs terminate the transmission, the PHY continues to pass the
data on.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
The collision function is disabled if the device is in the Full Duplex mode, is in the Link Fail State, or if the
device is in the diagnostic loopback mode.
10 Mbps
Collision in 10Mbps mode is identical to the 100Mbps mode except, (1) reception is determined by the
10Mbps squelch criteria, (2) data being passed to the MAC are forced to all 0's, (3) MAC is notified of the
collision when the SQE test is performed, (4) MAC is notified of the collision when the jabber condition has
been detected.
Collision Test
The MAC and PHY collision indication can be tested by setting the collision test register bit in the PHY MI
serial port Control register. When this bit is set, internal TXEN from the MAC is looped back onto COL and
the TP outputs are disabled.
7.7.10 Start of Packet
100 Mbps
Start of packet for 100 Mbps mode is indicated by a unique Start of Stream Delimiter (referred to as SSD).
The SSD pattern consists of the two /J/K/ 5B symbols inserted at the beginning of the packet in place of
the first two preamble symbols, as defined in IEEE 802.3 Clause 24.
The transmit SSD is generated by the 4B5B encoder and the /J/K/ symbols are inserted by the 4B5B
encoder at the beginning of the transmit data packet in place of the first two 5B symbols of the preamble.
The receive pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits
(two 5B words) from the descrambler. Between packets, the receiver will be detecting the idle pattern,
which is 5B /I/ symbols. While in the idle state, the MAC is notified that no data/invalid data is received.
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If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /J/K/
symbols, the start of packet is detected, data reception is begun, the MAC is notified that valid data is
received, and 5/5/ symbols are substituted in place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is
neither /I/I/ nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the
start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad SSD) is
signaled to the controller interface. When False Carrier is detected, the MAC is notified of false carrier and
invalid received, and the bad SSD bit is set in the PHY Ml serial port Status Output register. Once a False
Carrier Event is detected, the idle pattern (two /I/I/ symbols) must be detected before any new SSD's can
be sensed.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is
neither /l/l/ nor /J/K/ symbols but does not contain at least 2 non-contiguous 0's, the data is ignored and the
receiver stays in the idle state.
10 Mbps
Since the idle period in 10 Mbps mode is defined to be the period when no data is present on the TP
inputs, then the start of packet for 10 Mbps mode is detected when valid data is detected by the TP
squelch circuit. When start of packet is detected, carrier sense signal at internal MII is asserted as
described in the Controller Interface section. Refer to the TP squelch section for 10 Mbps mode for the
algorithm for valid data detection.
7.7.11 End of Packet
100 Mbps
End of packet for 100 Mbps mode is indicated by the End of Stream Delimiter (referred to as ESD). The
ESD pattern consists of the two /T/R/ 4B5B symbols inserted after the end of the packet, as defined in
IEEE 802.3 Clause 24.
The transmit ESD is generated by the 4B5B encoder and the /T/R/ symbols are inserted by the 4B5B
encoder after the end of the transmit data packet.
The receive ESD pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code
bits (two 5B words) from the descrambler during valid packet reception to determine if there is an ESD.
If the 10 consecutive code bits from the receiver during valid packet reception consist of the /T/R/ symbols,
the end of packet is detected, data reception is terminated, the MAC is notified of valid data received, and
/I/I/ symbols are substituted in place of the /T/R/ symbols.
If 10 consecutive code bits from the receiver during valid packet reception do not consist of /T/R/ symbols
but consist of /I/I/ symbols instead, then the packet is considered to have been terminated prematurely and
abnormally. When this premature end of packet condition is detected, the MAC is notified of invalid data
received for the nibble associated with the first /I/ symbol. Premature end of packet condition is also
indicated by setting the bad ESD bit in the PHY Ml serial port Status Output register.
10 Mbps
The end of packet for 10 Mbps mode is indicated with the SOI (Start of Idle) pulse. The SOI pulse is a
positive pulse containing a Manchester code violation inserted at the end of every packet.
The transmit SOI pulse is generated by the TP transmitter and inserted at the end of the data packet after
TXEN is deasserted. The transmitted SOI output pulse at the TP output is shaped by the transmit
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waveshaper to meet the pulse template requirements specified in IEEE 802.3 Clause 14 and shown in
FIGURE 11.
The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI
pulse is detected, data reception is ended and the MAC is notified of no data/invalid data received.
0 BT
3.1 V
0.5 V/ns
0.25 BT
585 mV
585 mV sin(2 (t/1BT))
0 t 0.25 BT and
2.25 t 2.5 BT
***
-3.1 V
FIGURE 11 - SOI OUTPUT VOLTAGE TEMPLATE - 10MBPS
2.25 BT
4.5 BT
4.5 BT2.5 BT
6.0 BT
+50 mV
-50 mV
45.0 BT
7.7.12 Link Integrity & Autonegotiation
General
The LAN91C111 can be configured to implement either the standard link integrity algorithms or the
AutoNegotiation algorithm.
The standard link integrity algorithms are used solely to establish an active link to and from a remote
device. There are different standard link integrity algorithms for 10 and 100 Mbps modes. The
AutoNegotiation algorithm is used for two purposes: (1) To automatically configure the device for either
10/100 Mbps and Half/Full Duplex modes, and (2) to establish an active link to and from a remote device.
The standard link integrity and AutoNegotiation algorithms are described below.
AutoNegotiation is only specified for 100BASE-TX and 10BASE-T operation.
10BASE-T Link Integrity Algorithm - 10Mbps
The LAN91C111 uses the same 10BASE-T link integrity algorithm that is defined in IEEE 802.3 Clause 14.
This algorithm uses normal link pulses, referred to as NLP's and transmitted during idle periods, to
determine if a device has successfully established a link with a remote device (called Link Pass State).
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1.3
The transmit link pulse meets the template defined in IEEE 802.3 Clause 14 and shown in FIGURE 12.
Refer to IEEE 802.3 Clause 14 for more details if needed.
+50 mV
-50 mV
3.1 V
585 mV
BT
0
0.25
BT
0.5 V/ns
-3.1 V
0.5
BT
0.6
BT
0.85
BT
2.0
2.0
BT
300 mV
200 mV
4.0
BT
4.0
BT
42.0
BT
+50 mV
-50 mV
FIGURE 12 - LINK PULSE OUTPUT VOLTAGE TEMPLATE - NLP, FLP
100BASE-TX Link Integrity Algorithm -100Mbps
Since 100BASE-TX is defined to have an active idle signal, then there is no need to have separate link
pulses like those defined for 10BASE-T. The LAN91C111 uses the squelch criteria and descrambler
synchronization algorithm on the input data to determine if the device has successfully established a link
with a remote device (called Link Pass State). Refer to IEEE 802.3 for both of these algorithms for more
details.
AutoNegotiation Algorithm
As stated previously, the AutoNegotiation algorithm is used for two purposes: (1) To automatically configure the device for either 10/100 Mbps and Half/ Full Duplex modes, and (2) to establish an active link to
and from a remote device. The AutoNegotiation algorithm is the same algorithm that is defined in IEEE
802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast link pulses and referred to as
FLP'S, to pass up to 16 bits of signaling data back and forth between the LAN91C111 and a remote
device. The transmit FLP pulses meet the templated specified in IEEE 802.3 and shown in FIGURE 12. A
timing diagram contrasting NLP's and FLP's is shown in FIGURE 13.
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a.) Normal Link Pulse (NLP)
TPO±
b.) Fast Link Pulse (FLP)
TPO±
D0 D15D14D3D2D1
Clock Clock Clock Clock Clock Clock Clock
Data Data Data Data Data Data
FIGURE 13 - NLP VS. FLP LINK PULSE
The AutoNegotiation algorithm is initiated by any of these events: (1) AutoNegotiation enabled, (2) a device
enters the Link Fail State, (3) AutoNegotiation Reset. Once a negotiation has been initiated, the
LAN91C111 first determines if the remote device has AutoNegotiation capability. If the remote device is
not AutoNegotiation capable and is just transmitting either a 10BASE-T or 100BASE-TX signal, the
LAN91C111 will sense that and place itself in the correct mode. If the LAN91C111 detects FLP's from the
remote device, then the remote device is determined to have AutoNegotiation capability and the device
then uses the contents of the Ml serial port AutoNegotiation Advertisement register and FLP's to advertise
its capabilities to a remote device. The remote device does the same, and the capabilities read back from
the remote device are stored in the PHY Ml serial port AutoNegotiation Remote End Capability register.
The LAN91C111 negotiation algorithm then matches it's capabilities to the remote device's capabilities and
determines what mode the device should be configured to according to the priority resolution algorithm
defined in IEEE 802.3 Clause 28. Once the negotiation process is completed, the LAN91C111 then
configures itself for either 10 or 100 Mbps mode and either Full or Half Duplex modes (depending on the
outcome of the negotiation process), and it switches to either the 100BASETX or 10BASE-T link integrity
algorithms (depending on which mode was enabled by AutoNegotiation). Refer to IEEE 802.3 Clause 28
for more details.
AutoNegotiation Outcome Indication
The outcome or result of the AutoNegotiation process is stored in the speed detect and duplex detect bits
in the PHY MI serial port Status Output register.
AutoNegotiation Status
The status of the AutoNegotiation process can be monitored by reading the AutoNegotiation
acknowledgement bit in the Ml serial port Status register. The Ml serial port Status register contains a
single AutoNegotiation acknowledgement bit which indicates when an AutoNegotiation has been initiated
and successfully completed.
AutoNegotiation Enable
The AutoNegotiation algorithm can be enabled by setting both the ANEG bit in the MAC Receive/PHY
Control Register and the ANEG_EN bit in the MI PHY Register 0 (Control register). Clearing either of
these two bits will turn off AutoNegotiation mode. When the AutoNegotiation algorithm is enabled, the
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device halts all transmissions including link pulses for 1200-1500 ms, enters the Link Fail State, and
restarts the negotiation process. When AutoNegotiation mode is turned on or reset, software driver should
wait for at least 1500ms to read the ANEG_ACK bit in the MI PHY Status Register to determine whether
the AutoNegotiation process has been completed. When the ANEG bit in the Receive/PHY Control
Register is cleared, AutoNegotiation algorithm is disabled, the selection of 10/100 Mbps mode and duplex
mode is determined by the SPEED bit and the DPLX bit in the MAC Receive/PHY Control register. When
the ANEG bit in the Receive/PHY Control Register is set and the ANEG_EN bit in the MI PHY Register 0
(Control Register) is cleared, AutoNegotiation algorithm is disabled, the selection of 10/100 Mbps mode
and duplex mode is determined by the SPEED bit and the DPLX bit in the MI PHY Register 0 (Control
Register).
AutoNegotiation Reset
The AutoNegotiation algorithm can be initiated at any time by setting the AutoNegotiation reset bit in the
PHY MI serial port Control register.
Link Disable
The link integrity function can be disabled by setting the link disable bit in the PHY Ml serial port
Configuration 1 register. When the link integrity function is disabled, the device is forced into the Link Pass
state, configures itself for Half/Full Duplex based on the value of the duplex bit in the PHY MI serial port
Control register, configures itself for 100/10 Mbps operation based on the values of the speed bit in the Ml
serial port Control register, and continues to transmit NLP'S or TX idle patterns, depending on whether the
device is in 10 or 100 Mbps mode.
7.7.13 Jabber
100 Mbps
Jabber function is disabled in the 100 Mbps mode.
10 Mbps
Jabber condition occurs when the transmit packet exceeds a predetermined length. When jabber is
detected, the TP transmit outputs are forced to the idle state, collision is asserted, and register bits in the
PHY Ml serial port Status and Status Output registers are set.
Jabber Disable
The jabber function can be disabled by setting the jabber disable bit in the PHY MI serial port Configuration
2 register.
7.7.14 Receive Polarity Correction
100 Mbps
No polarity detection or correction is needed in 100Mbps mode.
10 Mbps
The polarity of the signal on the TP receive input is continuously monitored. If either 3 consecutive link
pulses or one SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally
determined to be incorrect, and a reverse polarity bit is set in the PHY Ml serial port Status Output register.
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The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity
feature is not disabled.
Autopolarity Disable
The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port
Configuration 2 register.
7.7.15 Full Duplex Mode
100 Mbps
Full Duplex mode allows transmission and reception to occur simultaneously. When Full Duplex mode is
enabled, collision is disabled.
The device can be either forced into Half or Full Duplex mode, or the device can detect either Half or Full
Duplex capability from a remote device and automatically place itself in the correct mode.
The device can be forced into the Full or Half Duplex modes by either setting the duplex bit in the MI serial
port Control register.
The device can automatically configure itself for Full or Half Duplex modes by using the AutoNegotiation
algorithm to advertise and detect Full and Half Duplex capabilities to and from a remote terminal. All of
this is described in detail in the Link Integrity and AutoNegotiation section.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
10 Mbps
Full Duplex in 10 Mbps mode is identical to the 100 Mbps mode.
100/10 Mbps SELECTION
General
The device can be forced into either the 100 or 10 Mbps mode, or the device also can detect 100 or 10
Mbps capability from a remote device and automatically place itself in the correct mode.
The device can be forced into either the 100 or 10 Mbps mode by setting the speed select bit in the PHY
MI serial port Control register assuming AutoNegotiation is not enabled.
The device can automatically configure itself for 100 or 10 Mbps mode by using the AutoNegotiation
algorithm to advertise and detect 100 and 10 Mbps capabilities to and from a remote terminal. All of this is
described in detail in the Link Integrity & AutoNegotiation section.
7.7.16 Loopback
Diagnostic Loopback
A diagnostic loopback mode can also be selected by setting the loopback bit in the MI serial port Control
register. When diagnostic loopback is enabled, transmit data at internal MII is looped back onto receive
data output at internal MII, transmit enable signal is looped back onto carrier sense output at internal MII,
the TP receive and transmit paths are disabled, the transmit link pulses are halted, and the Half/Full
Duplex modes do not change.
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7.7.17 PHY Powerdown
The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY Ml serial
port Control register. In powerdown mode, the TP outputs are in high impedance state, all functions are
disabled except the PHY Ml serial port, and the power consumption is reduced to a minimum. The device
is guaranteed to be ready for normal operation 500mS after powerdown is deasserted.
7.7.18 PHY Interrupt
The LAN91C111 PHY has interrupt capability. The interrupt is triggered by certain output status bits (also
referred to as interrupt bits) in the serial port. R/LT bits are read bits that latch on transition. R/LT bits are
also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch
themselves into their register locations and assert the interrupt indication when they change state.
Interrupt bits stay latched until they are read. When interrupt bits are read, the interrupt indication is
deasserted and the interrupt bits that caused the interrupt to happen are updated to their current value.
Each interrupt bit can be individually masked and subsequently be removed as an interrupt bit by setting
the appropriate mask register bits in the Mask register.
lnterrupt indication is done in two ways: (1) MDINT bit in Interrupt Status Register, (2) INT bit in the PHY Ml
Serial Port Status Output register. The INT bit is an active high interrupt register bit that resides in the
PHY MI Serial Port Status Output register.
7.8 Reset
The chip (MAC & PHY) performs an internal system reset when either (1) the RESET pin is asserted high
for at least 100ns, (2) writing “1” to the SOFT_RST bit in the Receive Control Register, this reset bit is not
a self-clearing bit, reset can be terminated by writing the bit low. It programs all registers to their default
value. When reset is initiated by (1) and the EEPROM is presented and enabled, the controller will load the
EEPROM to obtain the following configurations: 1) Configuration Register, 2) BASE Register, or/and 3)
MAC Address. The internal MAC is not a power on reset device, thus reset is required after power up to
ensure all register bits are in default state.
The internal PHY is reset when either (1) VDD is applied to the device, (2) the RST bit is set in the PHY Ml
serial port Control register, this reset bit is a self-clearing bit, and the PHY will return a “1” on reads to this
bit until the reset is completed, 3) the RESET pin is asserted high, (4) the SOFT_RST bit is set high and
then cleared. When reset is initiated by (1) or (2), an internal power-on reset pulse is generated which
resets all internal circuits, forces the PHY Ml serial port bits to their default values, and latches in new
values for the MI address. After the power-on reset pulse has finished, the reset bit in the PHY Ml serial
port Control registers cleared and the device is ready for normal operation. When reset is initiated by (3),
the same procedure occurs except the device stays in the reset state as long as the RESET pin is held
high. The internal PHY is guaranteed to be ready for normal operation 50 mS after the reset pin was deasserted or the reset bit is set. Software driver requires to wait for 50mS after setting the RST bit to high to
access the internal PHY again.
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Chapter 8 MAC Data Structures and Registers
8.1 Frame Format In Buffer Memory
The frame format in memory is similar for the Transmit and Receive areas. The first word is reserved for
the status word. The next word is used to specify the total number of bytes, and it is followed by the data
area. The data area holds the frame itself.
bit15
bit0
RAM
OFFSET
1st Byte2nd Byte
(DECIMAL)
0
2
RESERVED
STATUS WORD
BYTE COUNT (always even)
4
DATA AREA
2046 Max
CONTROL BYTE
LAST DATA BYTE (if odd)
Last Byte
FIGURE 14 - DATA FRAME FORMAT
TRANSMIT PACKET RECEIVE PACKET
STATUS WORD Written by CSMA upon transmit
completion (see Status Register)
BYTE COUNT Written by CPU Written by CSMA
DATA AREA Written/modified by CPU Written by CSMA
CONTROL BYTE Written by CPU to control
odd/even data bytes
Written by CSMA upon receive
completion (see RX Frame
Status Word)
Written by CSMA; also has
odd/even bit
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BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the
BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The maximum number of bytes in a
RAM page is 2048 bytes.
The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low
byte of the last word is relevant.
The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in
memory.
DATA AREA - The data area starts at offset 4 of the packet structure and can extend up to 2043 bytes.
The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS,
followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the
source address. The LAN91C111 does not insert its own source address. On receive, all bytes are provided by
the CSMA side.
The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C111. It is treated
transparently as data both for transmit and receive operations.
CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the CPU as:
X X ODD CRC 0 0 0 0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE.
If clear, the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted.
CRC - When set, CRC will be appended to the frame. This bit has only meaning if the NOCRC bit in the
TCR is set.
For receive packets the CONTROL BYTE is written by the controller as:
0 1 ODD 0 0 0 0 0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE.
If clear, the number of data bytes is even and the byte before the CONTROL BYTE should be ignored.
8.2 Receive Frame Status
This word is written at the beginning of each receive frame in memory. It is not available as a register.
HIGH
BYTE
LOW
BYTE
ALGN
ERR
Reserved 5 4 3 2 1 0
BROD
CAST
BAD
CRC
ODD
FRM
HASH VALUE
TOOLNG
TOO
SHORT
MULT
CAST
ALGNERR - Frame had alignment error.
BRODCAST - Receive frame was broadcast.
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BADCRC - Frame had CRC error, or RX_ER was asserted during reception.
ODDFRM - This bit when set indicates that the received frame had an odd number of bytes.
TOOLNG - Frame length was longer than 802.3 maximum size (1518 bytes on the cable).
TOOSHORT - Frame length was shorter than 802.3 minimum size (64 bytes on the cable).
HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive
routines to speed up the group address search. The hash value consists of the six most significant bits of
the CRC calculated on the Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the
hash value select a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected.
Examples of the address mapping:
ADDRESS HASH VALUE 5-0 MULTICAST TABLE BIT
ED 00 00 00 00 00
0D 00 00 00 00 00
01 00 00 00 00 00
2F 00 00 00 00 00
MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set,
and the address was a multicast, the packet will pass address filtering regardless of other filtering criteria.
000 000
010 000
100 111
111 111
MT-0 bit 0
MT-2 bit 0
MT-4 bit 7
MT-7 bit 7
8.3 I/O Space
The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the I/O
space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O
area is shared by all banks and can be used to change the bank in use. Registers are described using the
following convention:
OFFSET NAME TYPE SYMBOL
HIGH
BYTE
X X X X X X X X
LOW
BYTE
X X X X X X X X
OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided
the bank select has the appropriate value.
The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.
The odd byte can be accessed using address (offset + 1).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit
registers, in that case the offset of each one is independently specified.
Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
The default bit values upon hard reset are highlighted below each register.
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Table 4 - Internal I/O Space Mapping
BANK0 BANK1 BANK2 BANK3
0 TCR CONFIG MMU COMMAND MT0-1
2 EPH STATUS BASE PNR MT2-3
4 RCR IA0-1 FIFO PORTS MT4-5
6 COUNTER IA2-3 POINTER MT6-7
8 MIR IA4-5 DATA MGMT
A RPCR GENERAL DATA REVISION
C RESERVED CONTROL INTERRUPT ERCV
E BANK BANK BANK BANK
A special BANK (BANK7) exists to support the addition of external registers.
8.4 Bank Select Register
OFFSET NAME TYPE SYMBOL
E BANK SELECT
REGISTER
HIGH
BYTE
0 0 1 1 0 0 1 1
LOW
BYTE
X X X X X 0 0 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BS2 BS1 BS0
READ/WRITE BSR
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to
select the register bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the
LAN91C111.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2
Note
: The bank select register can be accessed as a doubleword at offset 0x0Ch, as a word at offset 0x0Eh, or
as a byte at offset 0x0Eh, A doubleword write to offset 0x0Ch will write the BANK SELECT REGISTER but
will not write the registers 0x0Ch and 0x0Dh, but will only write to register 0x0Eh
BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles where
BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of
external registers.
Note
: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be
done if the Revision Control register indicates the device is the LAN91C111.
Bank 7 is a new register Bank to the SMSC LAN91C111 device. This bank has extended registers that
allow the extended feature set of the SMSC LAN91C111.
SMSC DS – LAN91C111 Rev. B Page 45 Rev. 09/17/2002
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8.5 Bank 0 - Transmit Control Register
OFFSET NAME TYPE SYMBOL
0 TRANSMIT CONTROL
REGISTER
This register holds bits programmed by the CPU to control some of the protocol transmit options.
READ/WRITE TCR
10/100 Non-PCI Ethernet Single Chip MAC + PHY
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
SWFDUP
PAD_EN Reserved Reserved Reserved Reserved FORCOL LOOP TXENA
Reserved
EPH
LOOP
STP
SQET
FDUPLX
MON_
CSN
Reserved NOCRC
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from
recognizing carrier sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision
related status bits in the EPHSR are not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and
SNGL COL). Uses COL100 as flow control, limiting backoff and jam to 1 clock each before inter-frame
gap, then retry will occur after IFG. If COL100 is active during preamble, full preamble will be output
before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have no effect.
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults
low. When EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3 = 0h,
TXEN100 = 0. The following and external inputs are blocked: CRS100=0, COL100=0, RX_DV= RX_ER=0.
STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error.
Does not stop on SQET error and transmits next frame if clear. Defaults low.
FDUPLX - When set the LAN91C111 will cause frames to be received if they pass the address filter
regardless of the source for the frame. When clear the node will not receive a frame sourced by itself. This
bit does not control the duplex mode operation, the duplex mode operation is controlled by the SWFDUP
bit.
MON_CSN - When set the LAN91C111 monitors carrier while transmitting. It must see its own carrier by
the end of the preamble. If it is not seen, or if carrier is lost during transmission, the transmitter aborts the
frame without CRC and turns itself off and sets the LOST CARR bit in the EPHSR. When this bit is clear
the transmitter ignores its own carrier. Defaults low. Should be 0 for MII operation.
NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired
CRC. Defaults to zero, namely CRC inserted.
PAD_EN - When set, the LAN91C111 will pad transmit frames shorter than 64 bytes with 00. For TX,
CPU should write the actual BYTE COUNT before padded by the LAN91C111 to the buffer RAM, excludes
the padded 00. When this bit is cleared, the LAN91C111 does not pad frames.
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set
and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the
FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on the
line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal
operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of FORCOL, will reset TXENA to
0. In order to force another collision, TXENA must be set to 1 again.
LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY
chip in loopback mode.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the
LAN91C111 will complete the current transmission before stopping. When stopping due to an error, this bit
is automatically cleared.
Rev. 09/17/2002 Page 46 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.6 Bank 0 - EPH Status Register
OFFSET NAME TYPE SYMBOL
2 EPH STATUS REGISTER READ ONLY EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
HIGH
BYTE
LOW
BYTE
TX UNRN
0 -nLNK pin 0 0 0 0 0 0
TX
DEFR
0 0 0 0 0 0 0 0
LINK_
OK
LTX
BRD
Reserved
SQET 16COL
CTR
_ROL
EXC
_DEF
LTX
MULT
LOST
CARR
MUL
COL
LATCOL Reserved
SNGL
COL
TX_SUC
TXUNRN - Transmit Under Run. Set if under run occurs, it also clears TXENA bit in TCR. Cleared by
setting TXENA high. This bit may only be set if early TX is being used.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A
transition on the value of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15).
Cleared by reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/current transmit was deferred for more than 1518 * 2 byte
times. Cleared at the end of every packet sent.
LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64
byte times into the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in
TCR. Cleared by setting TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 µs of the inter frame
gap. Cleared at the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every
transmit frame.
SQET - Signal Quality Error Test. In MII, SQET bit is always set after first transmit, except if SWFDUP=1.
As a consequence, the STP_SQET bit in the TCR register cannot be set as it will always result in transmit
fatal error. The absence of this signal is a 'Signal Quality Error' and is reported in this status bit.
Transmission stops and EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit
is cleared by setting TXENA high.
16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR
is reset. Cleared when TXENA is set high.
LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of
every transmit frame.
MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was
experienced. Cleared when TX_SUC is high at the end of the packet being sent.
SMSC DS – LAN91C111 Rev. B Page 47 Rev. 09/17/2002
PRELIMINARY
Page 48
SNGLCOL - Single collision detected for the last transmit frame. Set when a collision is detected. Cleared
when TX_SUC is high at the end of the packet being sent.
TX_SUC - Last transmit was successful. Set if transmit completes without a fatal error. This bit is cleared
by the start of a new frame transmission or when TXENA is set high. Fatal errors are:
16 collisions (1/2 duplex mode only)
SQET fail and STP_SQET = 1 (1/2 duplex mode only)
FIFO Underrun
Carrier lost and MON_CSN = 1 (1/2 duplex mode only)
Late collision (1/2 duplex mode only)
8.7 Bank 0 - Receive Control Register
OFFSET NAME TYPE SYMBOL
4 RECEIVE CONTROL REGISTER READ/WRITE RCR
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
SOFT
RST
Reserved Reserved Reserved Reserved Reserved ALMUL PRMS
FILT
CAR
ABORT_E
NB
Reserved Reserved Reserved
10/100 Non-PCI Ethernet Single Chip MAC + PHY
STRIP
CRC
RXEN
RX_
ABORT
SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by
writing the bit low. The LAN91C111’s configuration is not preserved except for Configuration, Base, and
IA0-IA5 Registers. EEPROM is not reloaded after software reset.
FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times).
Otherwise recognizes a receive frame as soon as carrier sense is active. (Does NOT filter RX DV on MII!)
ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111
will automatically abort a packet being received when the appropriate collision input is activated. This bit
has no effect if the SWFDUP bit in the TCR is set.
STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory
following the packet. Defaults low.
RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle.
Defaults low on reset.
ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear
accepts only the multicast frames that match the multicast table setting. Defaults low.
PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission unless
it is in Full Duplex!
RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame
will not be received. The bit is cleared by RESET or by the CPU writing it low.
Reserved - Must be 0.
Rev. 09/17/2002 Page 48 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.8 Bank 0 - Counter Register
OFFSET NAME TYPE SYMBOL
6 COUNTER REGISTER READ ONLY ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All
counters are cleared when reading the register and do not wrap around beyond 15.
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
NUMBER OF EXC. DEFFERED TX NUMBER OF DEFFERED TX
MULTIPLE COLLISION COUNT SINGLE COLLISION COUNT
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS
REGISTER bit description, occurs. Note that the counters can only increment once per enqueued transmit
packet, never faster, limiting the rate of interrupts that can be generated by the counters. For example if a
packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented
by one. If a packet experiences between 2 to 16 collisions, the MULTIPLE COLLISION COUNT field is
incremented by one. If a packet experiences deferral the NUMBER OF DEFERRED TX field is
incremented by one, even if the packet experienced multiple deferrals during its collision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no
transmit interrupts are generated on successful transmissions.
Reading the register in the transmit service routine will be enough to maintain statistics.
8.9 Bank 0 - Memory Information Register
OFFSET NAME TYPE SYMBOL
8 MEMORY INFORMATION REGISTER READ ONLY MIR
HIGH
BYTE
0 0 0 0 0 1 0 0
LOW
BYTE
0 0 0 0 0 1 0 0
FREE MEMORY AVAILABLE (IN BYTES * 2K * M)
MEMORY SIZE (IN BYTES *2K * M)
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free
memory. The register defaults to the MEMORY SIZE upon POR (Power On Reset) or upon the RESET
MMU command.
MEMORY SIZE - This register can be read to determine the total memory size.
All memory related information is represented in 2K * M byte units, where the multiplier M is 1 for
LAN91C111.
SMSC DS – LAN91C111 Rev. B Page 49 Rev. 09/17/2002
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Page 50
8.10 Bank 0 - Receive/Phy Control Register
OFFSET NAME TYPE SYMBOL
A RECEIVE/PHY CONTROL
REGISTER
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
Reserved Reserved
LS2A LS1A LS0A LS2B LS1B LS0B Reserved Reserved
SPEED DPLX ANEG
SPEED – Speed select Input. This bit is valid and selects 10/100 PHY operation only when the ANEG Bit =
0, this bit overrides the SPEED bit in the PHY Register 0 (Control Register) and determine the speed
mode. When this bit is set (1), the Internal PHY will operate at 100Mbps. When this bit is cleared (0), the
Internal PHY will operate at 10Mbps. When the ANEG bit = 1, this bit is ignored and 10/100 operation is
determined by the outcome of the Auto-negotiation or this bit is overridden by the SPEED bit in the PHY
Register 0 (Control Register) when the ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex
operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control
Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at full
duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode. When the
ANEG bit = 1, this bit is ignored and duplex mode is determined by the outcome of the Auto-negotiation or
this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register) when the ANEG_EN bit in
the PHY Register 0 (Control Register) is clear.
READ/WRITE RPCR
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Reserved Reserved Reserved
ANEG – Auto-Negotiation mode select - The PHY is placed in Auto-Negotiation mode when the ANEG bit
and the ANEG_EN bit in PHY Register 0 (Control Register) both are set. When either of these bits is
cleared (0), the PHY is placed in manual mode.
WHAT DO YOU WANT
TO DO?
Try to Auto-Negotiate to
……
ANEG
Bit
RPCR
(MAC)
AUTO-
NEGOTIATION
CONTROL BITS
ANEG_EN
Bit
Register 0
(PHY)
AUTO-NEGOTIATION ADVERTISEMENT
TX_FDX
Bit
Register 4
(PHY)
REGISTER
TX_HDX
Bit
Register 4
(PHY)
10_FDX
Bit
Register 4
(PHY)
10_HDX
Bit
Register 4
(PHY)
DUPLEX
MODE
CONTROL
FOR THE MAC
SWFDUP
Bit
Transmit
Control Register
(MAC)
100 Full Duplex 1 1 1 1 1 1 1
100 Half Duplex 1 1 0 1 1 1 0
10 Full Duplex 1 1 0 0 1 1 1
10 Half Duplex 1 1 0 0 0 1 0
What do you want to do? Auto-Negotiation
Control bits
Speed and Duplex Mode Control for the PHY Duplex Mode
Control for the
MAC
Try to Manually Set to
……
ANEG
Bit
RPCR
(MAC
Bank 0
Offset
A)
ANEG_EN
Bit
Register 0
(PHY)
SPEED
Bit
RPCR
(MAC
Bank 0
Offset A)
DPLX
Bit
RPCR
(MAC
Bank 0
Offset A)
SPEED
Bit
Register 0
(PHY)
DPLX
Bit
Register 0
(PHY)
SWFDUP
Bit
Transmit
Control Register
(MAC)
Rev. 09/17/2002 Page 50 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
Page 51
10/100 Non-PCI Ethernet Single Chip MAC + PHY
WHAT DO YOU WANT
TO DO?
100 Full Duplex
100 Half Duplex
10 Full Duplex
10 Half Duplex
LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to
the LEDA output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2A LS1A LS0A LED SELECT SIGNAL – LEDA
0 0 0 nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0 0 1 Reserved
0 1 0 nPLED0 - 10Mbps Link detected
0 1 1 nPLED1 - Full Duplex Mode enabled
1 0 0 nPLED2 - Transmit or Receive packet occurred
1 0 1 nPLED3 - 100Mbps Link detected
1 1 0 nPLED4 - Receive packet occurred
1 1 1 nPLED5 - Transmit packet occurred
AUTO-
NEGOTIATION
CONTROL BITS
0 0 1 1 X X 1
0 1 1 1 X X 1
1 0 X X 1 1 1
0 0 1 0 X X 0
0 1 1 0 X X 0
1 0 X X 1 0 0
0 0 0 1 X X 1
0 1 0 1 X X 1
1 0 X X 0 1 1
0 0 0 0 X X 0
0 1 0 0 X X 0
1 0 X X 0 0 0
AUTO-NEGOTIATION ADVERTISEMENT
REGISTER
DUPLEX
MODE
CONTROL
FOR THE MAC
LS2B, LS1B, LS0B – LED select Signal Enable. These bits define what LED control signals are routed to
the LEDB output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2B LS1B LS0B LED SELECT SIGNAL – LEDB
0 0 0 nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0 0 1 Reserved
0 1 0 nPLED0 - 10Mbps Link detected
0 1 1 nPLED1 – Full Duplex Mode enabled
1 0 0 nPLED2 – Transmit or Receive packet occurred
1 0 1 nPLED3 - 100Mbps Link detected
1 1 0 nPLED4 - Receive packet occurred
1 1 1 nPLED5 - Transmit packet occurred
Reserved – Must be 0.
SMSC DS – LAN91C111 Rev. B Page 51 Rev. 09/17/2002
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Page 52
8.11 Bank 1 - Configuration Register
OFFSET NAME TYPE SYMBOL
0 CONFIGURATION REGISTER READ/WRITE CR
The Configuration Register holds bits that define the adapter configuration and are not expected to change
during run-time. This register is part of the EEPROM saved setup.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
HIGH
BYTE
1 0 1 0 0 0 0 0
LOW
BYTE
1 0 1 1 0 0 0 1
EPH
Power
EN
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
NO
WAIT
Reserved GPCNTRL EXT PHY Reserved
EPH Power EN - Used to selectively power transition the EPH to a low power mode. When this bit is
cleared (0), the Host will place the EPH into a low power mode. The Ethernet MAC will gate the 25Mhz TX
and RX clock so that the Ethernet MAC will no longer be able to receive and transmit packets. The Host
interface however, will still be active allowing the Host access to the device through Standard IO access.
All LAN91C111 registers will still be accessible. However, status and control will not be allowed until the
EPH Power EN bit is set AND a RESET MMU command is initiated.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the
Data Register if not ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to
the LAN91C111.
GPCNTRL - This bit is a general purpose output port. Its inverse value drives pin nCNTRL and it is
typically connected to a SELECT pin of the external PHY device such as a power enable. It can be used to
select the signaling mode for the external PHY or as a general purpose non-volatile configuration pin.
Defaults low.
EXT PHY – External PHY Enabled.
This bit, when set (1):
a) Enables the external MII.
b) The Internal PHY is disabled and is disconnected (Tri-stated from the internal MII along with any
sideband signals (such as MDINT) going to the MAC Core).
When this bit is cleared (0 - Default):
a) The internal PHY is enabled.
b) The external MII pins, including the MII Management interface pins are tri-stated.
Reserved – Reserved bits.
Rev. 09/17/2002 Page 52 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.12 Bank 1 - Base Address Register
OFFSET NAME TYPE SYMBOL
2 BASE ADDRESS REGISTER READ/WRITE BAR
This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM
saved setup and is not usually modified during run-time.
HIGH
BYTE
0 0 0 1 1 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 1
A15 A14 A13 A9 A8 A7 A6 A5
Reserved Reserved
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the
IOBASE for the LAN91C111‘s registers. The 64k I/O space is fully decoded by the LAN91C111 down to a
16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros.
All bits in this register are loaded from the serial EEPROM. The I/O base decode defaults to 300h
(namely, the high byte defaults to 18h).
Reserved – Reserved bits.
Below chart shows the decoding of I/O Base Address 300h:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
8.13 Bank 1 - Individual Address Registers
OFFSET NAME TYPE SYMBOL
4 THROUGH 9 INDIVIDUAL ADDRESS
REGISTERS
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM
reload. The registers can be modified by the software driver, but a STORE operation will not modify the
EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds to the first bit of
the address on the cable.
READ/WRITE IAR
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
SMSC DS – LAN91C111 Rev. B Page 53 Rev. 09/17/2002
ADDRESS 0
ADDRESS 1
ADDRESS 2
ADDRESS 3
ADDRESS 4
ADDRESS 5
PRELIMINARY
Page 54
8.14 Bank 1 - General Purpose Register
OFFSET NAME TYPE SYMBOL
A GENERAL PURPOSE REGISTER READ/WRITE GPR
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be
used by the software driver. The storage is word oriented, and the EEPROM word address to be read or
written is specified using the six lowest bits of the Pointer Register.
This register can also be used to sequentially program the Individual Address area of the EEPROM, that is
normally protected from accidental Store operations.
This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control
Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of
the LAN91C111.
HIGH DATA BYTE
LOW DATA BYTE
10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.15 Bank 1 - Control Register
OFFSET NAME TYPE SYMBOL
C CONTROL REGISTER READ/WRITE CTR
HIGH
BYTE
0 0 0 1 0 0 1 0
LOW BYTE
0 0 0 1 0 0 0 0
Reserved
LE
ENABLE
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate
interrupts and their memory is released.
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was
successful (when TX_SUC is set). In that case there is no status word associated with its packet number,
and successful packet numbers are not even written into the TX COMPLETION FIFO. A sequence of
transmit packets will generate an interrupt only when the sequence is completely transmitted (TX EMPTY
INT will be set), or when a packet in the sequence experiences a fatal error (TX INT will be set). Upon a
fatal error TXENA is cleared and the transmission sequence stops. The packet number that failed, is
present in the FIFO PORTS register, and its pages are not released, allowing the CPU to restart the
sequence after corrective action is taken.
LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts
merged into the EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused by a
LINK_OK transition, will acknowledge the interrupt. LE ENABLE defaults low (disabled).
RCV_
BAD
CR
ENABLE
Reserved Reserved
TE
ENABLE
AUTO
RELEASE
Reserved Reserved
Reserved Reserved Reserved
EEPROM
SELECT
RELOAD STORE
CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts
merged into the EPH INT bit. Reading the COUNTER register after an EPH INT interrupt caused by a
counter rollover, will acknowledge the interrupt. CR ENABLE defaults low (disabled).
TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged
into the EPH INT bit. An EPH INT interrupt caused by a transmitter error is acknowledged by setting
Rev. 09/17/2002 Page 54 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
TXENA bit in the TCR register to 1 or by clearing the TE ENABLE bit. TE ENABLE defaults low (disabled).
Transmit Error is any condition that clears TXENA with TX_SUC staying low as described in the EPHSR
register.
EEPROM SELECT - This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE
refers to. When high, the General Purpose Register is the only register read or written. When low,
RELOAD reads Configuration, Base and Individual Address, and STORE writes the Configuration and
Base registers.
RELOAD - When set it will read the EEPROM and update relevant registers with its contents. Clears upon
completing the operation.
STORE - When set, stores the contents of all relevant registers in the serial EEPROM. Clears upon
completing the operation.
Note
: When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high. The
remaining 14 bits of this register will be invalid. During this time attempted read/write operations, other than
polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume
accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET
or by software takes less than 750 µs.
8.16 Bank 2 - MMU Command Register
OFFSET NAME TYPE SYMBOL
0 MMU COMMAND REGISTER WRITE ONLY
MMUCR
BUSY Bit Readable
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO
control.
The three command bits determine the command issued as described below:
HIGH
BYTE
LOW
BYTE
Operation Code
0
COMMAND Reserved Reserved Reserved Reserved BUSY
COMMAND SET:
OPERATION
CODE
DECIMAL
VALUE
COMMAND
000 0 NOOP - NO OPERATION
001 1 ALLOCATE MEMORY FOR TX
010 2 RESET MMU TO INITIAL STATE - Frees all memory allocations, clears
relevant interrupts, resets packet FIFO pointers.
011 3 REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU
has completed processing of present receive frame. This command
removes the receive packet number from the RX FIFO and brings the
next receive frame (if any) to the RX area (output of RX FIFO).
SMSC DS – LAN91C111 Rev. B Page 55 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
OPERATION
CODE
100 4 REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases
101 5 RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet
110 6 ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method
111 7 RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO
:
Notes
When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet
number has memory allocated to it.
COMMAND SEQUENCING
DECIMAL
VALUE
COMMAND
all memory used by the packet presently at the RX FIFO output. The
MMU busy time after issuing REMOVE and RELEASE command
depends on the time when the busy bit is cleared. The time from issuing
REMOVE and RELEASE command on the last receive packet to the time
when receive FIFO is empty depends on RX INT bit turning low. An
alternate approach can be checking the read RX FIFO register.
specified in the PACKET NUMBER REGISTER. Should not be used for
frames pending transmission. Typically used to remove transmitted frames,
after reading their completion status. Can be used following 3) to release
receive packet memory in a more flexible way than 4).
of transmitting a packet just loaded into RAM. The packet number to be
enqueued is taken from the PACKET NUMBER REGISTER.
holding the packet numbers awaiting transmission and the TX Completion
FIFO. This command provides a mechanism for canceling packet
transmissions, and reordering or bypassing the transmit queue. The RESET
TX FIFOs command should only be used when the transmitter is disabled.
Unlike the RESET MMU command, the RESET TX FIFOs does not release
any memory.
A second allocate command (command 1) should not be issued until the present one has completed.
Completion is determined by reading the FAILED bit of the allocation result register or through the
allocation interrupt.
A second release command (commands 4, 5) should not be issued if the previous one is still being
processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the
contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3
should not be issued until BUSY goes low.
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still
processing a release command. When clear, MMU has already completed last release command. BUSY
and FAILED bits are set upon the trailing edge of command.
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8.17 Bank 2 - Packet Number Register
OFFSET NAME TYPE SYMBOL
2 PACKET NUMBER REGISTER READ/WRITE PNR
Reserved Reserved
0 0 0 0 0 0 0 0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is
accessible through the TX area. Some MMU commands use the number stored in this register as the
packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
OFFSET NAME TYPE SYMBOL
3 ALLOCATION RESULT REGISTER READ ONLY ARR
This register is updated upon an ALLOCATE MEMORY MMU command.
FAILED
1 0 0 0 0 0 0 0
Reserved
PACKET NUMBER AT TX AREA
ALLOCATED PACKET NUMBER
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only
cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For
polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is
synchronized to the read operation. Sequence:
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1) Allocate Command
2) Poll ALLOC_INT bit until set
3) Read Allocation Result Register
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request.
The value is only valid if the FAILED bit is clear.
: For software compatibility with future versions, the value read from the ARR after an allocation request is
Note
intended to be written into the PNR as is, without masking higher bits (provided FAILED = 0).
8.18 Bank 2 - FIFO Ports Register
OFFSET NAME TYPE SYMBOL
4 FIFO PORTS REGISTER READ ONLY FIFO
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO.
The packet numbers to be processed by the interrupt service routines are read from this register.
HIGH
BYTE
1 0 0 0 0 0 0 0
LOW
BYTE
1 0 0 0 0 0 0 0
REMPTY Reserved RX FIFO PACKET NUMBER
TEMPTY Reserved TX FIFO PACKET NUMBER
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the
Interrupt Status Register.
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid
if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the
Interrupt Status Register.
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if
TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.
Note
: For software compatibility with future versions, the value read from each FIFO register is intended to be
written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
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8.19 Bank 2 - Pointer Register
OFFSET NAME TYPE SYMBOL
6 POINTER REGISTER READ/WRITE
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
RCV
POINTER REGISTER - The value of this register determines the address to be accessed within the
transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.
The increment is by one for every byte access, by two for every word access, and by four for every double
word access. When RCV is set the address refers to the receive area and uses the output of RX FIFO as
the packet number, when RCV is clear the address refers to the transmit area and uses the packet number
at the Packet Number Register.
READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If
the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high,
generates a pre-fetch into the Data Register for read purposes.
AUTO
INCR.
READ ETEN
NOT EMPTY is a read
NOT
EMPTY
POINTER LOW
PTR
only bit
POINTER HIGH
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the
last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without
affecting the process being interrupted. The Pointer Register should not be loaded until the Data Register
FIFO is empty. The NOT EMPTY bit of this register can be read to determine if the FIFO is empty. On
reads, if ARDY is not connected to the host, the Data Register should not be read before 370ns after the
pointer was loaded to allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
ETEN - When set enables EARLY Transmit underrun detection. Normal operation when clear.
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO
is empty before loading a new pointer value. This is a read only bit.
Note
: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
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8.20 Bank 2 - Data Register
OFFSET NAME TYPE SYMBOL
8 THROUGH Bh DATA REGISTER READ/WRITE DATA
X X X X X X X X
X X X X X X X X
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer
register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the
LAN91C111 regardless of whether the pointer address is even, odd or dword aligned. Data goes through
the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are
used, the appropriate (next) byte can be accessed through the Data Low or Data High registers. The order
to and from the FIFO is preserved. Byte, word and dword accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate double word move operations
regardless of the actual bus width (16 or 32 bits). The DATA register is accessible at any address in the 8
through Bh range, while the number of bytes being transferred is determined by A1 and nBE0-nBE3. The
FIFOs are 12 bytes each.
10/100 Non-PCI Ethernet Single Chip MAC + PHY
DATA HIGH
DATA LOW
8.21 Bank 2 - Interrupt Status Registers
OFFSET NAME TYPE SYMBOL
C INTERRUPT STATUS REGISTER READ ONLY IST
MDINT ERCV INT EPH INT
0 0 0 0 0 1 0 0
OFFSET NAME TYPE SYMBOL
C INTERRUPT ACKNOWLEDGE
REGISTER
MDINT ERCV INT
OFFSET NAME TYPE SYMBOL
D INTERRUPT MASK REGISTER READ/WRITE MSK
MDINT
MASK
0 0 0 0 0 0 0 0
ERCV INT
MASK
EPH INT
MASK
RX_OVRN
INT
RX_OVRN
INT
RX_OVRN
INT
MASK
ALLOC INT
ALLOC INT
MASK
TX EMPTY
INT
TX INT RCV INT
WRITE ONLY ACK
TX EMPTY
INT
TX EMPTY
INT
MASK
TX INT
TX INT
MASK
RCV INT
MASK
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This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register)
change state.
1) LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.
These bits automatically latch upon changing state and stay latched until they are read. When they are
read, the bits that caused the interrupt to happen are updated to their current value. The MDINT bit will be
cleared by writing the acknowledge register with MDINT bit set.
ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of
bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch).
ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the
ERCV INT bit set.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special
conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the
execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH
Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The
possible sources are:
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the
specific reason will be reflected by the bits:
TXUNRN - Transmit under-run
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error
Enable)
EPH INT will only be cleared by the following methods:
Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK
transition.
Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.
Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above
(3.1 to 3.5).
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2)
the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the
RCV DISCRD bit in the ERCV register set. The RX_OVRN INT bit latches the condition for the purpose of
being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with
the RX_OVRN INT bit set.
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ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement of the
FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the
next allocation request is processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a
sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay
set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a
real time reading of the FIFO empty is desired, the bit should be first cleared and then read.
The TX_EMPTY MASK bit should only be set after the following steps:
A packet is enqueued for transmission
The previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
TXUNRN - Transmit under-run
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit
set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read
from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the
FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
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FIGURE 15 - INTERRUPT STRUCTURE
SMSC DS – LAN91C111 Rev. B Page 63 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.22 Bank 3 - Multicast Table Registers
OFFSET NAME TYPE SYMBOL
0 THROUGH 7 MULTICAST TABLE READ/WRITE MT
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
HIGH
BYTE
0 0 0 0 0 0 0 0
MULTICAST TABLE 0
MULTICAST TABLE 1
MULTICAST TABLE 2
MULTICAST TABLE 3
MULTICAST TABLE 4
MULTICAST TABLE 5
MULTICAST TABLE 6
MULTICAST TABLE 7
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most
significant bits of the CRC of the destination addresses. The three msb's determine the register to be used
(MT0-MT7), while the other three determine the bit within the register.
If the appropriate bit in the table is set, the packet is received.
If the ALMUL bit in the RCR register is set, all multicast addresses are received regardless of the multicast
table values.
Hashing is only a partial group addressing filtering scheme, but being the hash value available as part of
the receive status word, the receive routine can reduce the search time significantly. With the proper
memory structure, the search is limited to comparing only the multicast addresses that have the actual
hash value in question.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
8.23 Bank 3 - Management Interface
OFFSET NAME TYPE SYMBOL
8 MANAGEMENT INTERFACE READ/WRITE MGMT
HIGH
BYTE
0 0 1 1 0 0 1 1
LOW
BYTE
0 0 1 1 0 0 MDI Pin 0
Reserved
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated.
MSK_
CRS100
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved MDOE MCLK MDI MDO
The purpose of this interface, along with the corresponding pins is to implement MII PHY management in
software.
8.24 Bank 3 - Revision Register
OFFSET NAME TYPE SYMBOL
A REVISION REGISTER READ ONLY REV
HIGH
BYTE
0 0 1 1 0 0 1 1
LOW
BYTE
1 0 0 1 0 0 0 1
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
CHIP REV
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8.25 Bank 3 - Early RCV Register
OFFSET NAME TYPE SYMBOL
C EARLY RCV REGISTER READ/WRITE ERCV
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 1 1 1 1 1
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being
received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will
be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0
set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing.
ERCV THRESHOLD - Threshold for ERCV interrupt. Specified in 64 byte multiples. Whenever the number
of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT
bit of the INTERRUPT STATUS REGISTER is set.
RCV
DISCRD
Reserved Reserved ERCV THRESHOLD
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Reserved
8.26 Bank 7 - External Registers
OFFSET NAME TYPE SYMBOL
0 THROUGH 7 EXTERNAL REGISTERS
nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range
occurs.
HIGH
BYTE
LOW
BYTE
CYCLE NCSOUT LAN91C111 DATA BUS
AEN=0
A3=0
Driven low. Transparently latched on
nADS rising edge.
A4-15 matches I/O BASE
BANK SELECT = 7
BANK SELECT = 4,5,6 High Ignore cycle.
Otherwise High Normal LAN91C111 cycle.
EXTERNAL R/W REGISTER
EXTERNAL R/W REGISTER
Ignored on writes.
Tri-stated on reads.
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Chapter 9 PHY MII Registers
Multiple Register Access
Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register
access features. The multiple register access features can be enabled by setting the multiple register
access enables bit in the PHY Ml serial port Configuration 2 register. When multiple register access is
enabled, multiple registers can be accessed on a single PHY Ml serial port access cycle by setting the
register address to 11111 during the first 16 MDC clock cycles. There is no actual register residing in
register address location 11111, so when the register address is then set to 11111, all eleven registers are
accessed on the 176 rising edges of MDC that occur after the first 16 MDC clock cycles of the PHY Ml
serial port access cycle. The registers are accessed in numerical order from 0 to 20. After all 192 MDC
clocks have been completed, all the registers have been read/written, and the serial shift process is halted,
data is latched into the device, and MDIO goes into high impedance state. Another serial shift cycle
cannot be initiated until the idle condition (at least 32 continuous 1's) is detected.
Bit Types
Since the serial port is bi-directional, there are many types of bits. Write bits (W) are inputs during a write
cycle and are high impedance during a read cycle. Read bits (R) are outputs during a read cycle and high
impedance during a write cycle. Read/Write bits (RW) are actually write bits, which can be read out during
a read cycle. R/WSC bits are R/W bits that are self-clearing after a set period of time or after a specific
event has completed. R/LL bits are read bits that latch themselves when they go low, and they stay
latched low until read. After they are read, they are reset high. R/LH bits are the same as R/LL bits except
that they latch high. R/LT are read bits that latch themselves whenever they make a transition or change
value, and they stay latched until they are read. After R/LT bits are read, they are updated to their current
value. R/LT bits can also be programmed to assert the interrupt function.
Bit Type Definition
R: Read Only R/WSC: Read/Write Self Clearing
W: Write Only R/LH: Read/Latch high
RW: Read/Write R/LL: Read/Latch low
R/LT: Read/Latch on Transition
REGISTER ADDRESS REGISTER NAME
0 Control
1 Status
2,3 PHY ID
4 Auto-Negotiation Advertisement
5 Auto-Negotiation Remote End Capability
6....15 Reserved
16 Configuration 1
17 Configuration 2
18 Status Output
19 Mask
20 Reserved
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PHY Register Description
Table 5 - MII Serial Frame Structure
<Idle> <Start> <Read> <Write> <PHY Addr.> <REG.Addr.> <Turnaround> <Data>
IDLE ST[1:0] READ WRITE PHYAD[4:0] REGAD[4:0] TA[1:0] D[15:0]
D[15:0]
↓
Register 0 Control
Register 1 Status
Register 2 PHY ID#1
Register 3 PHY ID#2
Register 4 AutoNegotiation Advertisement
Register 5 AutoNegotiation Remote End Capability
Register 16 Configuration 1
Register 17 Configuration 2
Register 18 Status Output
Register 19 Mask
Register 20 Reserved
SYMBOL NAME DEFINITION R/W
IDLE Idle Pattern These bits are an idle pattern. Device will not initiate an MI cycle
until it detects at least 32 1's
ST1
ST0
READ Read Select 1 = Read Cycle W
WRITE Write Select 1 = Write Cycle W
PHYAD[4:0] Physical
Start Bits When ST[1:0]=01, a MI Serial Port access cycle starts. W
PHYSICAL ADDRESS R
Device
Address
W
REGAD[4:0] Register
Address
Rev. 09/17/2002 Page 68 SMSC DS – LAN91C111 Rev. B
If REGAD[4:0] = 00000-11110, these bits determine the specific
register from which D[15:0] is read/written. If multiple register
access is enabled and REGAD[4:0] = 11111, all registers are
read/written in a single cycle.
W
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
SYMBOL NAME DEFINITION R/W
TA1
TA0
D[15:0].... Data These 16 bits contain data to/from one of the eleven registers
Turnaround
Time
These bits provide some turnaround time for MDIO
When READ = 1, TA[1:0] = Z0
When WRITE = 1, TA[1:0] = 10
The turnaround time is a 2 bit time spacing between the Register
Address field and the Data field of a management frame to avoid
contention during a read transaction. For a read transaction, both
the STA and the PHY shall remain in a high impedance state for the
first bit time of the turnaround. The PHY shall drive a zero bit during
the second bit time of the turnaround of a read transaction. During a
write transaction, the STA shall drive a one bit for the first bit time of
the turnaround and a zero bit for the second bit time of the
turnaround.
selected by register address bits REGAD[4:0].
R/W
Any
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Table 6 - MII Serial Port Register MAP
10/100 Non-PCI Ethernet Single Chip MAC + PHY
0
R/W
0
R/W
Reserved Reserved
0
Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved ReservedReserved
0
00
11
RRRRRR RR
R/WR/W R/W R/WR/W R /W R/WR/W
10_FDXTX_HDXTX_FDXT4RFNP ACK 10_HDX CSMA
100000 00 0110 00
R/WR/WR/W R/WR/W R R/WR/W
RLVL0CABLEEQLZRUNSCDSXMTPDNLNKDIS XM TDIS ReservedReserved TLVL1 TRF1TLVL3 TLVL2 TRF0TLVL0BYPSCR
10_FDXTX_HDXTX_FDXT4RFNP ACK 10_HDX CSMA
000000 00 00000
RRRRRR RR
Reserved
ReservedReserved
00
00
00
RRRRRR/LH R/LHR/LL
x.6x.7x.8x.9x.13 x.10x.15 x.14 x.11x.12 x.3 x.0x.5 x.4 x. 1x.2
R/WR/W R/W R/ WR/W R/W R/WR/W
Reserved
CAP_SUPR
COLTSTDPLXANEG_RSTSPEEDRST LPBK PDNANEG_EN MII_DIS
ReservedReservedReservedReserved
0011 or 000 01 0000 00
R/WR/WSCR/W R/ WR/WSC R/W R/WR/W
RRRRRR RR
OUI12OUI11OUI10OUI9OUI5OUI3 OUI4 OUI 7OUI6 OUI15 OUI17OUI13 OUI14 OUI18OUI16OUI8
001001 11 1100 00
RRRRRR RR
RRRRRR RR
10
RRRRRR RR
PART2PART3PART4PART5OUI21OUI19 OUI2 0 OUI23OUI2 2 REV3 REV1PART1 PART0 REV0REV2OUI24
000000 00 0001 11
001011 11 0000 00
RRRRRR RR
R/W
0
R/W
0
R/W
0
R/W
APOLDIS JABDIS MREG INTMDIO
00
R/WR/W R/W R/WR/W R /W R/WR/W
000000 00 0010 10
R/WR/WR/W R/WR/W R/W R/WR/W
Reserved Reserved Reserved Reserved
0
R/W
DPLXDETSPDDETJABRPOL
01
1
R/W
1
R/W
Reserved
R/WR/W
R/W R/W
Reserved Reserved Reserved
R/WR/W
ReservedReserved
R/W
01
R/LTR/LT R RR/LT R/LT RR
000001 00 0000 00
R/LTR/LTR/LT R/LTR R/LT R/LTR/LT
MDPLDTMSPDDT
MJAB
MRPOLMLOSSSYNMLNKFAI L MSSDMCWRD MESD
11
R/W
R/W
1111111 0000 00
R/WR/WR/W R/WR/W R/WR/W
0
R/W
0
R/W
0
R/W
010
R/W
01
R/WR/W R/W R/W
0000
R/WR/WR/W R/WR/WR/W
111 11
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved
Reserved Reserved
Configuration 2
17
R/W
R/WR/W R/W R/WR/W R/W
LOSSSYNC
000
R/W
INT LNKFAIL SSDCWRD ESD
Status
18
1
MINT
Output
Mask
19
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved
20
0
R/W
Reserved
Reserved
Reserved Reserved
Reserved Reserved
CAP_TXHCAP_T4 CAP_ TXF CAP_THCAP_TF CAP_ANEG JABANEG_ACK REM_ FLT EXREGLINK
Remote
Control
Status
0
PHY ID #1
1
2
AutoNegot.
PHY ID #2
4
3
Capability
Advertisement
AutoNegot.
5
Configuration 1
16
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9.1 Register 0. Control Register
RST LPBK SPEED ANEG_EN PDN MII_DIS ANEG_RST DPLX
RW, SC RW RW RW RW RW RW. SC RW
0 0 1 1 0 1 0 0
COLST Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RW RW RW RW RW RW RW RW
0 0 0 0 0 0 0 0
RST - Reset
A ‘1’ written to this bit will initiate a reset of the PHY. The bit is self-clearing, and the PHY will return a ‘1’ on
reads to this bit until the reset is completed. Write transactions to this register may be ignored while the
PHY is processing the reset. All PHY registers will be driven to their default states after a reset. The
internal PHY is guaranteed to be ready for normal operation 50 mS after the RST bit is set. Software
driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again.
LPBK - Loopback
Writing a ‘1’ will put the PHY into loopback mode.
Speed (Speed Selection)
When Auto Negotiation is disabled this bit can be used to manually select the link speed. Writing a ‘1’ to
this bit selects 100 Mbps, a ‘0’ selects 10 Mbps.
When Auto-Negotiation is enabled reading or writing this bit has no meaning/effect.
ANEN_EN - Auto-Negotiation Enable
Auto-negotiation (ANEG) is on when this bit is ‘1’. In that case the contents of bits Speed and Duplex are
ignored and the ANEG process determines the link configuration.
PDN - Power down
Setting this bit to ‘1’ will put the PHY in PowerDown mode. In this state the PHY will
management transactions.
MII_DIS - MII DISABLE
Setting this bit will set the PHY to an isolated mode in which it will respond to MII management frames over
the MII management interface but will ignore data on the MII data interface. The internal PHY is placed in
isolation mode at power up and reset. It can be removed from isolation mode by clearing the MII_DIS bit
in the PHY Control Register. If necessary, the internal PHY can be enabled by clearing the EXT_PHY bit
in the Configuration Register.
ANEG_RST - Auto-Negotiation Reset
respond to
This bit will return 0 if the PHY does not support ANEG or if ANEG is disabled through the ANEG_EN bit. If
neither of the previous is true, setting this bit to ‘1’ resets the ANEG process. This bit is self clearing and
the PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG process.
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DPLX - Duplex mode
When Auto Negotiation is disabled this bit can be used to manually select the link duplex state. Writing a
‘1’ to this bit selects full duplex while a ‘0’ selects half duplex.
When Auto-Negotiation is enabled reading or writing this bit has no effect.
COLTST - Collision test
Setting a ‘1’ allows for testing of the MII COL signal. ‘0’ allows normal operation.
Reserved: Reserved, Must be 0 for Proper Operation
9.2 Register 1. Status Register
CAP_T4 CAP_TXF CAP_TXH CAP_TF CAP_TH Reserved Reserved. Reserved
R R R R R R R R
0 1 1 1 1 0 0 0
Reserved CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG LINK JAB EXREG
R R R R, LH R R, LL R, LH R
0 0 0 0 1 0 0 1
CAP_T4 - 100BASE-T4 Capable
‘1’ Indicates 100Base-T4 capable PHY, ‘0’ not capable.
CAP_TXF - 100BASE-TX Full Duplex Capable
‘1’ Indicates 100Base-X full duplex capable PHY, ‘0’ not capable.
CAP_TXH - 100BASE-TX Half Duplex Capable
‘1’ Indicates 100Base-X alf duplex capable PHY, ‘0’ not capable.
CAP_TF - 10BASE-T Full Duplex Capable
‘1’ Indicates 10Mbps full duplex capable PHY, ‘0’ not capable.
CAP_TH - 10BASE-T Half Duplex Capable
‘1’ Indicates 10Mbps half duplex capable PHY, ‘0’ not capable.
Reserved: Reserved, Must be 0 for Proper Operation.
CAP_SUPR - MI Preamble Suppression Capable
‘1’ indicates the PHY is able to receive management frames even if not preceded by a preamble. ‘0’ when
it is not able.
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ANEG_ACK - Auto-Negotiation Acknowledgment
When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are valid.
‘0’ means ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY
returns zero if ANEG is disabled.
REM_FLT- Remote Fault Detect
‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or reseting the
PHY.
CAP_ANEG - AutoNegotiation Capable
Indicates the ability (‘1’) to perform ANEG or not (‘0’).
LINK - Link Status
A ‘1’ indicates a valid Link and a ‘0’ and invalid Link. The ‘0’ condition is latched until this register is read.
JAB - Jabber Detect
Jabber condition detected when ‘1’ for 10Mbps. ‘1’ latched until this register is read or the PHY is reset.
Always ‘0’ for 100Mbps
EXREG - Extended Capability register
‘1’ Indicates extended registers are implemented
9.3 Register 2&3. PHY Identifier Register
These two registers (offsets 2 and 3) provide a 32-bit value unique to the PHY.
REG BITS NAME DEFAULT VALUE R/W SOFT RESET
2 15-0 Company ID 0000000000010110 R Retains Original Value
3 15-10 Company ID 111110 R Retains Original Value
3 9-4 Manufacturer's ID 000100 R Retains Original Value
3 3-0 Manufacturer's Revision # - - - - R Retains Original Value
9.4 Register 4. Auto-Negotiation Advertisement Register
NP ACK RF Reserved Reserved Reserved T4 TX_FDX
RW R RW RW RW RW RW RW
0 0 0 0 0 0 0 1
TX_HDX 10_FDX 10_HDX Reserved Reserved Reserved Reserved CSMA
RW RW RW RW RW RW RW RW
1 1 1 0 0 0 0 1
This register control the values transmitted by the PHY to the remote partner when advertising its abilities
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NP - Next Page
A ‘1’ indicates the PHY wishes to exchange Next Page information.
ACK - Acknowledge
It is used by the Auto-negotiation function to indicate that a device has successfully received its Link
Partner’s Link code Word.
RF - Remote Fault
When set, an advertisement frame will be sent with the corresponding bit set. This in turn will cause the
PHY receiving it to set the Remote Fault bit in its Status register
T4 - 100BASE-T4
A '1' indicates the PHY is capable of 100BASE-T4
TX_FDX - 100BASE-TX Full Duplex Capable
A '1' indicates the PHY is capable of 100BASE-TX Full Duplex
TX_HDX - 100BASE-TX Half Duplex Capable
A '1' indicates the PHY is capable of 100BASE-TX Half Duplex
10_FDX - 10BASE-T Full Duplex Capable
A '1' indicates the PHY is capable of 10BASE-T Full Duplex
10_HDX - 10BASE-T Half Duplex Capable
A '1' indicates the PHY is capable of 10BASE-T Half Duplex
The management entity sets the value of this field prior to AutoNegotiation.
‘1’ in these bit indicates that the mode of operation that corresponds to these will be acceptable to be autonegotiated to. Only modes supported by the PHY can be set.
CSMA
A '1' indicates the PHY is capable of 802.3 CSMA Operation
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9.5 Register 5. Auto-Negotiation Remote End Capability Register
NP ACK RF Reserved Reserved Reserved T4 TX_FDX
R R R R R R R R
0 0 0 0 0 0 0 0
TX_HDX 10_FDX 10_HDX Reserved Reserved Reserved Reserved CSMA
R R R R R R R R
0 0 0 0 0 0 0 0
The bit definitions are analogous to the Auto Negotiation Advertisement Register.
9.6 Register 16. Configuration 1-- Structure and Bit Definition
LNKDIS XMTDIS XMTPDN Reserved Reserved BYPSCR UNSCDS EQLZR
RW RW RW RW RW RW RW RW
0 0 0 0 0 0 0 0
CABLE RLVL0 TLVL3 TLVL2 TLVL1 TLVL0 TRF1 TRF0
RW RW RW RW RW RW RW RW
0 0 1 0 0 0 1 0
LNKDIS: Link Disable 1 = Receive Link Detect Function Disabled (Force Link Pass)
0 = Normal
XMTDIS: TP Transmit 1 = TP Transmitter Disabled
0 = Normal
XMTPDN: TP Transmit 1 = TP Transmitter Powered Down
Powerdown 0 = Normal
RESERVED: RESERVED Reserved, Must be 0 for Proper Operation
BYPSCR: Bypass 1 = Bypass Scrambler/Descrambler
Scrambler/Descr- 0 = No Bypass
ambler Select
UNSCDS: Unscrambled Idle 1 = Disable AutoNegotiation with devices that transmit unscrambled
Reception Disable idle on powerup and various instances
0 = Enables AutoNegotiation with devices that transmit unscrambled idle on
powerup and various instances
EQLZR: Receive Equalizer 1 = Receive Equalizer Disabled, Set To 0 Length
Select 0 = Receive Equalizer On (For 100MB Mode Only)
CABLE Cable Type Select 1 = STP (150 Ohm)
0 = UTP (100 Ohm)
RLVL0 Receive Input 1 = Receive Squelch Levels Reduced By 4.5 dB R/W
Level Adjust 0 = Normal
TLVL0-3 Transmit OutputSee Table 3
Level Adjust
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TRF0-1 Transmitter 11 = -0.25nS
Rise/Fall Time 10 = +0.0nS
Adjust 01 = +0.25nS
00 = +0.50nS
9.7 Register 17. Configuration 2 - Structure and Bit Definition
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R R R R R R R R
1 1 1 1 1 1 1 1
Reserved Reserved APOLDIS JABDIS MREG INTMDIO Reserved Reserved
R R RW RW RW RW RW RW
0 0 0 0 0 0 0 0
APOLDIS: Auto Polarity Disable 1 = Auto Polarity Correction Function Disabled
0 = Normal
JABDIS: Jabber Disable Select 1 = Jabber Disabled R/W
0 = Enabled
MREG: Multiple Register Access Enable 1 = Multiple Register Access Enabled
0 = No Multiple Register Access
INTMDIO: Interrupt Scheme Select 1 = Interrupt Signaled With MDIO Pulse During Idle
0 = Interrupt Not Signaled On MDIO
Reserved: Reserved for Factory Use
9.8 Register 18. Status Output - Structure and Bit Definition
INT LNKFAIL LOSSSYNC CWRD SSD ESD RPOL JAB
R R/LT R/LT R/LT R/LT R/LT R/LT R/LT
0 0 0 0 0 0 0 0
SPDDET DPLXDET Reserved Reserved Reserved Reserved Reserved Reserved
R/LT R/LT R R
1 0 0 0 0 0 0 0
INT: Interrupt Detect 1 = Interrupt Bit(s) Have Changed Since Last Read Operation.
0 = No Change
LNKFAIL: Link Fail Detect 1 = Link Not Detected
0 = Normal
LOSSSYNC: Descrambler Loss of 1 = Descrambler Has Lost Synchronization
Synchronization Detect 0 = Normal
CWRD: Codeword Error 1 = Invalid 4B5B Code Detected On Receive Data
0 = Normal
SSD: Start Of Stream Error 1 = No Start Of Stream Delimiter Detected on Receive Data
0 = Normal
ESD: End Of Stream Error 1 = No End Of Stream Delimiter Detected on Receive Data
0 = Normal
R
R R R
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RPOL: Reverse Polarity Detect 1 = Reverse Polarity Detected
0 = Normal
JAB: Jabber Detect 1 = Jabber Detected
0 = Normal
SPDDET: 100/10 Speed Detect 1 = Device in 100Mbps Mode (100BASE-TX)
0 = Device in 10Mbps Mode (10BASE-T)
DPLXDET: Duplex Detect 1 = Device In Full Duplex
0 = Device In Half Duplex
Reserved: Reserved Reserved for Factory Use
9.9 Register 19. Mask - Structure and Bit Definition
MINT MLNKFAIL MLOSSSYN MCWRD MSSD MESD MRPOL MJAB
RW RW RW RW RW RW RW RW
1 1 1 1 1 1 1 1
MSPDDT MDPLDT Reserved Reserved Reserved Reserved Reserved Reserved
RW RW RW RW RW RW RW RW
1 1 0 0 0 0 0 0
MINT: Interrupt Mask Interrupt Detect 1 = Mask Interrupt For INT In Register 18
0 = No Mask
MLNKFAIL: Interrupt Mask Link Fail Detect 1 = Mask Interrupt For LNKFAIL In Register 18
0 = No Mask
MLOSSSYN: Interrupt Mask Descrambler Loss 1 = Mask Interrupt For LOSSSYNC In Register 18
of Synchronization Detect 0 = No Mask
MCWRD: Interrupt Mask Codeword Error 1 = Mask Interrupt For CWRD In Register 18
0 = No Mask
MSSD: Interrupt Mask Start Of Stream Error 1 = Mask Interrupt For SSD In Register 18
0 = No Mask
MESD: Interrupt Mask End Of Stream Error 1 = Mask Interrupt For ESD In Register 18
0 = No Mask
MRPOL: Interrupt Mask Reverse Polarity Detect 1 = Mask Interrupt For RPOL In Register 18
0 = No Mask
MJAB: Interrupt Mask Jabber Detect 1 = Mask Interrupt For JAB In Register 18
0 = No Mask
MSPDDT: Interrupt Mask 100/10 Speed Detect 1 = Mask Interrupt For SPDDET In Register 18
0 = No Mask
MDPLDT: Interrupt Mask Duplex Detect 1 = Mask Interrupt For DPLXDET In Register 18
0 = No Mask
Reserved: Reserved Reserved for Factory Use
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9.10 Register 20. Reserved - Structure and Bit Definition
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RW RW RW RW RW RW RW RW
0 0 0 0 0 0 0 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RW RW RW RW RW RW RW RW
1 0 1 0 0 0 0 0
Reserved: Reserved for Factory Use
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Chapter 10 Software Driver and Hardware Sequence
Flow
10.1 Software Driver and Hardware Sequence Flow for Power
Management
This section describes the sequence of events and the interaction between the Host Driver and the
Ethernet controller to perform power management. The Ethernet controller has the ability to reduce its
power consumption when the Device is not required to receive or transmit Ethernet Packets.
Power Management is obtained by disabling the EPH clocks, including the Clocks derived from the Internal
PHY block to reduce internal switching, this reducing current consumption.
The Host interface however, will still be accessible. As discussed in Table 7 - Typical Flow Of Events For
Placing Device In Low Power Mode and Table 8 - Flow Of Events For Restoring Device In Normal Power
Mode, the tables describe the interaction between the EPH and Host driver allowing the Device to
transition from low power state to normal functionality and vice versa.
Table 7 - Typical Flow Of Events For Placing Device In Low Power Mode
S/W DRIVER CONTROLLER FUNCTION
1 Disable Transmitter – Clear the TXENA bit of
the Transmit Control Register
2 Remove and release all TX completion packet
numbers on the TX completion FIFO.
3 Disable Receiver – Clear the RXEN bit of the
Receive Control Register.
4 Process all Received packets and Issue a
Remove and Release command for each
respective RX packet buffer.
5 Disable Interrupt sources – Clear the Interrupt
Status Register
Save Device Context – Save all Specific
Register Values set by the driver.
6 Set PDN bit in PHY MI Register 0 to 1
7 The internal PHY entered in powerdown mode,
8 Write to the “EPH Power EN” Bit located in the
configuration register, Bank 1 Offset 0.
9 Ethernet MAC gates the RX Clock, TX clock
Ethernet MAC finishes packet currently being
transmitted.
The receiver completes receiving the current
frame, if any, and then goes idle. Ethernet MAC
will no longer receive any packets.
RX and TX completion FIFO’s are now Empty
and all MMU packet numbers are now free.
the TP outputs are in high impedance state.
derived from the Internal PHY. The EPH Clock is
also disabled.
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S/W DRIVER CONTROLLER FUNCTION
10 The Ethernet MAC is now in low power mode.
The Host may access all Runtime IO mapped
registers. All IO registers are still accessible.
However, the Host should not read or write to
the registers with the exception of:
a) Configuration Register
b) Control Register
c) Bank Register
Table 8 - Flow Of Events For Restoring Device In Normal Power Mode
S/W DRIVER CONTROLLER FUNCTION
1 Write and set (1) the “EPH Power EN” Bit, located
in the configuration register, Bank 1 Offset 0.
2 Ethernet MAC Enables the RX Clock, TX clock
3 Write the PDN bit in PHY MI Register 0 to 0
4 Internal PHY entered normal operation mode
derived from the Internal PHY. The EPH Clock is
also enabled.
5 Issue MMU Reset Command
6 Restore Device Register Level Context.
7 Enable Transmitter – Set the TXENA bit of the
Transmit Control Register
8 Enable Receiver – Set (1) the RXEN bit of the
Receive Control Register.
9 Ethernet MAC is now restored for normal
Ethernet MAC can now transmit Ethernet
Packets.
Ethernet MAC is now able to receive Packets.
operation.
10.2 Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
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S/W DRIVER MAC SIDE
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
5 The enqueued packet will be transferred to the
6
7
a) SERVICE INTERRUPT - Read Interrupt
Status Register. If it is a transmit interrupt,
read the TX FIFO Packet Number from the
FIFO Ports Register. Write the packet
number into the Packet Number Register.
The corresponding status word is now
readable from memory. If status word
shows successful transmission, issue
RELEASE packet number command to free
up the memory used by this packet.
Remove packet number from completion
FIFO by writing TX INT Acknowledge
Register.
b) Option 1) Release the packet.
Option 2) Check the transmit status in the
EPH STATUS Register, write the packet
number of the current packet to the Packet
Number Register, re-enable TXENA, then
go to step 4 to start the TX sequence again.
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
a) Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO
into the TX completion FIFO. Interrupt is
generated by the TX completion FIFO being
not empty.
b) If a TX failure occurs on any packets, TX
INT is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at
the TX FIFO PORTS Register.
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10.3 Typical Flow of Events for Transmit (Auto Release = 1)
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
5 The enqueued packet will be transferred to the
6 Transmit pages are released by transmit
7
8
a) SERVICE INTERRUPT – Read Interrupt
Status Register, exit the interrupt service
routine.
b) Option 1) Release the packet.
Option 2) Check the transmit status in the
EPH STATUS Register, write the packet
number of the current packet to the Packet
Number Register, re-enable TXENA, then
go to step 4 to start the TX sequence again.
S/W DRIVER MAC SIDE
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
completion.
a) The MAC generates a TXEMPTY interrupt
upon a completion of a sequence of
enqueued packets.
b) If a TX failure occurs on any packets, TX
INT is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at
the TX FIFO PORTS Register.
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10.4 Typical Flow of Event For Receive
1 ENABLE RECEPTION - By setting the RXEN
bit.
2 A packet is received with matching address.
3 The internal DMA logic generates sequential
4 When the end of packet is detected, the status
5 SERVICE INTERRUPT - Read the Interrupt
Status Register and determine if RCV INT is set.
The next receive packet is at receive area. (Its
packet number can be read from the FIFO Ports
Register). The software driver can process the
packet by accessing the RX area, and can move
it out to system memory if desired. When
processing is complete the CPU issues the
REMOVE AND RELEASE FROM TOP OF RX
command to have the MMU free up the used
memory and packet number.
S/W DRIVER MAC SIDE
Memory is requested from MMU. A packet
number is assigned to it. Additional memory is
requested if more pages are needed.
addresses and writes the receive words into
memory. The MMU does the sequential to
physical address translation. If overrun, packet
is dropped and memory is released.
word is placed at the beginning of the receive
packet in memory. Byte count is placed at the
second word. If the CRC checks correctly the
packet number is written into the RX FIFO. The
RX FIFO, being not empty, causes RCV INT
(interrupt) to be set. If CRC is incorrect the
packet memory is released and no interrupt will
occur.
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Call TX INTR or TXEMPTY
Yes No
Call ALLOCATE
INTR
Get Next TX
Packet
Available for
Transmission?
ISR
Save Bank Select & Address
Ptr Registers
Mask SMC91C111
Interrupts
Read Interrupt Register
Yes
EPH INTR?
TX INTR?
ALLOC INTR?
No Yes
NoYes
No Yes
RX INTR?
No
Call RXINTR
Write Allocated Pkt # into
Packet Number Reg.
Write Ad Ptr Reg. & Copy Data
& Source Address
Enqueue Packet
Set "Ready for Packet" Flag
Call EPH INTR
Call MDINT
Return Buffers to Upper Layer
Yes
MDINT?
Restore Address Pointer &
Bank Select Registers
Unmask SMC91C111
Interrupts
Exit ISR
Disable Allocation Interrupt
Mask
FIGURE 16 - INTERRUPT SERVICE ROUTINE
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RX INTR
Write Ad. Ptr. Reg. & Read
Word 0 from RAM
Yes
Read Words 2, 3, 4 from RAM
No Yes
Get Copy Specs from Upper
No Yes
Destination
Multicast?
for Address Filtering
Address
Filtering Pass?
Status Word
OK?
Do Receive Lookahead
Layer
Okay to
Copy?
No
YesNo
Copy Data Per Upper Layer
Issue "Remove and Release"
Specs
Command
Return to ISR
FIGURE 17 - RX INTR
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TX Interrupt With AUTO_RELEASE = FALSE
1. Save the Packet Number Register
Saved_PNR = Read Byte (Bank 2, Offset 2)
2. Read the EPH Status Register
Temp = Read (Bank 0, Offset 2)
3. Acknowledge TX Interrupt
Write Byte (0x02, (Bank 2, Offset C));
4. Check for Status of Transmission
If ( Temp AND 0x0001)
{
//If Successful Transmission
Step 4.1.1: Issue MMU Release (Release Specific Packet)
Write (0x00A0, (Bank2, Offset 0));
Step 4.1.2: Return from the routine
}
else
{
//Transmission has FAILED
// Now we can either release or re-enqueue the packet
Step 4.2.1: Get the packet to release/re-enqueue, stored in FIFO
Temp = Read (Bank 2, Offset 4)
Temp = Temp & 0x003F
Step 4.2.2: Write to the PNR
Write (Temp, (Bank2, Offset 2))
Step 4.2.3
// Option 1: Release the packet
Write (0x00A0, (Bank2, Offset 0));
//Option 2: Re-Enqueue the packet
Write (0x00C0, (Bank2, Offset 0));
Step 4.2.4: Re-Enable Transmission
Temp = Read(Bank0, Offset 0);
Temp = Temp2
Write (Temp2, (Bank 0, Offset 0));
Step 4.2.5: Return from the routine
}
5. Restore the Packet Number Register
Write
(Saved_PNR, (Bank 2, Offset 2))
Byte
FIGURE 18 - TX INTR
OR
10/100 Non-PCI Ethernet Single Chip MAC + PHY
0x0001
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
TXEMPTY INTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 0
&
TXINT = 0
(Waiting for Completion)
TXEMPTY = X
&
TXINT = 1
(Transmission Failed)
Read Pkt. # Register & Save
Write Add res s Pointer
Register
Read Status Word from RAM
Update Statistics
Issue "Release" Command
Acknowledge TXINTR
Re-Enable TXENA
TXEMPTY = 1
&
TXINT = 0
(Everything went through
successfully)
Update Variables
Restore Packet Number
Retur n to ISR
FIGURE 19 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED)
SMSC DS – LAN91C111 Rev. B Page 87 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
DRIVER SEND
Choose Bank Select
Register 2
Call ALLOCATE
Exit Driver Send
Read Interrupt Status Register
Ye s N o
Read Allocation Resu lt
Register
W rite Allo ca te d Packet into
Packet # Register
Write Address Pointer Register
Copy Part of TX Data Packet
Write Source Address into
into R AM
Proper Location
Copy Remaining TX Data
Packet into R AM
ALLOCATE
Issue "Allocate Memory"
Command to MMU
Allocatio n
Passed?
Store Data Buffer Pointer
Clear "Ready for Packet" Flag
En able A llocation Inte rrupt
Enqueue Packet
Set "Ready for Packet" Flag
Return Buffers to Up per Layer
Return
FIGURE 20 - DRIVE SEND AND ALLOCATE ROUTINES
MEMORY PARTITIONING
Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit
and receive resources. The MMU allocates and de-allocates memory upon different events. An additional
mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation.
Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the MAC
for receive. The CPU can control the number of bytes it requests for transmit but it cannot determine the
number of bytes the receive process is going to demand. Furthermore, the receive process requests will
be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might
not be for the node, and that are not subject to upper layer software flow control.
Rev. 09/17/2002 Page 88 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
INTERRUPT GENERATION
The interrupt strategy for the transmit and receive processes is such that it does not represent the
bottleneck in the transmit and receive queue management between the software driver and the controller.
For that purpose there is no register reading necessary before the next element in the queue (namely
transmit or receive packet) can be handled by the controller. The transmit and receive results are placed
in memory.
The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and receive
interrupts are enabled. This allows the interrupt service routine to process many receive packets without
exiting, or one at a time if the ISR just returns after processing and removing one.
There are two types of transmit interrupt strategies:
1) One interrupt per packet.
2) One interrupt per sequence of packets.
The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used.
TX INT bit - Set whenever the TX completion FIFO is not empty.
TX EMPTY INT bit - Set whenever the TX FIFO is empty.
AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their
memory is released automatically.
1) One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the
completion result in memory and process the interrupt one packet at a time. Depending on the
completion code the driver will take different actions. Note that the transmit process is working in
parallel and other transmissions might be taking place. The LAN91C111 is virtually queuing the
packet numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by
reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for
the driver to keep a list of packet numbers being transmitted. The numbers are queued by the
LAN91C111 and provided back to the CPU as their transmission completes.
2) One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1.
TX EMPTY INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has
stopped and therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that
when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed
successfully.
Note
: The pointer register is shared by any process accessing the LAN91C111 memory. In order to allow
processes to be interruptable, the interrupting process is responsible for reading the pointer value before
modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1) Transmit loading (sometimes interrupt driven)
2) Receive unloading (interrupt driven)
3) Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is
also required from interrupt service routines.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
TWO
OPTIONS
INTERRUPT
STATUS REGISTER
RCV
INT
TX EMPTY
INT
TX
INT
ALLOC
INT
T
X
I
F
O
F
'EMPTY'
X
T
C
O
M
P
E
L
T
F
F
I
O
'NOT EMPTY'
TX DONE
PACKET NUMBER
M.S. BIT ONLY
O
I
N
PACKET NUMBER
REGISTER
CPU ADDRESS
PAC K # O UT
'NOT EMPTY'
RX FIFO
PACKET NUMBER
R
X
F
F
I
O
RX PACKET
NUMBER
CSMA ADDRESS
C
S
M
A
/
C
D
P
A
L
A
D
P
C
E
O
K
G
C
I
D
R
H
Y
S
T
A
E
I
#
L
S
S
M
M
U
C
A
L
A
D
D
R
E
S
S
R
A
M
FIGURE 21 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
Rev. 09/17/2002 Page 90 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 11 Board Setup Information
The following parameters are obtained from the EEPROM as board setup information:
ETHERNET INDIVIDUAL ADDRESS
I/O BASE ADDRESS
MII INTERFACE
All the above mentioned values are read from the EEPROM upon hardware reset. Except for the
INDIVIDUAL ADDRESS, the value of the IOS switches determines the offset within the EEPROM for these
parameters, in such a way that many identical boards can be plugged into the same system by just
changing the IOS jumpers.
In order to support a software utility based installation, even if the EEPROM was never programmed, the
EEPROM can be written using the LAN91C111. One of the IOS combination is associated with a fixed
default value for the key parameters (I/O BASE) that can always be used regardless of the EEPROM
based value being programmed. This value will be used if all IOS pins are left open or pulled high.
The EEPROM is arranged as a 64 x 16 array. The specific target device is the 9346 1024-bit Serial
EEPROM. All EEPROM accesses are done in words. All EEPROM addresses in the spec are specified as
word addresses.
REGISTER
Configuration Register
Base Register
INDIVIDUAL ADDRESS 20-22 hex
If IOS2-IOS0 = 7, only the INDIVIDUAL ADDRESS is read from the EEPROM. Currently assigned values
are assumed for the other registers. These values are default if the EEPROM read operation follows
hardware reset.
The EEPROM SELECT bit is used to determine the type of EEPROM operation: a) normal or b) general
purpose register.
1) NORMAL EEPROM OPERATION - EEPROM SELECT bit = 0
On EEPROM read operations (after reset or after setting RELOAD high) the CONFIGURATION
REGISTER and BASE REGISTER are updated with the EEPROM values at locations defined by the
IOS2-0 pins. The INDIVIDUAL ADDRESS registers are updated with the values stored in the
INDIVIDUAL ADDRESS area of the EEPROM.
On EEPROM write operations (after setting the STORE bit) the values of the CONFIGURATION
REGISTER and BASE REGISTER are written in the EEPROM locations defined by the IOS2-IOS0
pins.
The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and
STORE) are used to control the EEPROM. Their values are not stored nor loaded from the EEPROM.
2) GENERAL PURPOSE REGISTER - EEPROM SELECT bit = 1
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the
POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER.
EEPROM WORD
ADDRESS
IOS Value * 4
(IOS Value * 4) + 1
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE
REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least
significant bits.
RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the
value until read low is used to determine completion. When an EEPROM access is in progress the
STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111
can be read or written until the EEPROM operation completes and both bits are clear. This
mechanism is also valid for reset initiated reloads.
Note
: If no EEPROM is connected to the LAN91C111, for example for some embedded applications, the ENEEP
pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and
Individual Address assume their default values upon hardware reset and the CPU is responsible for
programming them for their final value.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
IOS2-0 WORD ADDRESS
000 0h
001
010
011
100
101
110
XXX
1h
4h
5h
8h
9h
Ch
Dh
10h
11h
14h
15h
18h
19h
20h
21h
22h
16 BITS
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
IA0-1
IA2-3
IA4-5
FIGURE 22 - 64 X
16 SERIAL EEPROM MAP
SMSC DS – LAN91C111 Rev. B Page 93 Rev. 09/17/2002
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Chapter 12 Application Considerations
The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines,
system level implications and sample configurations for the most relevant bus types. All applications are
based on buffered architectures with a private SRAM bus.
FAST ETHERNET SLAVE ADAPTER
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
1) LAN91C111 chip
2) Serial EEPROM (93C46)
3) Some bus specific glue logic
Target systems:
1) VL Local Bus 32 bit systems
2) High-end ISA or non-burst EISA machines
3) EISA 32 bit slave
VL Local Bus 32 Bit Systems
On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as a 32 bit peripheral in
terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word
instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions.
Table 9 - VL Local Bus Signal Connections
VL BUS
SIGNAL
A2-A15 A2-A15 Address bus used for I/O space and register decoding, latched
M/nIO AEN Qualifies valid I/O decoding - enabled access when low. This
W/nR W/nR Direction of access. Sampled by the LAN91C111 on first rising
nRDYRTN nRDYRTN Ready return. Direct connection to VL bus.
nLRDY nSRDY and
LCLK LCLK Local Bus Clock. Rising edges used for synchronous bus
nRESET RESET Connected via inverter to the LAN91C111.
nBE0 nBE1
nBE2 nBE3
nADS nADS, nCYCLE Address Strobe is connected directly to the VL bus. nCYCLE is
IRQn INTR0 Typically uses the interrupt lines on the ISA edge connector of VL
LAN91C111
SIGNAL
some logic
nBE0 nBE1
nBE2 nBE3
NOTES
by nADS rising edge, and transparent on nADS low time.
signal is latched by nADS rising edge and transparent on nADS
low time.
clock that has nCYCLE active. High on writes, low on reads.
nSRDY has the appropriate functionality and timing to create the
VL nLRDY except that nLRDY behaves like an open drain output
most of the time.
interface transactions.
Byte enables. Latched transparently by nADS rising edge.
created typically by using nADS delayed by one LCLK.
bus
Rev. 09/17/2002 Page 94 SMSC DS – LAN91C111 Rev. B
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
VL BUS
SIGNAL
D0-D31 D0-D31 32 bit data bus. The bus byte(s) used to access the device are a
nLDEV nLDEV nLDEV is a totem pole output. nLDEV is active on valid decodes
VCC nRD nWR
GND A1 nVLBUS
OPEN nDATACS
LAN91C111
SIGNAL
NOTES
function of nBE0-nBE3:
nBE0 nBE1 nBE2 nBE3
0 0 0 0 Double word access
0 0 1 1 Low word access
1 1 0 0 High word access
0 1 1 1 Byte 0 access
1 0 1 1 Byte 1 access
1 1 0 1 Byte 2 access
1 1 1 0 Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that nBE2
and nBE3 override the value of A1, which is tied low in this
application.
of A15-A4 and AEN=0.
UNUSED PINS
SMSC DS – LAN91C111 Rev. B Page 95 Rev. 09/17/2002
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VLBUS
10/100 Non-PCI Ethernet Single Chip MAC + PHY
W/nR
A2-A15
LCLK
M/nIO
nRESET
IRQn
D0-D31
nRDYRTN
nBE0-nBE3
nADS
Delay 1 LCLK
W/nR
A2-A15
LCLK
AEN
RESET
INTR0
D0-D31
nRDYRTN
nBE0-nBE3
nADS
nCYCLE
LAN91C111
nSRDY nLDEV
nLRDY
O.C.
simulated
O.C.
nLDEV
FIGURE 23 - LAN91C111 ON VL BUS
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
HIGH-END ISA OR NON-BURST EISA MACHINES
On ISA machines, the LAN91C111 is accessed as a 16 bit peripheral. The signal connections are listed in
the following table:
Table 10 - High-End ISA or Non-Burst EISA Machines Signal Connectors
ISA BUS
SIGNAL
A1-A15 A1-A15 Address bus used for I/O space and register decoding.
AEN AEN Qualifies valid I/O decoding - enabled access when low.
nIORD nRD I/O Read strobe - asynchronous read accesses. Address is valid
nIOWR nWR I/O Write strobe - asynchronous write access. Address is valid
IOCHRDY ARDY This signal is negated on leading nRD, nWR if necessary. It is
RESET RESET
A0 nBE0
nSBHE nBE1
IRQn INTR0
D0-D15 D0-D15 16 bit data bus. The bus byte(s) used to access the device are a
nIOCS16 nLDEV buffered nLDEV is a totem pole output. Must be buffered using an open
GND nADS
VCC nBE2, nBE3,
LAN91C111
SIGNAL
nCYCLE, W/nR,
nRDYRTN,
LCLK
NOTES
before leading edge.
before leading edge. Data is latched on trailing edge.
then asserted on CLK rising edge after the access condition is
satisfied.
function of nBE0 and nBE1:
nBE0 nBE1 D0-D7 D8-D15
0 0 Lower Upper
0 1 Lower Not used
1 0 Not used Upper
Not used = tri-state on reads, ignored on writes
collector driver. nLDEV is active on valid decodes of A15-A4 and
AEN=0.
UNUSED PINS
No upper word access.
SMSC DS – LAN91C111 Rev. B Page 97 Rev. 09/17/2002
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Page 98
ISA
BUS
A1-A15, AEN
RESET
VCC
D0-D15
IRQ
nIORD
nIOWR
A0
nSBHE
nIOCS16
EISA 32 BIT SLAVE
A1-A15, AEN
RESET
nBE2, nBE3
D0-D15
INTR0
nRD
nWR
nBE0
nBE1
O.C.
FIGURE 24 - LAN91C111 ON ISA BUS
LAN91C111
nLDEV
10/100 Non-PCI Ethernet Single Chip MAC + PHY
On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path
option. As an I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs,
the timing information is externally derived from nCMD edges. Given that the access will be at least 1.5 to
2 clocks (more than 180ns at least) there is no need to negate EXRDY, simplifying the EISA interface
implementation. As a DMA Slave, the LAN91C111 accepts burst transfers and is able to sustain the peak
rate of one doubleword every BCLK. Doubleword alignment is assumed for DMA transfers. The
LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycle solicits wait states.
Table 11 - EISA 32 Bit Slave Signal Connections
EISA BUS
SIGNAL
LA2-LA15 A2-A15 Address bus used for I/O space and register decoding,
M/nIO
AEN
Latched W-R
combined with
nCMD
Rev. 09/17/2002 Page 98 SMSC DS – LAN91C111 Rev. B
LAN91C111
SIGNAL
latched by nADS (nSTART) trailing edge.
AEN Qualifies valid I/O decoding - enabled access when low.
These signals are externally ORed. Internally the AEN pin is
latched by nADS rising edge and transparent while nADS is
low.
nRD I/O Read strobe - asynchronous read accesses. Address is
valid before its leading edge. Must not be active during DMA
bursts if DMA is supported.
NOTES
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Page 99
10/100 Non-PCI Ethernet Single Chip MAC + PHY
EISA BUS
SIGNAL
Latched W-R
combined with
nCMD
nSTART nADS Address strobe is connected to EISA nSTART.
RESDRV RESET
nBE0 nBE1
nBE2 nBE3
IRQn INTR0 Interrupts used as active high edge triggered
D0-D31 D0-D31 32 bit data bus. The bus byte(s) used to access the device
nEX32
nNOWS
(optional
additional logic)
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
BCLK LCLK EISA Bus Clock. Data transfer clock for DMA bursts.
nDAK<n> nDATACS DMA Acknowledge. Active during Slave DMA cycles. Used
nIORC W/nR Indicates the direction and timing of the DMA cycles. High
nIOWC
nEXRDY nRDYRTN EISA bus signal indicating whether a slave DMA cycle will
VCC nVLBUS
GND A1
LAN91C111
SIGNAL
nWR I/O Write strobe - asynchronous write access. Address is
valid before leading edge . Data latched on trailing edge.
Must not be active during DMA bursts if DMA is supported.
nBE0 n BE1
nBE2 nBE3
nLDEV nLDEV is a totem pole output. nLDEV is active on valid
nCYCLE Indicates slave DMA writes.
Byte enables. Latched on nADS rising edge.
are a function of nBE0-nBE3:
nBE0 nBE1 nBE2 nBE3
0 0 0 0 Double word access
0 0 1 1 Low word access
1 1 0 0 High word access
0 1 1 1 Byte 0 access
1 0 1 1 Byte 1 access
1 1 0 1 Byte 2 access
1 1 1 0 Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that
nBE2 and nBE3 override the value of A1, which is tied low in
this application. Other combinations of nBE are not supported
by the LAN91C111. Software drivers are not anticipated to
generate them.
decodes of LAN91C111 pins A15-A4, and AEN=0. nNOWS is
similar to nLDEV except that it should go inactive on nSTART
rising. nNOWS can be used to request compressed cycles
(1.5 BCLK long, nRD/nWR will be 1/2 BCLK wide).
by the LAN91C111 as nDATACS direct access to data path.
during LAN91C111 writes, low during LAN91C111 reads.
take place on the next BCLK rising edge, or should be
postponed. nRDYRTN is used as an input in the slave DMA
mode to bring in EXRDY.
UNUSED PINS
NOTES
SMSC DS – LAN91C111 Rev. B Page 99 Rev. 09/17/2002
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EISA BUS
LA2- LA15
10/100 Non-PCI Ethernet Single Chip MAC + PHY
A2-A15
RESET
AEN
M/nIO
D0-D31
IRQn
nBE[0:3]
nCMD
nWR
BCLK
nSTART
LATCH
+
gates
RESET
AEN
D0-D31
INTR0
LAN91C111
nBE[0:3]
nRD
nWR
LCLK
nADS
nLDEV
nEX32
O.C.
FIGURE 25 - LAN91C111 ON EISA BUS
Rev. 09/17/2002 Page 100 SMSC DS – LAN91C111 Rev. B
PRELIMINARY
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