Datasheet KS88C01632, KS88C01624, KS88C01532, KS88C01524, S3C80G9 Datasheet (Samsung)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.

S3C80F7/C80F9/C80G7/C80G9 Microcontroller

The S3C80F7/C80F9/C80G7/C80G9 single-chip CMOS microcontroller is fabricated using a highly advanced
CMOS process and is based on Samsung's newest CPU architecture.

The S3C80F9/C80G9 is the microcontroller which has 32-Kbyte mask-programmable ROM and S3C80F7/C80G7
is the microcontroller which has 24-Kbyte mask-programmable ROM.
The S3P80F9/P80G9 is the microcontroller which has 32-Kbyte one-time-programmable EPROM and
S3P80F7/P80G7 is the microcontroller which has 24-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers developed S3C80F7/C80F9/C80G7/C80G9 by
integrating the following peripheral modules with the powerful SAM87 RC core:

— Internal LVD circuit and 16 bit-programmable pins for external interrupts.
— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
— One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.
— One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3C80F7/C80F9/C80G7/C80G9 is a versatile general-purpose microcontroller which is especially suitable
for use as remote transmitter controller. It is currently available in a 32-pin SOP, 42-pin SDIP and 44-pin QFP
package.

1-1

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

FEATURES

CPU

• SAM87RC CPU core

Memory

• 32-Kbyte internal ROM (S3C80F9/C80G9)

: 0000H–7FFFH

• 24-Kbyte internal ROM (S3C80F7/C80G7)

: 0000H–5FFFH

• Data memory: 272-byte RAM (318 register)

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power-

down modes

Instruction Execution Time

• 500 ns at 8-MHz f

(minimum)

OSC

Interrupts

• 22 interrupt sources with 16 vector and 7 level.

I/O Ports

• Three 8-bit I/O ports (P0–P2), one 8-bit output

port(P4) and 6-bit port (P3) for a total of 38 bit­programmable pins.(44-QFP)

• Three 8-bit I/O ports (P0–P2), one 8-bit output

port(P4) and 4-bit port (P3) for a total of 36 bit­programmable pins.(42-SDIP)

• Three 8-bit I/O ports (P0–P2) and one 2-bit I/O

port (P3) for a total of 26-bit programmable pins.
(32-SOP)

Carrier Frequency Generator

• One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Back-up mode

• When V

is lower than V

DD

, the chip enters

LVD

Back-up mode to block oscillation and reduce
the current consumption.

In S3C80G7/C80G9, this function is disabled

when operating state is “STOP mode”.

• When RESET pin is lower than Input Low

Voltage (VIL), the chip enters Back-up mode to
block oscillation and reduce the current

consumption.

Low Voltage Detect Circuit

• Low voltage detect to get into Back-up mode.

• Low level detect voltage

− S3C80F7/C80F9: 2.20 V (Typ) ± 200mV

− S3C80G7/C80G9: 1.90 V (Typ) ± 200mV

Operating Temperature Range

• –40

°

C to + 85 °C

Operating Voltage Range

• 1.7V to 5.0V at 4 MHz f

• 2.0V to 5.0V at 8 MHz f

(S3C80G7/C80G9)

OSC

(S3C80F7/C80F9)

OSC

Package Type

• 44-pin QFP-1010B

• 42-pin SDIP

Timers and Timer/Counters

• One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer
(software reset) function

• One 8-bit timer/counter (Timer 0) with three

operating modes; Interval mode, Capture and
PWM mode.

• One 16-bit timer/counter (Timer1) with two

operating modes; Interval mode and Capture.

1-2

• 32-pin SOP

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

BLOCK DIAGRAM

XIN

XOUT

VDD

MAIN

OSC

8-Bit
Basic
Timer

8-Bit

Timer/

Counter

16-Bit

Timer/

Counter

P0.0-0.3 (INT0-INT3)

P0.4-P0.7 (INT4)

LVD

I/O Port and Interrupt

32K-Bytes

ROM

Port 0

Control

SAM87RC

CPU

P1.0-P1.7

Port 1

317-Bytes

Register

File

TEST
RESET

Port 2

Port 3

Port 4

P2.0-2.3 (INT5-INT8)

P2.4-2.7 (INT9)

P3.0-T0PWM/
T0CAP/(T1CAP)
P3.1-REM/(T0CK)
P3.2/(T0CK)

P3.3/(T1CAP)
P3.4-3.5

P4.0-4.7

Figure 1-1. Block Diagram

Carrier

Registor

(Counter A)

1-3

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

PIN ASSIGNMENTS

P4.2
P4.1

P4.0
P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P2.4/INT9

P3.0/T0PWM/T0CAP/SDAT

R3.1/REM/SCLK

VDD

VSS

XOUT

XIN

TEST
P2.5/INT9
P2.6/INT9

RESET

P2.7/INT9

P1.0

P3.2/T0CK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

S3C80F7/C80F9

/C80G7/C80G9

(Top View)

42-SDIP

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P4.3
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
P4.4
P4.5
P4.6
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P4.7
P3.3/T1CAP

1-4

Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

P3.0/T0PWM/T0CAP/

P0.3/INT3

P0.2/INT2

P0.1/INT1

P0.0/INT0

P4.4

P4.5

P4.6

P1.7

P1.6

P1.5

P1.4

3332313029282726252423

P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4

P4.3
P4.2
P4.1

P4.0
P2.0/INT5
P2.1/INT6
P2.2/INT7

34
35

S3C80F7/C80F9

36
37
38
39
40
41
42
43
44

/C80G7/C80G9

(Top View)

(44-QFP)

1234567891011

22
21
20
19
18
17
16
15
14
13
12

P1.3
P1.2
P1.1
P4.7
P3.3/T1CAP
P3.2/T0CK
P1.0
P2.7/INT9
P3.5
P3.4

RESET

XIN

VSS

VDD

XOUT

SDAT

P2.3/INT8

P2.4/INT9

P3.1/REM/SCLK

TEST

P2.5/INT9

P2.6/INT9

Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

1-5

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

VSS

XIN

XOUT

TEST
P2.5/INT9
P2.6/INT9

RESET

P2.7/INT9

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

1
2
3
4
5

S3C80F7/C80F9

6
7

/C80G7/C80G9

8
9
10
11
12
13
14
15
16

(Top View)

32-SOP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VDD
P3.1/REM/T0CK/SCLK
P3.0/T0PWM/T0CAP/T1CAP/SDAT
P2.4/INT9
P2.3/INT8
P2.2/INT7
P2.1/INT6
P2.0/INT5
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0

Figure 1-4. Pin Assignment Diagram (32-Pin SOP Package)

1-6

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

Table 1-1. Pin Descriptions of 44-QFP and 42-SDIP

Pin

Names

P0.0–P0.7 I/O I/O port with bit-programmable pins.

Pin

Type

Pin Description Circuit

Type

1 34–41 30–37 Ext. INT

42 Pin

No.

Configurable to input or push-pull output
mode. Pull-up resistors can be assigned
by software. Pins can be assigned
individually as external interrupt inputs
with noise filters, interrupt enable/
disable, and interrupt pending control.
SED & R circuit built in P0 for STOP
releasing.

P1.0–P1.7 I/O I/O port with bit-programmable pins.

Configurable to input mode or output

2 20

24–301620–26
mode. Pin circuits are either push-pull or
n-channel open-drain type.

P2.0–P2.3
P2.4–P2.7

I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output
mode. Pull-up resistors can be assigned

1 4–8,

16, 17

19
by software. Pins can be assigned
individually as external interrupt inputs
with noise filters, interrupt enable/
disable, and interrupt pending control.
SED & R circuit built in P2 for STOP
releasing.

P3.0
P3.1

I/O 2-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull

3

9–10 3–4 T0PWM/ T0CAP

4
output mode, or n-channel open-drain
output mode. Input mode with pull-up
resistors can be assigned by software.
The two port 3 pins have high current
drive capability

P3.2–P3.3 I C-MOS Input port with pull-up resistors 5 21

22

P3.4–P3.5 O Open drain output port for high current

6 None 13–14 –
drive

P4.0–P4.7 O 8- bit-programmable output pins.

Configurable to open drain output port or
push-pull output port.

XIN, X

RESET

OUT

– System clock input and output pins – 13,14 7,8 –

I System reset signal input pin and back-

7 1–3

42,23
31-33

8 18 12 –
up mode input.

TEST I Test signal input pin (for factory use only;

– 15 9 –
must be connected to VSS.)

44 Pin

No.

42–44

1,2,

10,11,

15

17
18

41–38
27–29

19

Shared

Functions

(INT0 - 4)

–

Ext. INT

(INT5–9)

REM

(T0CK)

(T1CAP)

–

V

DD

V

SS

– Power supply input pin – 11 5 –
– Ground pin – 12 6 –

1-7

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 1-2. Pin Descriptions of 32-SOP

Pin

Names

Pin

Type

Pin Description Circuit

P0.0–P0.7 I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output
mode. Pull-up resistors are assignable by
software. Pins can be assigned individually as
external interrupt inputs with noise filters,
interrupt enable/ disable, and interrupt pending
control. SED & R circuit built in P0 for STOP
releasing.

P1.0–P1.7 I/O I/O port with bit-programmable pins.

Configurable to input mode or output mode.
Pin circuits are either push-pull or n-channel
open-drain type.

P2.0–P2.3
P2.4–P2.7

I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output
mode. Pull-up resistors can be assigned by
software. Pins can be assigned individually as
external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt pending
control. SED & R circuit built in P2 for STOP
releasing.

P3.0
P3.1

I/O 2-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull output
mode, or n-channel open-drain output mode.
Input mode with pull-up resistors can be
assigned by software. The two port 3 pins
have high current drive capability.

XIN, X

RESET

OUT

– System clock input and output pins – 2,3 –

I System reset signal input pin and back-up

mode input.

TEST I Test signal input pin (for factory use only;

must be connected to VSS).

Type

32 Pin

No.

Shared

Functions

1 17–24 Ext. INT

2 9–16 –

1 25–28

Ext. INT

29,5, 6,8

3
4

30,31 T0PWM/

T0CAP/T1CAP

REM/T0CK

8 7 –

– 4 –

V
V

1-8

DD
SS

– Power supply input pin – 32 –
– Ground pin – 1 –

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

PIN CIRCUITS

VDD

Pull-up
Resistor

Pull-up

Enable

VDD

Data

Input/
Output

Output

Disable

VSS

External

Interrupt

Stop

Noise

Filter

Stop release

Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)

1-9

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

PIN CIRCUITS (Continued)

VDD

Pull-up
Resistor

Pull-up

Enable

VDD

Data

Input/
Output

Open-Drain

Output Disable

VSS

Normal

Input

Noise

Filter

Figure 1-6. Pin Circuit Type 2 (Port 1)

1-10

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

VDD

Pull-up
Resistor

Pull-up
Enable

P3CON.2

VDD

Port 3.0 Data

T0_PWM

Open-Drain

Output Disable

P3.0 Input

T0CAP/(T1CAP)

M
U
X

P3CON.2,6,7

M

U
X

Data

VSS

Noise filter

Figure 1-7. Pin Circuit Type 3 (P3.0)

P3.0/T0PWM
T0CAP/(T1CAP)

1-11

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

PIN CIRCUITS (Continued)

VDD

Pull-up
Resistor

Pull-up

Enable

P3CON.5

VDD

Port 3.1 Data

CAOF(CACON.0)

Carrier On/Off (P3.7)

Open-Drain

Output

Disable

P3.1 Input

T0CK

M
U

X

P3CON.5,6,7

M
U

X

Data

VSS

Noise filter

Figure 1-8. Pin Circuit Type 4 (P3.1) Circuit

P3.1/REM/(T0CK)

VDD

Pull-up
Resistor

1-12

Input

T0CK : P3.2

T1CAP: P3.3

M

U
X

Figure 1-9. Pin Circuit Type 5 (P3.2, P3.3)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

Output

Data

VSS

Figure 1-10. Pin Circuit type 6 (P3.4, P3.5)

VDD

Data

Open-Drain

Output Disable

Output

VSS

Figure 1-11. Pin Circuit type 7 (Port 4)

VDD

Pull-up
Resistor

RESET

Figure 1-12. Pin Circuit type 8 (RESET)

1-13

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

14 ELECTRICAL DATA 1 (S3C80F7/C80F9)

OVERVIEW

In this section, S3C80F7/C80F9 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt
— Stop mode release timing when initiated by a Reset
— I/O capacitance
— A.C. electrical characteristics
— Input timing for external interrupts
— Input timing for RESET
— Oscillation characteristics
— Oscillation stabilization time

14-1

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 14-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage
Input voltage
Output voltage
Output current High

V

DD

V

IN

I

V

O

OH

All output pins
One I/O pin active – 18 mA

– – 0.3 to + 6.5 V
–

– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3

V
V

All I/O pins active – 60

Output current Low

I

OL

One I/O pin active + 30 mA
Total pin current for ports 0, 1, and 2 + 100

Total pin current for port 3 + 40

Operating

T

A

– – 40 to + 85

°C

temperature
Storage temperature

T

STG

– – 65 to + 150

°C

Table 14-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage

V

DD

F

OSC

= 8 MHz

2.0 – 5.0 V

(Instruction clock = 2 MHz)

Input High
voltage

Input Low voltage

Output High
voltage

V

V
V

V

V

V

V
V

OH1

OH2

IH1

IH2
IH3
IL1

IL2
IL3

All input pins except V
and V

IH3

RESET

XIN
All input pins except V

and V

IL3

RESET

IH2

IL2

0.8 V

DD

0.85 V

DD

V

– 0.3 V

DD

–

0 –

V

DD

V

DD
DD

0.2 V

0.2 V
XIN 0.3
V

= 2.4 V IOH = – 6 mA

DD

V

– 0.7

DD

Port 3.1 only, TA = 25°C
VDD = 2.4 V, IOH = – 2.2mA

V

0.7

–

DD

DD

DD

P3.0, P2.0–2.3
TA = 25°C

V

V

V

14-2

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Output High
voltage

Output Low
voltage

V

V

V

OH3

OL1

OL2

VDD = 2.4 V,IOH = – 1 mA
Port0, Port1, P2.4-2.7 and Port4

T

= 25°C

A

V

= 2.4 V, IOL = 12 mA, port

DD

3.1 only, T

= 25°C

A

VDD = 2.4 V, IOL = 5 mA

V

DD

–

1.0

– – V

– 0.4 0.5 V

0.4 0.5
P3.0, P3.4-3.5, P2.0-2.3
T

= 25°C

A

V

OL3

IOL = 2mA

0.4 1
Port 0, Port1, P2.4-2.7 and Port4
T

= 25°C

A

Input High
leakage current

Input Low
leakage current

I

LIH1

I

LIH2

I

LIL1

VIN = V
All input pins except X
X

VIN = VDD, X
V

OUT

= 0 V

IN

DD

IN

and X

IN

OUT

and

All input pins except XIN, X

OUT

– – 1 µA

20

– – – 1 µA

,

and RESET

Output High
leakage current

Output Low
leakage current

Pull-up resistors

I

LIL2

I

LOH

I

LOL

R

L1

V

= 0 V

IN

X

and X

V

IN

OUT

= V

OUT

DD

All output pins
V

= 0 V

OUT

All output pins
V

= 0 V, V

IN

T

= 25°C, Ports 0–2, P3.2–3.3

A

DD

= 2.4 V

– 20

– – 1 µA

– – – 1 µA

44 55 95

kΩ

14-3

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 14-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Supply current

(note)

I

DD1

Operating mode
V

= 5.0 V

DD

– 6 11 mA

8 MHz crystal
4 MHz crystal 4.5 9

I

DD2

Idle mode

1.8 3.5

VDD = 5.0 V
8 MHz crystal

4 MHz crystal 1.6 3.0

I

DD3

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

Stop mode; V
V

= 3.6 V

DD

V

= 2.4 V

DD

V

= 0.7 V

DD

DD

= 5.0 V

– 18 25 uA

12 15

4.5 8
1 1.5

Table 14-3. Characteristics of Low Voltage Detect circuit

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Hysteresys Voltage of

∆V

– – 100 300 mV

LVD (Slew Rate of LVD)
Low level detect voltage

V

LVD

– 2.00 2.20 2.40 V

Table 14-4. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply
voltage

Data retention supply
current

14-4

V

DDDR

I

DDDR

V

= 1.0 V

DDDR

Stop mode

– 1.0 – 5.0 V

– – 1 µA

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

Idle Mode

~

~

Stop Mode

(Basic Timer Active)

VDD

EXT INT

VDD

RESET

~

~

Execution of

STOP Instrction

Data Retention Mode

VDDDR

0.2VDD

Normal
Operating
Mode

0.8VDD

tWAIT

Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt

~

~

~

~

Execution of

STOP Instrction

Reset

Occur

Stop Mode

Oscillation Stabilization Time

Normal
Operating
Mode

NOTE:tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 14-2. Stop Mode Release Timing When Initiated by a RESET

tWAIT

14-5

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Stop Mode

~

VDD

VLVD

Execution of

STOP Instrction

NOTE:tWAIT is the same as 4096 x 16 x 1/fOSC.

~

~

~

Figure 14-3. Stop Mode Release Timing When Initiated by a LVD

Reset

Occur

Back-up Mode

VDDDR

Data Retention Time

Oscillation Stabilization Time

Normal
Operating
Mode

tWAIT

Table 14-5. Input/Output Capacitance

(T

= – 40 °C to + 85 °C , V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

C

C

OUT

IN

f = 1 MHz; unmeasured pins

are connected to V

SS

– – 10 pF

Input
capacitance

Output
capacitance

I/O capacitance

C

IO

Table 14-6. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C)

A

Parameter Symbol Conditions Min Typ Max Unit

Interrupt input,
High, Low width

RESET input Low

width

t

INTH

t

INTL

t

RSL

P0.0–P0.7, P2.3–P2.0

,

V

= 5.0 V

DD

Input
V

= 5.0 V

DD

200 300 – ns

1000 – –

14-6

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

tINTHtINTL

0.8 VDD

DD

0.2 V

NOTE:The unit tCPU means one CPU clock period.

Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3–P2.0)

VDD

RESET

Normal Operating Mode

NOTE:tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 14-5. Input Timing for RESET

Back-up Mode

(Stop Mode)

Reset

Occur

Oscillation Stabilization Time

Normal
Operating
Mode

tWAIT

14-7

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

S3C80F9

Table 14-7. Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Conditions Min Typ Max Unit

Crystal

Ceramic

External clock

External

Clock

Open Pin

C1

C2

C1

C2

CPU clock oscillation

IN

OUT

frequency

X

X

CPU clock oscillation

IN

OUT

frequency

X

input frequency

IN

X

X

XIN

XOUT

Table 14-8. Oscillation Stabilization Time

1 – 8 MHz

1 – 8 MHz

1 – 8 MHz

(TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.0 V)

Oscillator Test Condition Min Typ Max Unit

f

Main crystal

Main ceramic

> 400 kHz

OSC

Oscillation stabilization occurs when VDD is

– – 20 ms

– – 10 ms

equal to the minimum oscillator voltage range.

External clock

XIN input High and Low width (tXH, tXL)

25 – 500 ns

(main system)
Oscillator

stabilization

t

when released by a reset

WAIT

(1)

–

216/f

OSC

– ms

wait time

t

when released by an interrupt

WAIT

NOTES:

1. f

2. The duration of the oscillation stabilization time (t

is the oscillator frequency.

OSC

in the basic timer control register, BTCON.

(2)

) when it is released by an interrupt is determined by the setting

WAIT

– – – ms

14-8

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

Instruction

Clock

2 MHz

1.25 MHz

1.0 MHz

500 kHz

250 kHz
100 kHz

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, or 16)
A: 2.0 V, 8 MHz

A

1 2 3 4 5

Supply Voltage (V)

6 7

Figure 14-6. Operating Voltage Range of S3C80F9

fOSC
(Main Oscillator
Frequency)

8 MHz
6 MHz
4 MHz

400 kHz

14-9

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

15 ELECTRICAL DATA 2 (S3C80G7/C80G9)

OVERVIEW

In this section, S3C80G7/C80G9 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt
— Stop mode release timing when initiated by a Reset
— I/O capacitance
— A.C. electrical characteristics
— Input timing for external interrupts
— Input timing for RESET
— Oscillation characteristics
— Oscillation stabilization time

15-1

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 15-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage
Input voltage
Output voltage
Output current High

V

DD

V

IN

I

V

O

OH

All output pins
One I/O pin active – 18 mA

– – 0.3 to + 6.5 V
–

– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3

V
V

All I/O pins active – 60

Output current Low

I

OL

One I/O pin active + 30 mA
Total pin current for ports 0, 1, and 2 + 100

Total pin current for port 3 + 40

Operating

T

A

– – 40 to + 85

°C

temperature
Storage temperature

T

STG

– – 65 to + 150

°C

Table 15-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Operating Voltage

V

DD

F

OSC

= 4 MHz

1.7 – 5.0 V

(Instruction clock = 1 MHz)

Input High
voltage

Input Low voltage

Output High
voltage

V

V
V

V

V

V

V
V

OH1

OH2

IH1

IH2
IH3
IL1

IL2
IL3

All input pins except V
and V

IH3

RESET

XIN
All input pins except V

and V

IL3

RESET

IH2

IL2

0.8 V

DD

0.85 V

DD

V

– 0.3 V

DD

–

0 –

V

DD

V

DD
DD

0.2 V

0.2 V
XIN 0.3
V

= 2.4 V IOH = – 6 mA

DD

V

– 0.7

DD

Port 3.1 only, TA = 25°C
VDD = 2.4 V, IOH = – 2.2mA

VDD– 0.7

DD

DD

P3.0, P2.0–2.3
TA = 25°C

V

V

V

15-2

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

Table 15-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Output High
voltage

Output Low
voltage

V

V

V

OH3

OL1

OL2

VDD = 2.4 V,IOH = – 1 mA
Port0, Port1, P2.4–2.7 and Port4

T

= 25°C

A

V

= 2.4 V, IOL = 12 mA, port

DD

3.1 only, T

= 25°C

A

VDD = 2.4 V, IOL = 5 mA

V

DD

–

1.0

– – V

– 0.4 0.5 V

0.4 0.5
P3.0, P3.4–3.5, P2.0–2.3
T

= 25°C

A

V

OL3

IOL = 2mA

0.4 1
Port 0, Port1, P2.4–2.7 and Port4

T

= 25°C

A

Input High
leakage current

Input Low
leakage current

I

LIH1

I

LIH2

I

LIL1

VIN = V
All input pins except X
X

VIN = VDD, X
V

OUT

= 0 V

IN

DD

IN

and X

IN

OUT

and

All input pins except XIN, X

OUT

– – 1 µA

20

– – – 1 µA

,

and RESET

Output High
leakage current

Output Low
leakage current

Pull-up resistors

I

LIL2

I

LOH

I

LOL

R

L1

V

= 0 V

IN

X

and X

V

IN

OUT

= V

OUT

DD

All output pins
V

= 0 V

OUT

All output pins
V

= 0 V, V

IN

T

= 25°C, Ports 0–2, P3.2–3.3

A

DD

= 2.4 V

– 20

– – 1 µA

– – – 1 µA

44 55 95

kΩ

15-3

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 15-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Supply current

(note)

I

DD1

Operating mode
V

= 5.0 V

DD

– 4.5 9 mA

4 MHz crystal

I

DD2

Idle mode

1.6 3.0

VDD = 5.0 V
4 MHz crystal

I

DD3

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

Stop mode;
V

= 5.0 V

DD

– 1 6 uA

Table 15-3. Characteristics of Low Voltage Detect circuit

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Hysteresys Voltage of
LVD (Slew Rate of LVD)

Low level detect voltage

Table 15-4. Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply
voltage

Data retention supply
current

∆V

V

V

DDDR

I

DDDR

LVD

V

DDDR

= 1.0 V

Stop mode

– – 100 300 mV

– 1.70 1.90 2.10 V

– 1.0 – 5.0 V

– – 1 µA

15-4

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

Idle Mode

~

~

Stop Mode

(Basic Timer Active)

VDD

EXT INT

VDD

RESET

~

~

Execution of

STOP Instrction

Data Retention Mode

VDDDR

0.2VDD

Normal
Operating
Mode

0.8VDD

tWAIT

Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt

~

~

~

~

Execution of

STOP Instrction

Reset

Occur

Stop Mode

Oscillation Stabilization Time

Normal
Operating
Mode

NOTE:tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 15-2. Stop Mode Release Timing When Initiated by a RESET

tWAIT

15-5

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

Table 15-5. Input/Output Capacitance

(T

= – 40 °C to + 85 °C , V

A

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

C

C

OUT

IN

f = 1 MHz; unmeasured pins

are connected to V

SS

– – 10 pF

Input
capacitance

Output
capacitance

I/O capacitance

C

IO

Table 15-6. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C)

A

Parameter Symbol Conditions Min Typ Max Unit

Interrupt input,
High, Low width

RESET input Low

width

t

INTH

t

INTL

t

RSL

P0.0–P0.7, P2.3–P2.0

,

V

= 5.0 V

DD

Input
V

= 5.0 V

DD

200 300 – ns

1000 – –

15-6

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

tINTHtINTL

0.8 VDD

DD

0.2 V

NOTE:The unit tCPU means one CPU clock period.

Figure 15-3. Input Timing for External Interrupts (Port 0, P2.3–P2.0)

VDD

RESET

Normal Operating Mode

NOTE:tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 15-4. Input Timing for RESET

Back-up Mode

(Stop Mode)

Reset

Occur

Oscillation Stabilization Time

Normal
Operating
Mode

tWAIT

15-7

ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

S3C80G9

Table 15-7. Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Conditions Min Typ Max Unit

Crystal

Ceramic

External clock

External

Clock

Open Pin

C1

X

X

C2

X

C1

X

C2

XIN

XOUT

CPU clock oscillation
frequency

IN

OUT

CPU clock oscillation
frequency

IN

OUT

X

Table 15-8. Oscillation Stabilization Time

(TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.0 V)

input frequency

IN

1 – 4 MHz

1 – 4 MHz

1 – 4 MHz

Oscillator Test Condition Min Typ Max Unit

f

Main crystal

Main ceramic

> 400 kHz

OSC

Oscillation stabilization occurs when VDD is

– – 20 ms

– – 10 ms

equal to the minimum oscillator voltage range.

External clock

XIN input High and Low width (tXH, tXL)

25 – 500 ns

(main system)
Oscillator

stabilization

t

when released by a reset

WAIT

(1)

–

216/f

OSC

– ms

wait time

t

when released by an interrupt

WAIT

NOTES:

1. f

2. The duration of the oscillation stabilization time (t

is the oscillator frequency.

OSC

in the basic timer control register, BTCON.

(2)

) when it is released by an interrupt is determined by the setting

WAIT

– – – ms

15-8

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA

Instruction

Clock

2 MHz

1.25 MHz

1.0 MHz

500 kHz
250 kHz

100 kHz

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, or 16)
A: 1.7 V, 4 MHz

A

1 2 3 4 5

Supply Voltage (V)

6 7

Figure 15-6. Operating Voltage Range of S3C80G9

fOSC
(Main Oscillator
Frequency)

8 MHz
6 MHz
4 MHz

400 kHz

15-9

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) MECHANICAL DATA

16 MECHANICAL DATA

OVERVIEW

The S3C80F7/C80F9/C80G7/C80G9 microcontroller is currently available in a 32-pin SOP, 42-pin SDIP and 44­pin QFP package.

0-8

#32

#17

12.00 ± 0.30

(0.43)

32-SOP-450A

#1

20.30 MAX

19.90 ± 0.20

0.40 ± 0.10

NOTE: Dimensions are in millimeters.

#16

1.27

8.34 ± 0.20

+ 0.10

0.25

2.00 ± 0.10

0.05 MIN

11.43

- 0.05

0.90 ± 0.20

2.20 MAX

0.10 MAX

Figure 16-1. 32-Pin SOP Package Dimension

16-1

MECHANICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632)

(1.77)

#42 #22

42-SDIP-600

14.00 ± 0.20

39.50 MAX

39.10 ± 0.20

0.50 ± 0.10

1.00 ± 0.10

1.78

0-15

15.24

+ 0.10

- 0.05

0.25

#21#1

3.50 ± 0.20

5.08 MAX

0.51 MIN

3.30 ± 0.30

16-2

NOTE: Dimensions are in millimeters.

Figure 16-2. 42-Pin SDIP Package Dimension

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) MECHANICAL DATA

13.20 ± 0.30
0-8

10.00 ± 0.20

0.15

+ 0.10

- 0.05

13.20 ± 0.30

44-QFP-1010B

10.00 ± 0.20

#44

#1

0.80

NOTE: Dimensions are in millimeters.

Figure 16-3. 44-Pin SQFP Package Dimension

0.15 MAX

0.35

+ 0.10

- 0.05

0.10 MAX

0.80 ± 0.20

0.05 MIN

(1.00)

2.05 ± 0.10

2.30 MAX

16-3