KS57C21832/P21832 PRODUCT OVERVIEW
1-1
1 PRODUCT OVERVIEW
OVERVIEW
The KS57C21832 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, 8-bit timer/counter 0, 16-bit timer/counter 1, and serial I/O, the
KS57C21832 offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the KS57C21832's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The KS57C21832 microcontroller is also available in OTP (One Time Programmable) version, KS57P21832.
KS57P21832 microcontroller has an on-chip 32 K-byte one-time-programable EPROM instead of masked ROM.
The KS57P21832 is comparable to KS57C21832, both in function and in pin configuration.
PRODUCT OVERVIEW KS57C21832/P21832
1-2
FEATURES SUMMARY
Memory
• 8,192 × 4-bit RAM (excluding LCD display RAM)
• 32,768 × 8-bit ROM
39 I/O Pins
• I/O: 35 pins
• Input only: 4 pins
LCD Controller/Driver
• 56 segments and 16 common terminals
• 8 and 16 common selectable
• Internal resistor circuit for LCD bias
• All dot can be switched on/off
8-bit Basic Timer
• 4 interval timer functions
• Watchdog timer
8-bit Timer/Counter 0
• Programmable 8-bit timer
• External event counter
• Arbitrary clock frequency output
• External clock signal divider
• Serial I/O interface clock generator
16-Bit Timer/Counter 1
• Programmable 16-bit timer
• External event counter
• Arbitrary clock frequency output
• External clock signal divider
8-bit Serial I/O Interface
• 8-bit transmit/receive mode
• 8-bit receive mode
• LSB-first or MSB-first transmission selectable
• Internal or external clock source
Memory-Mapped I/O Structure
• Data memory bank 15
Watch Timer
• Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
• 4 frequency outputs to BUZ pin
• Clock source generation for LCD
Interrupts
• Four internal vectored interrupts
• Four external vectored interrupts
• Two quasi-interrupts
Bit Sequential Carrier
• Supports 16-bit serial data transfer in arbitrary
format
Power-Down Modes
• Idle mode (only CPU clock stops)
• Stop mode (main system clock and CPU clock
stop)
• Sub-system clock stop mode
Oscillation Sources
• Crystal, ceramic, or RC for main system clock
• Crystal oscillator for subsystem clock
• Main system clock frequency: 0.4 - 6 MHz
• Subsystem clock frequency: 32.768 kHz
• CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
• 0.67, 1.33, 10.7 µs at 6 MHz
• 0.95, 1.91, 15.3 µs at 4.19 MHz
• 122 µs at 32.768 kHz
Operating Temperature
• - 40 °C to 85 °C
Operating Voltage Range
• 1.8 V to 5.5 V (3.0 MHz @ 1.8 V)
Package Type
• 100-pin QFP
KS57C21832/P21832 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
VLC1-VLC5
COM0-COM7
P4.0-P5.3/
COM8-COM15
SEG0-SEG39
P9.3-P6.0/
SEG40-SEG55
LCD
Driver/
Controller
Program
Status Word
Stack
Pointer
Arithmetic
and
Logic Unit
Instruction
Internal
Interrupts
RESET
P8.0-P8.3
SEG47-SEG44
I/O Port 8
I/O Port 9
P9.0-P9.3
SEG43-SEG40
8-Bit
Timer/
Counter 0
Interrupt
Control
Block
Instruction
Register
Clock
16-Bit
TImer/
Counter 1
32 K Byte
Program
Memory
8192 x 4-Bit
Data
Memory
Serial I/O
I/O
Port 0
P0.0/
SCK
/KO
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
P6.0-P6.3
SEG55-SEG52
KS4-KS7
P7.0-P7.3
SEG51-SEG48
I/O Port 7
I/O Port 6
P5.0-P5.3/
COM12-COM15
P4.0-P4.3/
COM8-COM11
I/O Port 5
I/O Port 4
I/O Port 3
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
I/O Port 2
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
Input Port 1
P1.0-P1.3/
INT0-INT4
XT
OUT
X
OUT
XT
IN
X
IN
Basic
Timer
Watch
Timer
Figure 1-1. KS57C21832 Simplified Block Diagram
PRODUCT OVERVIEW KS57C21832/P21832
1-4
PIN ASSIGNMENTS
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
P4.0/COM8
P4.1/COM9
P4.2/COM10
P4.3/COM11
P5.0/COM12
P5.1/COM13
P5.2/COM14
P5.3/COM15
P6.0/SEG55/K4
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
P0.0/
SCK
/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
V
DD
V
SS
X
OUT
X
IN
TEST
XT
IN
XT
OUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
KS57C21832
(100-QFP-1420C)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31323334353637383940414243444546474849
50
100
99989796959493929190898887868584838281
Figure 1-2. KS57C21832 100-QFP Pin Assignment Diagram
KS57C21832/P21832 PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. KS57C21832 Pin Descriptions
Pin Name Pin Type Description Number Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as opendrain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
11
12
13
14
SCK/K0
SO/K1
SI/K2
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.
23
24
25
26
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O Same as port 0 except that port 2 is 3-bit I/O port.
27
28
29
CLO
LCDCK
LCDSY
P3.0
P3.1
P3.2
P3.3
I/O Same as port 0. 30
31
32
33
TCLO0
TCLO1
TCL0
TCL1
P4.0-P4.3
P5.0-P5.3
I/O
4-bit I/O ports.
1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
42-45
46-49
COM8-
COM11
COM12-
COM15
P6.0-P6.3
P7.0-P7.3
I/O Same as P4, P5.
50-53
54-57
SEG55/K4-
SEG52/K7
SEG51-
SEG48
P8.0-P8.3
P9.0-P9.3
I/O Same as P4, P5. 58-61
62-65
SEG47-
SEG44
SEG43-
SEG40
SCK I/O Serial I/O interface clock signal. 11 P0.0/K0
SO I/O Serial data output. 12 P0.1/K1
SI I/O Serial data input. 13 P0.2/K2
BUZ I/O 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
14 P0.3/K3
INT0, INT1 I External interrupts. The triggering edge for INT0 and
INT1 is selectable.
23, 24 P1.0, P1.1
PRODUCT OVERVIEW KS57C21832/P21832
1-6
Table 1-1. KS57C21832 Pin Descriptions (Continued)
Pin Name Pin Type Description Number Share Pin
INT2 I
Quasi-interrupt with detection of rising or falling
edges.
25 P1.2
INT4 I
External interrupt with detection of rising or
falling edges.
26 P1.3
CLO I/O Clock output . 27 P2.0
LCDCK I/O LCD clock output for display expansion. 28 P2.1
LCDSY I/O LCD synchronization clock output for display
expansion.
29 P2.2
TCLO0 I/O Timer/counter 0 clock output. 30 P3.0
TCLO1 I/O Timer/counter 1 clock output. 31 P3.1
TCL0 I/O External clock input for timer/counter 0. 32 P3.2
TCL1 I/O External clock input for timer/counter 1. 33 P3.3
COM0-COM7 O LCD common signal output. 34-41 –
COM8-COM11 I/O 42-45 P4.0-P4.3
COM12-COM15 46-49 P5.0-P5.3
SEG0-SEG39 O LCD segment signal output.
5-1,
100-66
–
SEG40-SEG43 I/O 65-62 P9.3-P9.0
SEG44-SEG47 61-58 P8.3-P8.0
SEG48-SEG51 57-54 P7.3-P7.0
SEG52-SEG55 53-50 P6.3/K7-P6.0/K4
K0-K3 I/O External interrupt. The triggering edge is
selectable.
11-14 P0.0-P0.3
K4-K7 50-53 P6.0-P6.3
V
DD
– Main power supply. 15 –
V
SS
– Ground. 16 –
RESET I Reset signal. 22 –
V
LC1-VLC5
– LCD power supply. 10-6 –
X
in, Xout
– Crystal, Ceramic or RC oscillator pins for
system clock.
18, 17 –
XT
in, XTout
– Crystal oscillator pins for subsystem clock. 20, 21 –
TEST I
Test signal input. (must be connected to VSS)
19 –
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
KS57C21832/P21832 PRODUCT OVERVIEW
1-7
Table 1-2. Overview of KS57C21832 Pin Data
Pin Names Share Pins I/O Type Reset Value Circuit Type
P0.1, P0.3 SO/K1, BUZ/K3 I/O Input E-1
P0.0, P0.2 SCK/K0, SI/K2 I/O Input E-2
P1.0-P1.3 INT0-INT2, INT4 I Input A-3
P2.0-P2.2 CLO, LCDCK, LCDSY I/O Input E
P3.0-P3.1 TCLO0, TCLO1 I/O Input E
P3.2-P3.3 TCL0, TCL1 I/O Input E-1
P4.0-P4.3
P5.0-P5.3
COM8-COM11
COM12-COM15
I/O Input H-13
P6.0-P6.3 SEG55/K4-SEG52/K7
I/O
Input
H-16
P7.0-P7.3 SEG51-SEG48 I/O Input H-13
P8.0-P8.3
P9.0-P9.3
SEG47-SEG44
SEG43-SEG40
I/O
Input
H-13
COM0-COM7 – O High H-3
SEG0-SEG39 – O High H-15
V
DD
– – – –
V
SS
– – – –
RESET – I – B
V
LC1
-
V
LC5
– – – –
X
IN,
X
OUT
– – – –
XT
IN,
XT
OUT
– – – –
TEST – I – –
PRODUCT OVERVIEW KS57C21832/P21832
1-8
PIN CIRCUIT DIAGRAMS
P-Channel
N-Channel
In
V
DD
Figure 1-3. Pin Circuit Type A
Schmitt Trigger
Pull-Up
Resistor
V
DD
Pull-Up
Resistor
Enable
In
P-Channel
Figure 1-4. Pin Circuit Type A-3
Schmitt Trigger
In
V
DD
Pull-Up
Resistor
Figure 1-5. Pin Circuit Type B
P-Channel
N-Channel
V
DD
Out
Output
DIsable
Data
Figure 1-6. Pin Circuit Type C
KS57C21832/P21832 PRODUCT OVERVIEW
1-9
N-CH
V
DD
Pull-up
Resistor
Enable
V
DD
I/O
PNE
Pull-up
Resistor
P-CH
Output
DIsable
Data
Figure 1-7. Pin Circuit Type E
Schmitt Trigger
N-CH
V
DD
Pull-up
Resistor
Enable
V
DD
I/O
PNE
Pull-up
Resistor
P-CH
Output
DIsable
Data
Figure 1-8. Pin Circuit Type E-1
PRODUCT OVERVIEW KS57C21832/P21832
1-10
N-CH
V
DD
Pull-up
Resistor
Enable
V
DD
I/O
PNE
Pull-up
Resistor
P-CH
Output
DIsable
Data
Schmitt Trigger
Figure 1-9. Pin Circuit Type E-2
KS57C21832/P21832 PRODUCT OVERVIEW
1-11
Out
V
DD
V
LC1
COM
V
LC5
V
LC4
Figure 1-10. Pin Circuit Type H-3
Out
V
DD
V
LC2
SEG
V
LC5
V
LC3
Figure 1-11. Pin Circuit Type H-15
PRODUCT OVERVIEW KS57C21832/P21832
1-12
COM/SEG
Output
Disable
Type H-3
I/O
Data
Type C
V
DD
P-CH
Pull-up
Resistor
Pull-up
Resistor
Enable
Figure 1-12. Pin Circuit Type H-13
SEG
Output
Disable
Type H-15
I/O
Data
Schmitt Trigger
Type C
V
DD
P-CH
Pull-up
Resistor
Pull-up
Resistor
Enable
Figure 1-13. Pin Circuit Type H-16
KS57C21832/P21832 ELECTRICAL DATA
14-1
14 ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C21832 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
IN
— Clock timing measurement at XT
IN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA KS57C21832/P21832
14-2
Table 14-1. Absolute Maximum Ratings
(T
A
= 25 °C)
Parameter Symbol Conditions Rating Units
Supply Voltage
V
DD
– - 0.3 to + 6.5 V
Input Voltage
V
I
Ports 0-9
- 0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
–
- 0.3 to VDD + 0.3
V
Output Current High
I
OH
One I/O pin active - 15 mA
All I/O pins active - 35
Output Current Low
I
OL
One I/O pin active + 30 (Peak value) mA
+ 15
(note)
Total for ports 0, 2-9 + 100 (Peak value)
+ 60
(note)
Operating Temperature
T
A
– - 40 to + 85
°
C
Storage Temperature
T
stg
– - 65 to + 150
°
C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty .
Table 14-2. D.C. Electrical Characteristics
(T
A
= - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Units
Input High
Voltage
V
IH1
All input pins except those
specified below for V
IH2-VIH3
0.7 V
DD
–
V
DD
V
V
IH2
Ports 0, 1, 6, P3.2, P3.3, and
RESET
0.8 V
DD
V
DD
V
IH3
X
IN, XOUT,
and XT
IN
V
DD
- 0.1 V
DD
Input Low
Voltage
V
IL1
All input pins except those
specified below for V
IL2-VIL3
– –
0.3 V
DD
V
V
IL2
Ports 0, 1, 6, P3.2, P3.3, and
RESET
0.2 V
DD
V
IL3
X
IN, XOUT,
and XT
IN
0.1
Output High
Voltage
V
OH
VDD = 4.5 V to 5.5 V
I
OH
= - 1 mA
Ports 0, 2-9
V
DD
- 1.0
– – V
Output Low
Voltage
V
OL
V
DD
= 4.5 V to 5.5 V
IOL = 15 mA
Ports 0, 2-9
– – 2.0 V
KS57C21832/P21832 ELECTRICAL DATA
14-3
Table 14-2. D.C. Electrical Characteristics (Continued)
(T
A
= - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Units
Input High
Leakage
Current
I
LIH1
VI = V
DD
All input pins except those
specified below for I
LIH2
– – 3 µA
I
LIH2
VI = V
DD
X
IN, XOUT,
XT
IN
,
and RESET
20
Input Low
Leakage
I
LIL1
V
I
= 0 V
All input pins except those
specified below for I
LIH2
– – - 3 µA
Current
I
LIL2
V
I
= 0 V
X
IN, XOUT,
and XT
IN
- 20
Output High
Leakage
Current
I
LOH
V
O
= V
DD
All output pins
– – 3 µA
Output Low
Leakage
Current
I
LOL
V
O
= 0 V
All output pins
– – - 3 µA
Pull-Up
Resistor
R
LI
V
I
= 0 V; V
DD
= 5 V
Port 0-9
25 47 100
kΩ
V
DD
= 3 V
50 95 200
R
L2
V
I
= 0 V; V
DD
= 5 V, RESET
100 220 400
V
DD
= 3 V
200 450 800
LCD Voltage
Dividing
Resistor
R
LCD
TA = 25 °C
25 55 80
kΩ
|
V
DD
-COMi|
Voltage Drop
(i = 0-15)
V
DC
- 15 µA per common pin – – 120 mV
|
V
DD
-SEGx|
Voltage Drop
(x = 0-55)
V
DS
- 15 µA per segment pin – – 120
V
LC1
Output
Voltage
V
LC1
LCD clock = 0 Hz, V
LC5
= 0 V 0.8 V
DD
- 0.2 0.8 V
DD
0.8 V
DD
+ 0.2
V
V
LC2
Output
Voltage
V
LC2
0.6 V
DD
- 0.2 0.6 V
DD
0.6 VDD+ 0.2
V
LC3
Output
Voltage
V
LC3
0.4 V
DD
- 0.2 0.4 V
DD
0.4 V
DD
+ 0.2
V
LC4
Output
Voltage
V
LC4
0.2 V
DD
- 0.2 0.2 V
DD
0.2 V
DD
+ 0.2
ELECTRICAL DATA KS57C21832/P21832
14-4
Table 14-2. D.C. Electrical Characteristics (Concluded)
(T
A
= - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Units
Supply
Current
I
DD1
(2)
V
DD
= 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
–
5.1
3.9
10.0
7.5
mA
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
2.5
1.8
4.0
3.0
I
DD2
(2)
Idle mode;
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
I
DD3
(3)
V
DD
= 3 V ± 10%
32 kHz crystal oscillator
– 22.8 35 µA
I
DD4
(3)
Idle mode; V
DD
= 3 V ± 10%
32 kHz crystal oscillator
6.4 15
I
DD5
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0000B
2.5 5
Stop mode;
VDD = 3 V ± 10%
XT = 0V
0.5 3
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0100B
0.2 3
Stop mode;
VDD = 3 V ± 10%
0.1 2
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
KS57C21832/P21832 ELECTRICAL DATA
14-5
Table 14-3. Main System Clock Oscillator Characteristics
(T
A
= - 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator Clock
Configuration
Parameter Test Condition Min Typ Max Units
Ceramic
Oscillator
X
IN
C1 C2
X
OUT
Oscillation frequency
(1)
– 0.4 – 6.0 MHz
Stabilization time
(2)
Stabilization occurs
when VDD is equal
to the minimum
oscillator voltage
range; VDD = 3.0 V.
– – 4 ms
Crystal
Oscillator
X
IN
C1 C2
X
OUT
Oscillation frequency
(1)
– 0.4 – 6.0 MHz
Stabilization time
(2)
VDD = 3.0 V
– – 10 ms
VDD = 2.0 V to 5.5 V
– – 30
External
Clock
XINX
OUT
XIN input frequency
(1)
– 0.4 – 6.0 MHz
XIN input high and low
level width (t
XH, tXL
)
– 83.3 – 1250 ns
RC
Oscillator
XINX
OUT
R
Frequency
R = 20 kΩ,
VDD = 5 V
– 2 – MHz
R = 39 kΩ,
VDD = 3 V
– 1 –
NOTES:
1. Oscillation frequency and X
IN
input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
ELECTRICAL DATA KS57C21832/P21832
14-6
Table 14-4. Recommended Oscillator Constants
(T
A
= - 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Manufacturer Series
Number
(1)
Frequency Range Load Cap (pF) Oscillator Voltage
Range (V)
Remarks
C1 C2 MIN MAX
TDK
FCRM5
3.58 MHz-6.0 MHz 33 33 2.0 5.5 Leaded Type
FCRMC5
3.58 MHz-6.0 MHz
(2) (2)
2.0 5.5 On-chip C
Leaded Type
CCRMC3
3.58 MHz-6.0 MHz
(3) (3)
2.0 5.5 On-chip C
SMD Type
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
KS57C21832/P21832 ELECTRICAL DATA
14-7
Table 14-5. Subsystem Clock Oscillator Characteristics
(TA = - 40 °C + 85 °C, V
DD
= 1.8 V to 5.5 V)
Oscillator Clock
Configuration
Parameter Test Condition Min Typ Max Units
Crystal
Oscillator
XT
IN
C1 C2
XT
OUT
Oscillation
frequency
(1)
– 32 32.768 35 kHz
Stabilization time
(2)
VDD = 2.7 V to 5.5 V
– 1.0 2 s
VDD = 2.0 V to 5.5 V
– – 10
External
Clock
XTIN XTOUT
XTIN input
frequency
(1)
– 32 – 100 kHz
XTIN input high and
low level width
(t
XTL, tXTH
)
– 5 – 15 µs
NOTES:
1. Oscillation frequency and XT
IN
input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-6. Input/Output Capacitance
(TA = 25 °C, V
DD
= 0 V )
Parameter Symbol Condition Min Typ Max Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
– – 15 pF
Output
Capacitance
C
OUT
– – 15 pF
I/O Capacitance
C
IO
– – 15 pF
ELECTRICAL DATA KS57C21832/P21832
14-8
Table 14-7. A.C. Electrical Characteristics
(T
A
= - 40 °C to + 85 °C, V
DD
= 1.8 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Units
Instruction Cycle
Time
(note)
t
CY
V
DD
= 2.7 V to 5.5 V
0.67 – 64 µs
VDD = 2.0 V to 5.5 V
0.95 64
TCL0, TCL1 Input
Frequency
f
TI0,
f
TI1
V
DD
= 2.7 V to 5.5 V
0 – 1.5 MHz
V
DD
= 2.0 V to 5.5 V
1
TCL0, TCL1 Input
High, Low Width
t
TIH0,
t
TIL0
t
TIH1, tTIL1
V
DD
= 2.7 V to 5.5 V
0.48 – – µs
VDD = 2.0 V to 5.5 V
1.8
SCK Cycle Time
t
KCY
V
DD
= 2.7 V to 5.5 V; Input
800 – – ns
Internal SCK source; Output 650
VDD = 2.0 V to 5.5 V; Input
3200
Internal SCK source; Output 3800
SCK High, Low
Width
tKH, t
KL
V
DD
= 2.7 V to 5.5 V; Input
325 – – ns
Internal SCK source; Output
t
KCY
/2-
50
VDD = 2.0 V to 5.5 V; Input
1600
Internal SCK source; Output
t
KCY
/2-
150
SI Setup Time to
SCK High
t
SIK
V
DD
= 2.7 V to 5.5 V; Input
100 – – ns
V
DD
= 2.7 V to 5.5 V; Output
150
V
DD
= 2.0 V to 5.5 V; Input
150
V
DD
= 2.0 V to 5.5 V; Output
500
SI Hold Time to
SCK High
t
KSI
V
DD
= 2.7 V to 5.5 V; Input
400 – – ns
V
DD
= 2.7 V to 5.5 V; Output
400
V
DD
= 2.0 V to 5.5 V; Input
600
V
DD
= 2.0 V to 5.5 V; Output
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
KS57C21832/P21832 ELECTRICAL DATA
14-9
Table 14-7. A.C. Electrical Characteristics (Continued)
(T
A
= - 40 °C to + 85 °C, V
DD
= 1.8 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Units
Output Delay for
SCK to SO
t
KSO
V
DD
= 2.7 V to 5.5 V; Input
– – 300 ns
V
DD
= 2.7 V to 5.5 V; Output
250
V
DD
= 2.0 V to 5.5 V; Input
1000
V
DD
= 2.0 V to 5.5 V; Output
1000
Interrupt Input
High, Low Width
t
INTH, tINTL
INT0, INT1, INT2, INT4,
K0-K7
10 – – µs
RESET Input Low
Width
t
RSL
Input 10 – – µs
NOTE: Minimum value for INT0 is based on a clock of 2t
CY
or 128/fx as assigned by the IMOD0 register setting.
1.5 MHz
CPU Clock
1.05 MHz
750 kHz
15.6 kHz
Main Oscillator Frequency
(Divided by 4)
4.2 MHz
3 MHz
6 MHz
1 2 3 4 5 6 7
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
1.8 V
Figure 14-1. Standard Operating Voltage Range
ELECTRICAL DATA KS57C21832/P21832
14-10
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode
(TA = - 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply voltage
V
DDDR
– 1.8 – 5.5 V
Data retention supply current
I
DDDR
V
DDDR
= 1.8 V
– 0.1 10 µA
Release signal set time
t
SREL
– 0 – – µs
Oscillator stabilization wait
time
(1)
t
WAIT
Released by RESET
–
217/fx
– ms
Released by interrupt –
(2)
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
KS57C21832/P21832 ELECTRICAL DATA
14-11
TIMING WAVEFORMS
Execution of
STOP Instrction
Internal
RESET
Operation
~
~
V
DDDR
~
~
Stop Mode
Idle Mode
Normal ModeData Retention Mode
t
SREL
t
WAIT
RESET
V
DD
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Execution of
STOP Instrction
V
DDDR
~
~
Data Retention Mode
V
DD
Normal Mode
~
~
Stop Mode
Idle Mode
t
SREL
t
WAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
ELECTRICAL DATA KS57C21832/P21832
14-12
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Measurement
Points
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
X
IN
t
XH
t
XL
1/fx
V
DD
- 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at X
IN
XT
IN
t
XTH
t
XTL
1/fxt
V
DD
- 0.1 V
0.1 V
Figure 14-6. Clock Timing Measurement at XT
IN
KS57C21832/P21832 ELECTRICAL DATA
14-13
TCL0
t
TIH
t
TIL
1/f
TI
0.8 V
DD
0.2 V
DD
Figure 14-7. TCL Timing
RESET
t
RSL
0.2 V
DD
Figure 14-8. Input Timing for RESET Signal
INT0, 1, 2, 4,
K0 to K7
t
INTH
t
INTL
0.8 V
DD
0.2 V
DD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
ELECTRICAL DATA KS57C21832/P21832
14-14
Output Data
Input Data
SCK
t
KH
t
KCY
t
KL
0.8 V
DD
0.2 V
DD
t
KSO
t
SIK
t
KSI
0.8 V
DD
0.2 V
DD
SI
SO
Figure 14-10. Serial Data Transfer Timing
KS57C21832/P21832 MICHANICAL DATA
15-1
15 MICHANICAL DATA
OVERVIEW
The KS57C21832 microcontrollers are available in a 100-QFP-1420C package.
NOTE :
Dimensions are in millimeters.
100-QFP-1420C
#100
#1
20.00
± 0.2
14.00
± 0.2
17.90 ± 0.3
23.90
± 0.3
0.10 MAX
0.65
(0.83)
0.10 MAX
(0.58)
0.80 ± 0.20
0.05 MIN
2.65
± 0.10
3.00 MAX
0.15
+0.10
-0.05
0-8
0.3
± 0.1
0.80
± 0.20
Figure 15-1. 100-QFP Package Dimension
MICHANICAL DATA KS57C21832/P21832
15-2
NOTES
KS57C21832/P21832 KS57P21832 OTP
16-1
16 KS57P21832 OTP
OVERVIEW
The KS57P21832 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C21832 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by
serial data format.
The KS57P21832 is fully compatible with the KS57C21832, both in function and in pin configuration. Because of
its simple programming requirements, the KS57P21832 is ideal for use as an evaluation chip for the
KS57C21832.
KS57P21832 OTP KS57C21832/P21832
16-2
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
P0.0/
SCK
/K0
P0.1/SO/K1
SDAT
/P0.2/SI/K2
SCLK
/P0.3/BUZ/K3
VDD/V
DD
VSS/V
SS
X
OUT
X
IN
VPP/TEST
XT
IN
XT
OUT
RESET
/RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
P4.0/COM8
P4.1/COM9
P4.2/COM10
P4.3/COM11
P5.0/COM12
P5.1/COM13
P5.2/COM14
P5.3/COM15
P6.0/SEG55/K4
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
KS57P21832
(100-QFP-1420C)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31323334353637383940414243444546474849
50
100
99989796959493929190898887868584838281
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. KS57P21832 Pin Assignments (100-QFP Package)
KS57C21832/P21832 KS57P21832 OTP
16-3
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P0.2 SDAT 13 I/O Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P0.3 SCLK 14 I/O Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
19 I Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
RESET RESET 22 I Chip initialization
VDD/V
SS
VDD/V
SS
15/16 I
Logic power supply pin. V
DD
should be tied to
+ 5 V during programming.
Table 16-2. Comparison of KS57P21832 and KS57C21832 Features
Characteristic KS57P21832 KS57C21832
Program Memory 32 Kbyte EPROM 32 Kbyte mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V 1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, V
PP
(TEST) = 12.5 V
Pin Configuration 100 QFP 100 QFP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the KS57P21832, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W Mode
5 V 5 V 0 0000H 1 EPROM read
12.5 V 0 0000H 0 EPROM program
12.5 V 0 0000H 1 EPROM verify
12.5 V 1 0E3FH 0 EPROM read protection
NOTE: "0" means Low level; "1" means High level.
KS57P21832 OTP KS57C21832/P21832
16-4
Table 16-4. D.C. Electrical Characteristics
(T
A
= - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Units
Supply
Current
I
DD1
(2)
V
DD
= 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
–
5.1
3.9
10.0
7.5
mA
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
2.5
1.8
4.0
3.0
I
DD2
(2)
Idle mode;
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
I
DD3
(3)
V
DD
= 3 V ± 10%
32 kHz crystal oscillator
– 22.8 35 µA
I
DD4
(3)
Idle mode; V
DD
= 3 V ± 10%
32 kHz crystal oscillator
6.4 15
I
DD5
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0000B
2.5 5
Stop mode;
VDD = 3 V ± 10%
XT = 0V
0.5 3
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0100B
0.2 3
Stop mode;
VDD = 3 V ± 10%
0.1 2
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
KS57C21832/P21832 KS57P21832 OTP
16-5
1.5 MHz
CPU Clock
1.05 MHz
750 kHz
15.6 kHz
Main Oscillator Frequency
(Divided by 4)
4.2 MHz
3 MHz
6 MHz
1 2 3 4 5 6 7
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
1.8 V
Figure 16-2. Standard Operating Voltage Range
KS57P21832 OTP KS57C21832/P21832
16-6
NOTES
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