Page 1
32-Channel LCD Driver
with Separate Backplane Output
Ordering Information
Package Options
Device
HV66 HV66PG HV66PJ HV66X
44 Lead Quad 44 J-Lead Quad Die
Plastic Gullwing Plastic Chip Carrier in waffle pack
HV66
Features
❏ Processed with HVCMOS® technology
❏ 32 push-pull CMOS output up to 32V
❏ Low power level shifting
❏ Source/sink current minimum 1mA
❏ Shift register speed 5MHz
❏ Latched data outputs
❏ Bidirectional shift register (DIR)
❏ Backplane output
Absolute Maximum Ratings
Supply voltage, V
Output voltage, V
Logic input levels
Ground current
Continuous total power dissipation
Operating temperature range -40°C to +85°C
Storage temperature range -65°C to +125°C
Lead temperature 1.6mm (1/16 inch) 260°C
from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to V
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.
2
DD
2
PP
2
3
4
.
SS
-0.5V to VDD + 0.5V
1
-0.5V to +7.0V
-0.5V to +35V
1.5A
1200mW
General Description
Not recommended for new designs.
The HV66 is a low-voltage serial to high-voltage parallel converter
with push-pull outputs. This device has been designed for use as
a driver circuit for LCD displays. It can also be used in any
application requiring multiple output high-voltage current sourcing and sinking capabilities. The inputs are fully CMOS compatible.
The device consists of a 32-bit shift register, 32 latches, and
control logic to perform blanking and polarity control of the
outputs. HVout1 is connected to the first stage of the shift register.
Data is shifted through the shift register on the logic rising
transition of the clock. A DIR pin causes data shifting counterclockwise when grounded and clockwise when connected to V
A data output buffer is provided for cascading devices. This output
reflects the current status of the last bit of the shift register.
Operation of the shift register is not affected by the LE (latch
enable), BL (blank) or the POL (polarity) inputs. Transfer of data
from the shift register to the latch occurs when the LE (latch
enable) input is high. The data in the latch is stored after LE
transitions from high to low.
The blank signal, BL, when pulled low, will set all outputs to the
same state as the BP
. If this signal is left open then the BL
OUT
defaults to a high state.
DD
.
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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Page 2
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics (V
Symbol Parameter Min Max Units Conditions
I
DD
I
PPQ
I
DDQ
V
V
I
IH
I
IL
V
V
OH
OL
OLBP
OHBP
VDD supply current 15 mA VDD = VDD max
High voltage supply current 0.5 mA Outputs high
Quiescent VDD supply current 0.5 mA All VIN = VSS or V
High-level output Q 22 V IO= 1mA, VPP = 24V
Low-level output Q 2 V IO= 1mA
High-level logic input current 1 µAVIH = V
Low-level logic input current -1 µAVIL = 0V
Low-level output voltage, backplane 3 V IO = 10mA
High-level output voltage, backplane 29 V IO = -10mA
= 5V, VPP = 32V, VSS = GND)
DD
0.5 mA Outputs low
Data out 4.6 V IO= -100µA
Data out 0.4 V I
f
= 5MHz
CLK
= 100µA
O
HV66
DD
DD
AC Characteristics (V
= 5V, VPP = 32V, TC = 25°C), logic input rises/fall time = 10ns.
DD
Symbol Parameter Min Max Units Conditions
f
CLK
t
W
t
SU
t
H
tON, t
OFF
t
, t
ON
OFF
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
t
, t
BR
BF
tBR - tBF BP
Clock frequency 5 MHz
Clock width high or low 100 ns
Data set-up time before clock rises 25 ns
Data hold time after clock rises 50 ns
Time from latch enable or POL to HV
OUT
500 ns CL = 20pF
Time from POL to BP output 500 ns CL = 20pF
Delay time clock to data high to low 200 ns CL = 10pF
Delay time clock to data low to high 200 ns CL = 10pF
Delay time clock to LE low to high 50 ns
Width of LE pulse 100 ns
LE set-up time before clock rises 50 ns
BP
rise/fall time 10 1000 µsCL = 350nF
OUT
rise and fall difference 100 µsCL = 350nF
OUT
Recommended Operating Conditions
Symbol Parameter Min Max Units
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
I
OD
Notes:
*Output will not switch below 12V.
Power-up sequence should be the following:
1. Connect ground. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
2. Apply V
Power-down sequence should be the reverse of the above.
The V
should not drop below VDD during operation.
PP
.4.Apply VPP.
DD
Logic supply voltage 4.5 5.5 V
Output voltage* 0 32 V
High-level input voltage 2.4 V
DD
Low-level input voltage 0 0.8 V
Clock frequency 0 5 MHz
Operating free-air temperature -40 +85 °C
Allowable current through output diodes 200 mA
V
2
Page 3
Switching Waveforms
Clock
Data Out
Latch Enable
50% 50% 50%
HV66
V
IH
Data Valid50% 50%Data Input
V
t
SU
t
H
IL
V
IH
50%
V
t
WL
t
WH
IL
V
OH
50%
V
OL
V
OH
V
OL
V
IH
V
OL
t
DLE
t
DLH
t
DHL
50%
t
50%
WLE
50%
t
SLE
HV
OUT
w/ S/R LOW
HV
OUT
w/ S/R HIGH
POL
(ASYNCH
w/ Clock)
BP
OUT
50%
t
OFF
50%
t
OFF
t
ON
50%
10%
t
ON
50%
V
OH
50%
50%
90%
t
BR
t
BF
V
V
V
V
V
OL
OH
OL
OHBP
OLBP
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Page 4
Functional Block Diagram
V
PP
Polarity
Blank
Latch Enable
V
DD
Data Input
Latch
HV
OUT
HV66
1
Clock
Latch
HV
OUT
2
32-Bit
Shift
DIR
Register
(Outputs 3 to 30
not shown)
HV
31
HV
BP
OUT
OUT
OUT
32
Latch
Data Out
Latch
GND
Function Table
Inputs Outputs
Function Data CLK LE BL POL DIR Shift Reg HV Outputs Data Out BP
1 2…32 1 2…32 2…32 *
Load S/R H or L ↑ LHHXH or L *…* * *…* * H
Load latches X H or L L H H X * *…* * *…* * H
XH or L L H L X * *…* * *…* * L
L ↑ HHHXL*…* H *…* * H
Transparent H ↑ HHHXH*…* L *…* * H
Mode
R/L Shift X ↑ XHX HQn → Qn+1 * *…* Q32
Blank X X X L L X * *…* L L…L * L
Control X X X L H X * *…* H H…H * H
Notes:
H = high level, L = low level, X = irrelevant,
* = dependent on previous stage’s state before the last CLK or last LE high.
L ↑ HHL XL*…* L *…* * L
H ↑ HHLXH*…* H *…* * L
X ↑ XHX LQn → Qn-1 * *…* Q1
↑ = low-to-high transition.
OUT
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HV66
Pin Configuration
HV66
44 Pin Plastic Gullwing (QFP) Package
Pin Function Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 HV
19 HV
20 HV
21 HV
22 HV
Note:
Pin designation for DIR = H/L
Example:for DIR = H, Pin 1 is HV
22/11 23 Data Out
OUT
21/12 24 GND
OUT
20/13 25 N/C
OUT
19/14 26 BL
OUT
18/15 27 POL
OUT
17/16 28 LE
OUT
16/17 29 V
OUT
15/18 30 Clock
OUT
14/19 31 DIR
OUT
13/20 32 Data In
OUT
12/21 33 V
OUT
11/22 34 BP Out
OUT
10/23 35 HV
OUT
9/24 36 HV
OUT
8/25 37 HV
OUT
7/26 38 HV
OUT
6/27 39 HV
OUT
5/28 40 HV
OUT
4/29 41 HV
OUT
3/30 42 HV
OUT
2/31 43 HV
OUT
1/32 44 HV
OUT
22
for DIR = L, Pin 1 is HV
OUT
OUT
11
DD
PP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
32/1
31/2
30/3
29/4
28/5
27/6
26/7
25/8
24/9
23/10
Package Outline
40
42
44
1
2
3
4
5
6
7
8
9
10
11
12
41
43
13 14 151617
top view
44-pin PQFP Package
39 38 37 36 35 34
20
19
18
21
33
32
31
30
29
28
27
26
25
24
23
22
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HV66
Pin Configuration
HV66
44 Pin J-Lead Package
Pin Function Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 Data Out 40 HV
19 GND 41 HV
20 N/C 42 HV
21 BL 43 HV
22 POL 44 HV
Note:
1. Pin designation for DIR = H/L
Example:for DIR = H, Pin 1 = HV
17/16 23 LE
OUT
16/17 24 V
OUT
15/18 25 Clock
OUT
14/19 26 DIR
OUT
13/20 27 Data In
OUT
12/21 28 V
OUT
11/22 29 BP Out
OUT
10/23 30 HV
OUT
9/24 31 HV
OUT
8/25 32 HV
OUT
7/26 33 HV
OUT
6/27 34 HV
OUT
5/28 35 HV
OUT
4/29 36 HV
OUT
3/30 37 HV
OUT
2/31 38 HV
OUT
1/32 39 HV
OUT
for DIR = L, Pin 1 = HV
OUT
OUT
17
16
DD
PP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
32/1
31/2
30/3
29/4
28/5
27/6
26/7
25/8
24/9
23/10
22/11
21/12
20/13
19/14
18/15
Package Outline
39 38 37 36 35 34
40
41
42
43
44
1
2
3
4
5
6
7 8 9 10 11 12
top view
44-pin PLCC
33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
13 14 15 16 17
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
02/06//02
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
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www.supertex.com
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