5V CMOS inputs
Up to 80V modulation voltage
Capable of 128 levels of gray shading
20MHz data throughput rate
32 outputs per device (can be cascaded)
Pin-programmable shift direction (DIR)
D/A conversion cycle time is 32µs
Diodes in output structure allow usage
in energy recovery systems
Integrated HVCMOS® technology
Available in 3-sided 64-lead gullwing package
Absolute Maximum Ratings
Supply voltage, V
Supply voltage, V
Logic input levels
Ground current
Continuous total power dissipation
Operating temperature range-40°C to +70°C
Storage temperature range-65°C to +150°C
Lead temperature 1.6mm (1/16 inch)260°C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 70°C at 22.2mW/°C.
1
DD
1
PP
1
2
3
-0.5V to +7.5V
-0.5V to +90V
-0.5 to VDD + 0.5V
1.5A
1W
General Description
The HV623 is a 32-channel driver IC for gray shade display use.
It is designed to produce varying output voltages between 3 and
80 volts. This amplitude modulation at the output is facilitated by
an external ramp voltage V
explanation.
This device consists of a dual 16-bit shift registers, 32 data latches
and comparators, and control logic to preform 128 levels of gray
shading. There are 7 bits of data inputs. Data is shifted through the
shift registers at both edges of the clock, resulting a data transfer
rate of twice of the shift clock frequency. When the DIR pin is high,
CSI/CSO is the input/output for the chip select pulse. When DIR
is low, CSI/CSO is the output/input for the chip select pulse. The
DIR = HIGH also allows the HV623 to shift data in the counterclockwise direction when viewed from the top of the package.
When the DIR pin is low, data is shifted in the clockwise direction.
The output circuitry allows the energy which is stored in the output
capacitance to be returned to V
output transistor.
. See Theory of Operation for detailed
R
through the body diode of the
PP
12-122
Page 2
HV623
Electrical Characteristics (at T
= 25°C, over operating conditions unless otherwise specified)
A
Low-Voltage DC Characteristics (Digital)
1
SymbolParameterMinTyp
I
DD
I
DDQ
I
IH
I
IL
C
IN
I
OH
I
OL
Notes
1. All typical values are at V
2. Guaranteed by design.
VDD supply current1220mAf
Quiescent VDD supply current100µAAll VIN = 0V, VDD = max
High-level input current1.050µAVIH = V
Low-level input current-1.0-50µAVIL = 0V
Maximum delta voltage between high voltage outputs±0.2VAt all gray levels
of the same level
Recommended Operating Conditions
SymbolParameterMinTypMaxUnits
V
DD
V
DD
V
IH
V
IL
V
BIAS
V
CTL
V
PP
V
R
f
SC
T
A
Notes:
Power-up sequence should be the following:
1. Connect ground. 2. Apply V
Power-down sequence should be the reverse of the above.
Low-voltage digital supply voltage4.55.05.5V
Low-voltage analog supply voltage4.55.05.5V
High-level input voltage (analog and digital)VDD -1V
DD
Low-level input voltage (analog and digital)01V
IPP control circuit bias voltage-20V
IPP control circuit control voltage02V
High-voltage supply-0.380V
Ramp voltage0VPP -2V
Shift clock operating frequency (at VDD = 5.5V)10.2MHz
Operating free-air temperature-4070°C
. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP.
DD
V
12-123
Page 3
HV623
Electrical Characteristics
AC Characteristics (V
Logic Timing
SymbolParameterMinTypMaxUnitsConditions
f
SC
f
DIN
t
SS
t
HS
t
WA
t
DS
t
DH
t
WD
t
WLC
t
DLCR
1
t
DRCC
t
DSL
t
CSC
t
WSC
t
CCC
t
WCC
Note 1: Count clock starts counting after 0.47µs min. This is equivalent to a time duration for a linear ramp VR to ramp from 0 to 3V, assuming the minimum value of TRR,
ramp size time of 12µs for V
Shift clock operating frequency10.2MHz
Data-in frequency20.4MHz
CSI/CSO pulse to shift clock setup time40ns
CSI/CSO pulse to shift clock hold time0ns
CSI pulse width49ns
Data to shift clock setup time20ns
Data to shift clock hold time0ns
Data-in pulse width24ns
Load count pulse width98ns
Load count to ramp delay1µs
Ramp to count clock delay0.47µs
Shift clock to load count delay time98ns
Shift clock cycle time98ns
Shift clock pulse width49ns
Count clock cycle time98ns
Count clock pulse width49ns
= 5.5V, TA = 25°C)
DD
= 80V.
R
V
RAMP
Timing
SymbolParameterMinTypMaxUnitsConditions
t
CR
t
RR
2
t
HR
t
FR
Note 2: The maximum ramp hold time may be longer than 15 µs, but the output voltage HV
Cycle time of ramp signal15µs
Ramp rise time12µs
Ramp hold time215µs
Ramp fall timeTBD3µs
will droop due to leakage.
OUT
Table 1:
Schemes to control IPP bias current, typical I
Option 1 Option 2
BIAS
V
CTLRCTL
V
(V)(V)(Ω)(mA)(V)(V)(Ω)(mA)
00.156K2-1.0056K4
01.056K7-2.0056K5.5
I
PP
V
PP
BIASVCTLRCTL
V
CTL
R
HV623
CTL
I
PP
V
CTL
+
-
R
CTL
+
V
-
BIAS
12-124
Page 4
Pin Definitions
Pin #NameFunction
30-36D1-D7Inputs for binary-format parallel data.
26SC (Shift Clock) Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock
rate (data rate = 20MHz max if clock rate = 10MHz max).
22CSI (ChipInput pin for the chip select pulse (when DIR is high).
Select Input)Output pin for the chip select pulse (when DIR is low).
43CSO (ChipInput pin for the chip select pulse (when DIR is low).
Select Output)Output pin for the chip select pulse (when DIR is high).
40LCInput for a pulse whose rising edge causes data from the input latches to enter the comparator latches,
(Load Count)and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).
Also, the HV
42CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.
18, 47V
R
High-voltage ramp input for charging the output stage hold capacitors (CH).
This input can be linear or non-linear as desired.
28DIRWhen this pin is connected to V
i.e., corresponding to HV
in descending order, i.e., corresponding to HV
27, 38LVGNDThis is ground for the logic section.
HVGND and LVGND should be connected together externally.
17, 48HVGNDThis is ground for the high-voltage (output) section.
HVGND and LVGND should be connected together externally.
19, 45V
1-16HV
49-64HV
21V
29V
DD
DD
24V
PP
1-High-voltage outputs.
OUT
32
OUT
(Analog)Low-voltage analog supply voltage.
(Digital)Low-voltage digital supply voltage.
CTL
This input biases the output source followers.
Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (V
particular panel). The combination of V
±0.2V of delta voltage between high voltage outputs of the same level at all gray levels.
25R
CTL
Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs
= 56KΩ for a particular panel). See V
(R
CTL
will clear to zero after the load count is initiated.
OUT
, input data is shifted in ascending order,
DD
OUT
1 to HV
32. When connected to LVGND, input data is shifted
OUT
CTL
32 to HV
OUT
and R
CTL
will reduce the output voltage variation to less than
CTL
function above.
OUT
1.
= 2V for a
CTL
HV623
Input and Output Equivalent Circuits
V
DD
Input
GND
(Logic)
Logic Inputs
12-125
V
DD
GND
(Logic)
Data Out
Logic Data Output
Page 5
HV623
Output Stage Detail
V
R
C
H
V
CTL
R
CTL
Internal
Logic
&
Bias
Circuit
Test Circuit
High-voltage Analog Output Source Current (I
For gray shade #1 (000 0000)
V
PP
70V
Q
1
HV
OUT
Q
2
0V
1. Set HV
2. Apply V
3. Apply a step voltage of 70V at V
4. Measure voltage across the 1KΩ resistor.
5. Output source current can be calculated by using
OUT
+
–
PP
HV623
Logic
= Low.
= 80V.
V
R
Output
Stage
HVGNDLVGND
(slew rate = 4.1V/µs).
R
V
PP
V
1K
= 80V
tst
.
AOH
)
HV
OUT
+
1KΩ V
tst
-
10KΩ
Functional Block Diagram
1
31
32
I/O
Buffers
2
SC
SC
Shift
Clock
Buffer
V
R
CTL
CTL
DIR
I/O
Buffers
Dual
16-bit
Shift Registers
L/E
L/E
L/E
L/E
Data
Latches
Data
Latches
Data
Latches
Data
Latches
Data In
Buffers
7
7
Load
7
7
Latches and
Comparators
Latches and
Comparators
Count
Latches and
Comparators
Latches and
Comparators
7
7
7
7
7
Clear
Pulse
Generator
Clear
Count
Load
RS
F/F
RS
F/F
RS
F/F
RS
F/F
Counter
Load
Count
Buffer
See Output Stage Detail
GND
V
V
PP
R
Output
Stage
Output
Stage
Output
Stage
Output
Stage
CC
Reset
Counter
Count
Clock
Buffer
HV
HV
HV
HV
OUT
OUT
OUT
OUT
1
2
31
32
CSI
SC = Shift Clock
LC = Load Count
CC = Count Clock
CSO
CSI = Chip Select Input
CSO = Chip Select Output
*Strobe = twice the SC frequency
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Package Outlines
1
Index
top view
24
2540
3-Sided Plastic QFP 64-pin Gullwing Package
64
41
*Analog VDD and digital VDD may be connected
separately for better noise immunity.
Theory of Operation
The HV623 has two primary functions:
1) Loading data from the data bus and,
2) Gray-shade conversion
(converting latched data to output voltages).
Since the device was developed initially for flat panel displays, the
operation will be described in terms that pertain to that technology. As shown by the Typical Drive Scheme, several HV623
packages are mounted at the top and bottom of a display panel.
Data exists on a 7-bit bus (adjacent PC board traces) at top and
bottom. The D1 through D7 inputs of each chip take data from the
bus when either a CSI or CSO pulse is present at the chip. These
pulses therefore act as a combination CHIP SELECT and LOCATION STROBE. Because of the way the chip HV
sequenced, data on the bus at the bottom of the display panel will
be entered into the left-most chip as HV
32. The CSI pulse will accomplish this with DIR = High.
HV
OUT
OUT1, HVOUT2,
pins are
OUT
etc. up to
Loading Data from Data Bus
Here is the full data-entry sequence:
1) The microcontroller puts data on the bus (7 bits)
2) To enter the data into the 32 sets of 7 latches on the first chip,
the shift clock rises. This positive transition is combined with
the CSI pulse and is generated only once to strobe the data into
the first set of latches. (These latches eventually send data to
the HV
falls, and this negative transition is combined with the CSI
pulse, which is now propagated internally, to strobe the new
data into the next set of 7 latches (which will end up as
HV
shift clock rate.
3) When the last set of 7 latches in the first chip has been loaded
(HV
exit pin is called CSO and the chip 2 entry pin is CSI . For chips
at the top of the panel things are reversed: DIR is low, entry pins
are CSO and exit pins are CSI , because the data-into-latches
sequence is in descending order, HV
4) The buses may of course be separate, and data can be strobed
in on an interleaved basis, etc., but those complications will be
left to systems designers.
1). The data on the bus then changes, the shift clock
OUT
2). This internal CSI pulse therefore runs at twice the
OUT
32), the CSI pulse leaves chip 1 and enters chip 2. The
OUT
32 down to HV
OUT
OUT
1.
12-130
Page 10
HV623
When data has been loaded into all 32 outputs of all chips (top and
bottom of the display panel), the load count pin is pulsed. On its
rising transition, all output levels are reset to zero and all the data
in the input latches is transferred to a like number of comparator
latches, (thus leaving the data latches ready to receive new data
during the following operations). After the transfer, the load count
pin is brought low. This transition begins the events that convert
the binary data into a gray-shade level.
Gray-shade Conversion
1) The COUNT CLOCK is started. An external signal is applied
to the COUNT CLOCK pin, causing the counter on each chip
to increment from binary 000 0000 to 111 1111 (0 to 127).
2) At the same time, the V
charging transistors, causing the HOLD CAPACITOR (C
each output to experience a rise in voltage.
3) The logic control compares the count in the comparator latch
to the count clock. The gate voltage of Q
voltage HV
4) Once V
will ramp up at the same rate as VR.
OUT
has reached the maximum voltage, then all the pixels
R
will be at the final value. (See Output Gray Scale Voltage.)
voltage is applied to all chips, via
R
H
and the output
1
) on
Output Voltage Variation
The output voltage of the HV623 is determined by the logic and
the ramp voltage V
coupled to an unacceptable level due to its adjacent outputs
through the panel. In order to solve this problem, internal logic
(refer to Output Stage Detail) is integrated in the IC to minimize
the effect.
Two external pins V
current flowing through Q
source and the R
(2V and 56KΩ are used for a particular panel). The internal bias
circuit will drive the resistor to a voltage level that is equal to the
voltage at steady state through an operational amplifier. The
V
CTL
current flowing through Q1 and Q2 will be limited to V
This combination of V
variation to less than ±0.2V of delta voltage for each gray shade,
independent of its adjacent output voltages.
. It is possible that the output voltage may be
R
and R
CTL
pin is connected to ground through a resistor
CTL
CTL
allow the feasibility to control the
CTL
. The V
2
and R
pin is connected to a voltage
CTL
will reduce the output voltage
CTL
CTRL/RCTRL
.
12-131
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