Datasheet HV623PG Datasheet (Supertex)

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Page 1

32-Channel 128-Level Amplitude Gray-Shade

Display Column Driver

Ordering Information

Package Option

Device 64-Lead 3-sided Plastic Gullwing

HV623 HV623PG

HV623

Features

5V CMOS inputs Up to 80V modulation voltage Capable of 128 levels of gray shading 20MHz data throughput rate 32 outputs per device (can be cascaded) Pin-programmable shift direction (DIR) D/A conversion cycle time is 32µs Diodes in output structure allow usage

in energy recovery systems Integrated HVCMOS® technology Available in 3-sided 64-lead gullwing package

Absolute Maximum Ratings

Supply voltage, V Supply voltage, V Logic input levels Ground current Continuous total power dissipation Operating temperature range -40°C to +70°C Storage temperature range -65°C to +150°C Lead temperature 1.6mm (1/16 inch) 260°C

from case for 10 seconds

Notes:

1. All voltages are referenced to GND.

2. Duty cycle is limited by the total power dissipated in the package.

3. For operation above 25°C ambient derate linearly to 70°C at 22.2mW/°C.

-0.5V to +7.5V

-0.5V to +90V

-0.5 to VDD + 0.5V

1.5A 1W

General Description

The HV623 is a 32-channel driver IC for gray shade display use. It is designed to produce varying output voltages between 3 and 80 volts. This amplitude modulation at the output is facilitated by an external ramp voltage V explanation.

This device consists of a dual 16-bit shift registers, 32 data latches and comparators, and control logic to preform 128 levels of gray shading. There are 7 bits of data inputs. Data is shifted through the shift registers at both edges of the clock, resulting a data transfer rate of twice of the shift clock frequency. When the DIR pin is high, CSI/CSO is the input/output for the chip select pulse. When DIR is low, CSI/CSO is the output/input for the chip select pulse. The DIR = HIGH also allows the HV623 to shift data in the counterclockwise direction when viewed from the top of the package. When the DIR pin is low, data is shifted in the clockwise direction.

The output circuitry allows the energy which is stored in the output capacitance to be returned to V output transistor.

. See Theory of Operation for detailed

through the body diode of the

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HV623

Electrical Characteristics (at T

= 25°C, over operating conditions unless otherwise specified)

Low-Voltage DC Characteristics (Digital)

Symbol Parameter Min Typ

DDQ

Notes

1. All typical values are at V

2. Guaranteed by design.

VDD supply current 12 20 mA f

Quiescent VDD supply current 100 µA All VIN = 0V, VDD = max High-level input current 1.0 50 µAVIH = V Low-level input current -1.0 -50 µAVIL = 0V

Input capacitance (data, LC, SC, CC) 15 pF VIN = 0V, f = 1MHz High-level output current -2 mA VDD = 4.5V Low-level output current 2 mA VDD = 4.5V

= 5.0V.

Max Units Conditions

= 10MHz

= 8MHz

Low-Voltage DC Characteristics (Analog)

Symbol Parameter Min Typ Max Units Conditions

DDQ

VDD supply current 100 µAfSC =10MHz

= 8MHz

Quiescent VDD supply current 100 µA All VIN = 0V, VDD = max

High-Voltage Bias Circuit for Output Variation Control

Symbol Parameter Min Typ Max Units Conditions

VPP supply current for bias circuit 2 mA Depending on external

bias circuit, see Table 1.

High-Voltage DC Characteristics

Symbol Parameter Min Typ Max Units Conditions

AOH

High-voltage analog output source current See Performance Curves mA VPP = 80V

See test circuit

AOL

∆V

High-voltage analog output sink current See Performance Curves mA VPP = 80V, VDD = 4.5V

= 2V

Maximum delta voltage between high voltage outputs ±0.2 V At all gray levels of the same level

Recommended Operating Conditions

Symbol Parameter Min Typ Max Units

BIAS

CTL

Notes:

Power-up sequence should be the following:

1. Connect ground. 2. Apply V Power-down sequence should be the reverse of the above.

Low-voltage digital supply voltage 4.5 5.0 5.5 V Low-voltage analog supply voltage 4.5 5.0 5.5 V High-level input voltage (analog and digital) VDD -1 V

Low-level input voltage (analog and digital) 0 1 V IPP control circuit bias voltage -2 0 V IPP control circuit control voltage 0 2 V High-voltage supply -0.3 80 V Ramp voltage 0 VPP -2 V Shift clock operating frequency (at VDD = 5.5V) 10.2 MHz Operating free-air temperature -40 70 °C

. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP.

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HV623

Electrical Characteristics

AC Characteristics (V Logic Timing

Symbol Parameter Min Typ Max Units Conditions

DIN

WLC

DLCR

DRCC

DSL

CSC

WSC

CCC

WCC

Note 1: Count clock starts counting after 0.47µs min. This is equivalent to a time duration for a linear ramp VR to ramp from 0 to 3V, assuming the minimum value of TRR,

ramp size time of 12µs for V

Shift clock operating frequency 10.2 MHz Data-in frequency 20.4 MHz CSI/CSO pulse to shift clock setup time 40 ns CSI/CSO pulse to shift clock hold time 0 ns CSI pulse width 49 ns Data to shift clock setup time 20 ns Data to shift clock hold time 0 ns Data-in pulse width 24 ns Load count pulse width 98 ns Load count to ramp delay 1 µs Ramp to count clock delay 0.47 µs Shift clock to load count delay time 98 ns Shift clock cycle time 98 ns Shift clock pulse width 49 ns Count clock cycle time 98 ns Count clock pulse width 49 ns

= 5.5V, TA = 25°C)

= 80V.

RAMP

Timing

Symbol Parameter Min Typ Max Units Conditions

Note 2: The maximum ramp hold time may be longer than 15 µs, but the output voltage HV

Cycle time of ramp signal 15 µs Ramp rise time 12 µs Ramp hold time 2 15 µs Ramp fall time TBD 3 µs

will droop due to leakage.

OUT

Table 1:

Schemes to control IPP bias current, typical I

Option 1 Option 2

BIAS

CTLRCTL

(V) (V) (Ω) (mA) (V) (V) (Ω) (mA)

0 0.1 56K 2 -1.0 0 56K 4 0 1.0 56K 7 -2.0 0 56K 5.5

BIASVCTLRCTL

CTL

HV623

CTL

BIAS

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Pin Definitions

Pin # Name Function

30-36 D1-D7 Inputs for binary-format parallel data. 26 SC (Shift Clock) Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock

rate (data rate = 20MHz max if clock rate = 10MHz max).

22 CSI (Chip Input pin for the chip select pulse (when DIR is high).

Select Input) Output pin for the chip select pulse (when DIR is low).

43 CSO (Chip Input pin for the chip select pulse (when DIR is low).

Select Output) Output pin for the chip select pulse (when DIR is high).

40 LC Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,

(Load Count) and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).

Also, the HV 42 CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches. 18, 47 V

High-voltage ramp input for charging the output stage hold capacitors (CH).

This input can be linear or non-linear as desired. 28 DIR When this pin is connected to V

i.e., corresponding to HV

in descending order, i.e., corresponding to HV 27, 38 LVGND This is ground for the logic section.

HVGND and LVGND should be connected together externally. 17, 48 HVGND This is ground for the high-voltage (output) section.

HVGND and LVGND should be connected together externally. 19, 45 V 1-16 HV

49-64 HV 21 V 29 V

24 V

1- High-voltage outputs.

OUT

(Analog) Low-voltage analog supply voltage.

(Digital) Low-voltage digital supply voltage.

CTL

This input biases the output source followers.

Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (V

particular panel). The combination of V

±0.2V of delta voltage between high voltage outputs of the same level at all gray levels. 25 R

CTL

Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs

= 56KΩ for a particular panel). See V

CTL

will clear to zero after the load count is initiated.

OUT

, input data is shifted in ascending order,

OUT

1 to HV

32. When connected to LVGND, input data is shifted

OUT

CTL

32 to HV

OUT

and R

CTL

will reduce the output voltage variation to less than

CTL

function above.

OUT

= 2V for a

CTL

HV623

Input and Output Equivalent Circuits

Input

GND (Logic)

Logic Inputs

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GND (Logic)

Data Out

Logic Data Output

Page 5

HV623

Output Stage Detail

CTL

Internal

Logic

Bias

Circuit

Test Circuit

High-voltage Analog Output Source Current (I For gray shade #1 (000 0000)

70V

OUT

1. Set HV

2. Apply V

3. Apply a step voltage of 70V at V

4. Measure voltage across the 1KΩ resistor.

5. Output source current can be calculated by using

OUT

+ –

HV623

Logic

= Low.

= 80V.

Output

Stage

HVGNDLVGND

(slew rate = 4.1V/µs).

= 80V

tst

AOH

)

OUT

1KΩ V

tst

10KΩ

Functional Block Diagram

I/O

Buffers

SC SC

Shift Clock Buffer

CTL

DIR

I/O

Buffers

Dual

16-bit

Shift Registers

L/E

Data

Latches

Data

Latches

Data

Latches

Data

Latches

Data In Buffers

Load

Latches and

Comparators

Latches and

Comparators

Count

Latches and

Comparators

Latches and

Comparators

Clear Pulse

Generator

Clear

Count

Load

RS F/F

Counter

Load Count Buffer

See Output Stage Detail

GND

Output

Stage

Output

Stage

Output

Stage

Output

Stage

Reset

Counter

Count Clock Buffer

OUT

CSI

SC = Shift Clock LC = Load Count CC = Count Clock

CSO

CSI = Chip Select Input CSO = Chip Select Output *Strobe = twice the SC frequency

CCLCD1D7

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Typical Panel Connections

Data Bus

(7)

DIR = LOW

VR, V LVGND, HVGND, SC, LC, CC, CSO

HV623

132132132

Display Panel

(Example)

, V

LVGND, HVGND,

SC, LC, CC, CSI

DIR = HIGH

Data Bus

(7)

Gray Shade Decoding Scheme

Shade Number D7 D6 D5 D4 D3 D2 D1

128 1111111 127 1111110 126 1111101 125 1111100 124 1111011 123 1111010 122 1111001 121 1111000

7 0000110 6 0000101 5 0000100 4 0000011 3 0000010 2 0000001 1 0000000

Gray Scale Voltage

1 2 • • • 127

Clock Cycle

321321321

(000 0000)

(111 1111)

HV HV

OUT

Gray Scale Voltage

OUT OUT

OUT

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Page 7

Function Table

Sequence Function DIR Data-In CSI CSO Shift Load Count V

(D1 - D7) Clock Count Clock

1 Shift Data H H Output L L L L

from HV

1 to 32 L H

OUT

2 Shift Data L H Output L L L L

from HV

32 to 1 L H

OUT

3 Load Shift Register X X L L L 4 Load Counter X X Pre-define by 1 or 2 L L L 5 Counting/Voltage X X L L Initiates -

Conversion V

RAMP

Timing Diagrams

(a) Basic System Timing

HV623

OUT

Chip Select

Input (CSI)

Chip Select

Output (CSO)

Shift Clock

(SC)

Data In

(D1 - D7)

Load Count*

(LC)

Count Clock

(CC)

OUT

Load

First

Device

↓↑

12345 128

Load

Second

Device

↑↓↑↓↑↓↑↓↑↓↑↓↑↓↑↓↑↓↑↓↑

↓↑ ↓↑

↓

Data from Data Bus (See Detailed Timing)

DLCR

↑↑↑↑↑↑

Load

Last

Device

↓↑↓↑↓↑↓↑

↑↑↑↑↑↑

12345 128

*HV

will clear to zero with load count.

OUT

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(b) Detailed Device Timing

Chip Select

Input (CSI)

SC 1

Shift Clock

(SC)

LOADING LAST DEVICE NEXT LOADING CYCLE

CSC

SC 2 SC 16 SC 1 SC 16

HV623

Data

(D1-D7)

Load Count

(LC)

Count Clock

(CC)

DATA SET 1

DATA

SET 2

DATA SET 3

Typical Performance Curves

Source Output Characteristics

DATA

SET 31

DATA

SET 32

WCC

CCC

Clock 128

DATA

SET 31

Count

80V

DATA SET 1

DSL

WLC

Count

Clock 1

DLCR

DRCC

Sink Output Characteristics

(milliamperes)

021435678 021435678

Volts VGS Volts

(milliamperes)

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HV623

Pin Configuration

64-Pin PG Package

Pin Function

1HV 2HV 3HV 4HV 5HV 6HV 7HV 8HV 9HV 10 HV 11 HV 12 HV 13 HV 14 HV 15 HV 16 HV

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 HVGND 18 V

19 V

20 N/C 21 V

(Analog)*

22 CSI

Pin Function

23 N/C 24 V 25 R 26 SC (Shift Clock) 27 LVGND 28 DIR 29 V 30 D 31 D 32 D 33 D 34 D 35 D 36 D 37 N/C 38 LVGND 39 N/C 40 LC (Load Count) 41 N/C 42 CC (Count Clock) 43 CSO 44 N/C

CTL

(Digital)*

7 6 5 4 3 2 1

Pin Function

45 V

46 N/C 47 V

48 HVGND 49 HV 50 HV 51 HV 52 HV 53 HV 54 HV 55 HV 56 HV 57 HV 58 HV 59 HV 60 HV 61 HV 62 HV 63 HV 64 HV

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Package Outlines

Index

top view

25 40

3-Sided Plastic QFP 64-pin Gullwing Package

*Analog VDD and digital VDD may be connected

separately for better noise immunity.

Theory of Operation

The HV623 has two primary functions:

1) Loading data from the data bus and,

2) Gray-shade conversion

(converting latched data to output voltages).

Since the device was developed initially for flat panel displays, the operation will be described in terms that pertain to that technology. As shown by the Typical Drive Scheme, several HV623 packages are mounted at the top and bottom of a display panel. Data exists on a 7-bit bus (adjacent PC board traces) at top and bottom. The D1 through D7 inputs of each chip take data from the bus when either a CSI or CSO pulse is present at the chip. These pulses therefore act as a combination CHIP SELECT and LOCATION STROBE. Because of the way the chip HV sequenced, data on the bus at the bottom of the display panel will be entered into the left-most chip as HV

32. The CSI pulse will accomplish this with DIR = High.

OUT

OUT1, HVOUT2,

pins are

OUT

etc. up to

Loading Data from Data Bus

Here is the full data-entry sequence:

1) The microcontroller puts data on the bus (7 bits)

2) To enter the data into the 32 sets of 7 latches on the first chip, the shift clock rises. This positive transition is combined with the CSI pulse and is generated only once to strobe the data into the first set of latches. (These latches eventually send data to the HV falls, and this negative transition is combined with the CSI pulse, which is now propagated internally, to strobe the new data into the next set of 7 latches (which will end up as HV shift clock rate.

3) When the last set of 7 latches in the first chip has been loaded (HV exit pin is called CSO and the chip 2 entry pin is CSI . For chips at the top of the panel things are reversed: DIR is low, entry pins are CSO and exit pins are CSI , because the data-into-latches sequence is in descending order, HV

4) The buses may of course be separate, and data can be strobed in on an interleaved basis, etc., but those complications will be left to systems designers.

1). The data on the bus then changes, the shift clock

OUT

2). This internal CSI pulse therefore runs at twice the

OUT

32), the CSI pulse leaves chip 1 and enters chip 2. The

OUT

32 down to HV

OUT

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HV623

When data has been loaded into all 32 outputs of all chips (top and bottom of the display panel), the load count pin is pulsed. On its rising transition, all output levels are reset to zero and all the data in the input latches is transferred to a like number of comparator latches, (thus leaving the data latches ready to receive new data during the following operations). After the transfer, the load count pin is brought low. This transition begins the events that convert the binary data into a gray-shade level.

Gray-shade Conversion

1) The COUNT CLOCK is started. An external signal is applied to the COUNT CLOCK pin, causing the counter on each chip to increment from binary 000 0000 to 111 1111 (0 to 127).

2) At the same time, the V charging transistors, causing the HOLD CAPACITOR (C each output to experience a rise in voltage.

3) The logic control compares the count in the comparator latch to the count clock. The gate voltage of Q voltage HV

4) Once V

will ramp up at the same rate as VR.

OUT

has reached the maximum voltage, then all the pixels

will be at the final value. (See Output Gray Scale Voltage.)

voltage is applied to all chips, via

and the output

) on

Output Voltage Variation

The output voltage of the HV623 is determined by the logic and the ramp voltage V coupled to an unacceptable level due to its adjacent outputs through the panel. In order to solve this problem, internal logic (refer to Output Stage Detail) is integrated in the IC to minimize the effect.

Two external pins V current flowing through Q source and the R (2V and 56KΩ are used for a particular panel). The internal bias circuit will drive the resistor to a voltage level that is equal to the

voltage at steady state through an operational amplifier. The

CTL

current flowing through Q1 and Q2 will be limited to V This combination of V variation to less than ±0.2V of delta voltage for each gray shade, independent of its adjacent output voltages.

. It is possible that the output voltage may be

and R

CTL

pin is connected to ground through a resistor

CTL

allow the feasibility to control the

CTL

. The V

and R

pin is connected to a voltage

CTL

will reduce the output voltage

CTL

CTRL/RCTRL

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