❏HVCMOS® technology
❏5V CMOS inputs
❏Up to 80V output voltage
❏PWM gray shade conversion
❏Capable of 256 levels of gray shading
❏Balanced shift clock complies with RS-422
❏8MHz shift and count clock frequency
❏16MHz data throughput rate
❏8 bit data bus
❏32 outputs per device
❏BLANK function
Absolute Maximum Ratings
Supply voltage, V
Supply voltage, V
Supply voltage, V
Logic input levels-0.5 to VDD + 0.5V
Continuous total power dissipation1.2W
Operating temperature range-40°C to +85°C
Storage temperature range-65°C to +150°C
Notes:
All voltages are referenced to GND.
Maximum V
For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.
PP
DD
PP
NN
to VNN voltage is 90V.
-0.5V to +7.5V
-0.5V to +80V
-15V to 0V
General Description
Not recommended for new designs. Please use HV632 instead.
The HV622 is a 32-channel gray-shade column driver IC designed for driving electrofluorescent displays. Using Supertex’s
unique HVCMOS
shading by PWM conversion.
The shift clock is a balanced clock with electrical characteristics
complying with EIA RS-422 standard. Input data, in groups of
eight, is latched into a set of data latches on both edges of the shift
clock. The data shifted in the first data latch corresponds to
1, the second data latch corresponds to HV
HV
OUT
These data are compared to the contents of the master binary
counter which counts on both edges of the count clock. Each time
the master counter begins to decrement from 1111 1111, the data
in the data latches are compared with the contents of the counter;
if they match, the corresponding outputs will go high. The master
counter counts down to 0000 0001 and then starts to count up
again. The outputs that are at high will stay at high until the
contents of the counter match the data in the data latches again.
Therefore, the higher the binary data in the data latches, the
longer the outputs will stay at high. Thus, different high voltage
pulse widths are produced. When the counter reaches its
1111 1111 count while counting up, the device is ready for the
next operation cycle. A data value of 0000 0000 produces no
pulse; the output stays low.
The BLANK input signal will reset the master counter to all ones
(1111 1111) and set all high voltage outputs to low.
®
technology, it is capable of 256 levels of gray
2, and so on.
OUT
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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Electrical Characteristics
(Over recommended conditions of VDD = 5V, VPP = 70V, VNN = -10V, TA = 25°C unless otherwise noted)
Low-Voltage DC Characteristics (Digital)
SymbolParameterMinMaxUnitsConditions
V
DD
I
DD
I
DDQ
I
IH
I
IL
I
OH
I
OL
Low-Voltage DC Characteristics (Analog)
SymbolParameterMinMaxUnitsConditions
V
DD
I
DD
I
DDQ
Low-voltage digital supply voltage4.55.5V
VDD supply current25mAfSC = 8MHz, fCC = 8MHz
Quiescent VDD supply current100µAAll VIN = GND, Count Clock = V
High-level input current10µAVIN = V
Shift clock frequency8.0MHz
Count clock frequency8.0MHz
Data In frequency16MHz
Chip select pulse width80ns
Chip select to shift clock set-up time15ns
Chip select to shift clock hold time45ns
Shift clock cycle time125ns
Data to shift clock set-up time10ns
Data to shift clock hold time52ns
Data In pulse width62ns
Load count pulse width75ns
Count clock pulse width62.5ns
Count clock cycle time125ns
Load count to count clock delay100ns
Count clock to HV
turn-on/turn-off600nsCL = 15pF
OUT
BLANK pulse width700ns
BLANK to HV
delay500nsCL = 15pF
OUT
Count clock delay between count down and500ns
count up cycles
V
Shift clock frequency8MHz
Count clock frequency8MHz
Operating temperature-40+85°C
Pin Definitions
Pin #NameI/OFunction
27-30D1 – D8IInputs for binary-format parallel data
36-29(D8 is the most significant bit)
34Shift ClockITriggers data on both edges
35Shift ClockITriggers data on both edges
31Count ClockIInput to the counter
24CSIIChip select input to enable the device to accept data
25CSOOChip select output to enable the next device
33Load CountIInput to initiate the counting
26BlankIInput to reset the counter and HV