Page 1
100 MHz, 80-Channel Serial To Parallel Converter
With Push-Pull Outputs
Ordering Information
Package Options
Device 100 Lead Quad
Plastic Gullwing Die
HV574 HV574PG HV574X
HV574
Features
❏ Processed with HVCMOS® technology
❏ 5V CMOS logic
❏ Output voltages up to 80V
❏ Low power level shifting
❏ 100MHz equivalent data rate using four dynamic
shift registers
❏ Static latched data outputs
❏ Forward and reverse shifting options (DIR pin)
❏ Diode to V
❏ Outputs may be hot switched
❏ Hi-Rel processing available
allows efficient power recovery
PP
Absolute Maximum Ratings
Supply voltage, V
Output voltage, V
Logic input levels
Ground current
Continuous total power dissipation
Operating temperature range -40 to 85°C
Storage temperature range -65°C to +150°C
Lead temperature 1.6mm (1/16 inch) 260°C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. Limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.
1
DD
1
PP
1
2
3
-0.5V to +7.5V
-0.5V to +90V
-0.3V to VDD +0.3V
1.5A
1200mW
General Description
The HV574 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for
use as a driver for printer applications. It can also be used in any
application requiring multiple output high-voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays.
The device has 4 parallel 20-bit dynamic shift registers, permitting
data rates 4X the speed of one ( they are clocked together).
There are 80 static latches and control logic to perform the polarity
select and blanking of the outputs. HV
stage of the first shift register through the polarity and blanking
logic. Data is shifted through the shift registers on the logic low to
high transition of the clock. The DIR pin causes CCW shifting
when connected to GND, and CW shifting when connected to
. A data output buffer is provided for cascading devices. This
V
DD
output reflects the current status of the last bit of the shift register
(HV
80). Operation of the shift register is not affected by the LE
OUT
(latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the
LE (latch enable) input is high. The data in the latches is stored
when LE is low.
1 is connected to the first
OUT
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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Electrical Characteristics (over recommended commercial operating conditions unless noted)
DC Characteristics
Symbol Parameter Min Max Units Conditions
I
I
I
DDQ
V
V
I
I
VDD supply current 30 mA VDD = VDD max
DD
Quiescent VPP supply current 100 µA Outputs high
PP
100 µA Outputs low
Quiescent VDD supply current 100 µA All VIN = V
High-level output HV
OH
Low-level output HV
OL
V
OUT
Data out V
3.75 V IO = 15mA, V
OUT
- 9V V IO= -30mA, V
PP
- 0.5 V IO= -100µA
DD
Data out 0.5 V IO= 100µA
High-level logic input current 1.0 µAVIH = V
IH
Low-level logic input current -1.0 µAVIL = 0V
IL
= 25MHz
f
CLK
DD
PP
DD
DD
HV574
= 80V
= 5V
AC Characteristics (T
= 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points])
A
Symbol Parameter Min Max Units Conditions
f
CLK
tWL,t
WH
t
SU
t
H
tON, t
OFF
t
DHL
t
DLH
t
* Delay time clock to LE low to high 25 ns
DLE
t
WLE
t
SLE
Clock frequency 0.001 25
0.001 20 V
MHz
VDD = 4.5V, TJ = 25°C
= 4.5V, TJ = 125°C
DD
Clock width high or low 20 ns
Data set-up time before clock rises 0 ns
Data hold time after clock rises 15 ns
Time from latch enable to HV
OUT
500 ns CL = 15pF
Delay time clock to data high to low 38 ns CL = 15pF, VDD = 5.0V
Delay time clock to data low to high 38 ns CL = 15pF, VDD = 5.0V
Width of LE pulse 25 ns
LE set-up time before clock rises 0 ns
tr, tf Output rise/fall time 1.0 µsCL = 600pF,
HV
from 0 to 60V
OUT
t
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
*
DLE
Recommended Operating Conditions
Symbol Parameter Min Max Units
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Notes: Power-up sequence should be the following:
1. Connect ground.
2. Apply V
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
5. The V
Power-down sequence should be the reverse of the above.
The V
should not drop below VDD during operation.
PP
.
DD
.
PP
should not drop below VDD or float during operation.
PP
Logic supply voltage 4.5 5.5 V
Output voltage 12 80 V
High-level input voltage VDD -0.5V V
Low-level input voltage 0 0.5 V
Clock frequency per register 0.001 25 MHz
Operating free-air temperature -40 +85 °C
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Input and Output Equivalent Circuits
HV574
V
DD
Input
GND
Logic Inputs
Switching Waveforms
Clock
Data Out
50% 50%
t
WL
V
GND
DD
t
SU
Logic Data Output
Data Valid Data Valid50%Data Input
t
DLH
t
DHL
Data Out
t
WH
V
PP
HV
OUT
GND
High Voltage Outputs
V
IH
V
IL
t
H
V
IH
50%
50%
V
IL
V
OH
50%
V
OL
V
50%
OH
V
OL
Latch Enable
HV
OUT
w/ S/R LOW
HV
OUT
w/ S/R HIGH
3
t
DLE
50%
t
OFF
10%
t
ON
t
WLE
90%
t
f
t
r
10%
90%
50%
t
SLE
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
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Functional Block Diagram
HV574
D
D
D
DIR
D
IN
OUT
CLK
D
IN
OUT
D
IN
OUT
V
DD
A
A
B
B
C
C
20-bit
shift
register
20-bit
shift
register
20-bit
shift
register
BLLE
POL V
PP
HV
HV
HV
HV
HV
HV
OUT
OUT
OUT
OUT
OUT
OUT
1
20
21
40
41
60
D
D
IN
OUT
HV
61
OUT
D
D
20-bit
shift
register
HV
OUT
80
GND
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Function Table
Inputs Outputs
Function Shift Reg HV Outputs Data Out
All O/P High X X X L L X H
All O/P Low X X X L H X L
O/P Normal X X X H H X No inversion
O/P Inverted X X X H L X Inversion
Data Falls
Through
(Latches
Transparent)
Data Stored/
Latches Loaded
I/O Relation
Notes: * = dependent on previous stage’s state. See Pin configuration for DIN and D
Data CLK LE BL POL DIR
L ↑ HHHX L L
H ↑ HHHX H H
L ↑ HHLX L H
H ↑ HHLX H L
XXLHHX * Stored Data
XXLHLX * Inversion of
Stored Data
X ↑ HHHHQ
D
IN
D
X ↑ LHHHQ
IN
→ Q
n
→ Q
n
n +1
n +1
New H or L D
Previous D
H or L
D
X ↑ LHHLQ
OUT
→ Q
n
n -1
Previous DINX
H or L
D
X ↑ HHHLQ
OUT
pin designation for CW and CCW shift.
OUT
→ Q
n
n -1
New H or L DINX
OUT
OUT
HV574
X
X
Pin Configuration
100-Pin PG Package
Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 HV
19 HV
20 HV
21 HV
22 HV
23 HV
24 HV
25 HV
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Pin Function
26 HV
27 HV
28 HV
29 HV
30 HV
OUT
OUT
OUT
OUT
OUT
5
4
3
2
1
31 N/C
32 V
PP
33 HVGND
34 D
35 D
36 D
37 D
38 V
IN
IN
IN
IN
DD
A
B
C
D
39 POL
40 LE
41 CLK
42 DIR
43 BL
44 GND
45 D
46 D
47 D
48 D
OUT
OUT
OUT
OUT
D
C
B
A
49 HVGND
50 V
PP
Pin Function
51 HV
52 HV
53 HV
54 HV
55 HV
56 HV
57 HV
58 HV
59 HV
60 HV
61 HV
62 HV
63 HV
64 HV
65 HV
66 HV
67 HV
68 HV
69 HV
70 HV
71 HV
72 HV
73 HV
74 HV
75 HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
Pin Function
76 HV
77 HV
78 HV
OUT
OUT
OUT
55
54
53
79 HVout52
80 HV
81 HV
82 HV
83 HV
84 HV
85 HV
86 HV
87 HV
88 HV
89 HV
90 HV
91 HV
92 HV
93 HV
94 HV
95 HV
96 HV
97 HV
98 HV
99 HV
100 HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
5
Package Outlines
100
1
30
31
top view
100-Lead Plastic Quad Flat Package
("Gullwing" Package)
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
81
50
11/12/01
www.supertex.com
80
51
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